[ARM] Allow selecting VRINT[APMXZR] and VCVT[BT] instructions for FPv5

[olista01]

Summary

Currently, we only codegen the VRINT[APMXZR] and VCVT[BT] instructions when targeting ARMv8, but they are actually present on any target with FP-ARMv8. Note that FP-ARMv8 is called FPv5 when is is part of an M-profile core, but they have the same instructions so we model them both FPARMv8 in the ARM backend.

[rengolin]

LGTM, thanks!

[olista01]

Committed revision 218763.

lib/Target/ARM/ARMISelLowering.cpp

if (!TM.Options.UseSoftFloat && !Subtarget->isThumb1Only()) {
     // int <-> fp are custom expanded into bit_convert + ARMISD ops.
     if (Subtarget->hasVFP2()) {
       setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
       setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
       setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
       setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
     }
 
-    // v8 adds f64 <-> f16 conversion. Before that it should be expanded.
-    if (!Subtarget->hasV8Ops()) {
+    // FP-ARMv8 adds f64 <-> f16 conversion. Before that it should be expanded.
+    if (!Subtarget->hasFPARMv8() || Subtarget->isFPOnlySP()) {
       setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
       setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
     }
 
     // fp16 is a special v7 extension that adds f16 <-> f32 conversions.
     if (!Subtarget->hasFP16()) {
       setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
       setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
     }
   }
 
   // Combine sin / cos into one node or libcall if possible.
   if (Subtarget->hasSinCos()) {
     setLibcallName(RTLIB::SINCOS_F32, "sincosf");
     setLibcallName(RTLIB::SINCOS_F64, "sincos");
     if (Subtarget->getTargetTriple().getOS() == Triple::IOS) {
       // For iOS, we don't want to the normal expansion of a libcall to
       // sincos. We want to issue a libcall to __sincos_stret.
       setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
       setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
     }
   }
 
-  // ARMv8 implements a lot of rounding-like FP operations.
-  if (Subtarget->hasV8Ops()) {
-    static MVT RoundingTypes[] = {MVT::f32, MVT::f64};
-    for (const auto Ty : RoundingTypes) {
-      setOperationAction(ISD::FFLOOR, Ty, Legal);
-      setOperationAction(ISD::FCEIL, Ty, Legal);
-      setOperationAction(ISD::FROUND, Ty, Legal);
-      setOperationAction(ISD::FTRUNC, Ty, Legal);
-      setOperationAction(ISD::FNEARBYINT, Ty, Legal);
-      setOperationAction(ISD::FRINT, Ty, Legal);
+  // FP-ARMv8 implements a lot of rounding-like FP operations.
+  if (Subtarget->hasFPARMv8()) {
+    setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
+    setOperationAction(ISD::FCEIL, MVT::f32, Legal);
+    setOperationAction(ISD::FROUND, MVT::f32, Legal);
+    setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
+    setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
+    setOperationAction(ISD::FRINT, MVT::f32, Legal);
+    if (!Subtarget->isFPOnlySP()) {
+      setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
+      setOperationAction(ISD::FCEIL, MVT::f64, Legal);
+      setOperationAction(ISD::FROUND, MVT::f64, Legal);
+      setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
+      setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
+      setOperationAction(ISD::FRINT, MVT::f64, Legal);
     }
   }
   // We have target-specific dag combine patterns for the following nodes:
   // ARMISD::VMOVRRD  - No need to call setTargetDAGCombine
   setTargetDAGCombine(ISD::ADD);
   setTargetDAGCombine(ISD::SUB);
   setTargetDAGCombine(ISD::MUL);
   setTargetDAGCombine(ISD::AND);

test/CodeGen/ARM/arm32-rounding.ll

-; RUN: llc < %s -mtriple=armv8-linux-gnueabihf -mattr=+fp-armv8 | FileCheck %s
+; RUN: llc < %s -mtriple=armv8-linux-gnueabihf -mattr=+fp-armv8 | FileCheck --check-prefix=CHECK --check-prefix=DP %s
+; RUN: llc < %s -mtriple=thumbv7em-linux-gnueabihf -mattr=+fp-armv8,+d16,+fp-only-sp | FileCheck --check-prefix=SP %s
+; RUN: llc < %s -mtriple=thumbv7em-linux-gnueabihf -mattr=+fp-armv8,+d16 | FileCheck --check-prefix=DP %s
 
 ; CHECK-LABEL: test1
 ; CHECK: vrintm.f32
 define float @test1(float %a) {
 entry:
   %call = call float @floorf(float %a) nounwind readnone
   ret float %call
 }
 
 ; CHECK-LABEL: test2
-; CHECK: vrintm.f64
+; SP: b floor
+; DP: vrintm.f64
 define double @test2(double %a) {
 entry:
   %call = call double @floor(double %a) nounwind readnone
   ret double %call
 }
 
 ; CHECK-LABEL: test3
 ; CHECK: vrintp.f32
 define float @test3(float %a) {
 entry:
   %call = call float @ceilf(float %a) nounwind readnone
   ret float %call
 }
 
 ; CHECK-LABEL: test4
-; CHECK: vrintp.f64
+; SP: b ceil
+; DP: vrintp.f64
 define double @test4(double %a) {
 entry:
   %call = call double @ceil(double %a) nounwind readnone
   ret double %call
 }
 
 ; CHECK-LABEL: test5
 ; CHECK: vrinta.f32
 define float @test5(float %a) {
 entry:
   %call = call float @roundf(float %a) nounwind readnone
   ret float %call
 }
 
 ; CHECK-LABEL: test6
-; CHECK: vrinta.f64
+; SP: b round
+; DP: vrinta.f64
 define double @test6(double %a) {
 entry:
   %call = call double @round(double %a) nounwind readnone
   ret double %call
 }
 
 ; CHECK-LABEL: test7
 ; CHECK: vrintz.f32
 define float @test7(float %a) {
 entry:
   %call = call float @truncf(float %a) nounwind readnone
   ret float %call
 }
 
 ; CHECK-LABEL: test8
-; CHECK: vrintz.f64
+; SP: b trunc
+; DP: vrintz.f64
 define double @test8(double %a) {
 entry:
   %call = call double @trunc(double %a) nounwind readnone
   ret double %call
 }
 
 ; CHECK-LABEL: test9
 ; CHECK: vrintr.f32
 define float @test9(float %a) {
 entry:
   %call = call float @nearbyintf(float %a) nounwind readnone
   ret float %call
 }
 
 ; CHECK-LABEL: test10
-; CHECK: vrintr.f64
+; SP: b nearbyint
+; DP: vrintr.f64
 define double @test10(double %a) {
 entry:
   %call = call double @nearbyint(double %a) nounwind readnone
   ret double %call
 }
 
 ; CHECK-LABEL: test11
 ; CHECK: vrintx.f32
 define float @test11(float %a) {
 entry:
   %call = call float @rintf(float %a) nounwind readnone
   ret float %call
 }
 
 ; CHECK-LABEL: test12
-; CHECK: vrintx.f64
+; SP: b rint
+; DP: vrintx.f64
 define double @test12(double %a) {
 entry:
   %call = call double @rint(double %a) nounwind readnone
   ret double %call
 }
 
 declare float @floorf(float) nounwind readnone
 declare double @floor(double) nounwind readnone

test/CodeGen/Thumb2/float-intrinsics-double.ll

-; RUN: llc < %s -mtriple=thumbv7-none-eabi   -mcpu=cortex-m3 | FileCheck %s -check-prefix=CHECK -check-prefix=SOFT -check-prefix=NONE
-; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m4 | FileCheck %s -check-prefix=CHECK -check-prefix=SOFT -check-prefix=SP
-; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m7 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP -check-prefix=VFP
-; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-a7 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP -check-prefix=NEON
+; RUN: llc < %s -mtriple=thumbv7-none-eabi   -mcpu=cortex-m3                    | FileCheck %s -check-prefix=CHECK -check-prefix=SOFT -check-prefix=NONE
+; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m4                    | FileCheck %s -check-prefix=CHECK -check-prefix=SOFT -check-prefix=SP
+; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m7                    | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP -check-prefix=VFP  -check-prefix=FP-ARMv8
+; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m7 -mattr=+fp-only-sp | FileCheck %s -check-prefix=CHECK -check-prefix=SOFT -check-prefix=SP
+; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-a7                    | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP -check-prefix=NEON -check-prefix=VFP4
+; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-a57                   | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP -check-prefix=NEON -check-prefix=FP-ARMv8
 
 declare double     @llvm.sqrt.f64(double %Val)
 define double @sqrt_d(double %a) {
 ; CHECK-LABEL: sqrt_d:
 ; SOFT: {{(bl|b)}} sqrt
 ; HARD: vsqrt.f64 d0, d0
   %1 = call double @llvm.sqrt.f64(double %a)
   ret double %1
; NEON: vbsl [[REG]], d
   %1 = call double @llvm.copysign.f64(double %a, double %b)
   ret double %1
 }
 
 declare double     @llvm.floor.f64(double %Val)
 define double @floor_d(double %a) {
 ; CHECK-LABEL: floor_d:
 ; SOFT: {{(bl|b)}} floor
-; HARD: b floor
+; VFP4: b floor
+; FP-ARMv8: vrintm.f64
   %1 = call double @llvm.floor.f64(double %a)
   ret double %1
 }
 
 declare double     @llvm.ceil.f64(double %Val)
 define double @ceil_d(double %a) {
 ; CHECK-LABEL: ceil_d:
 ; SOFT: {{(bl|b)}} ceil
-; HARD: b ceil
+; VFP4: b ceil
+; FP-ARMv8: vrintp.f64
   %1 = call double @llvm.ceil.f64(double %a)
   ret double %1
 }
 
 declare double     @llvm.trunc.f64(double %Val)
 define double @trunc_d(double %a) {
 ; CHECK-LABEL: trunc_d:
 ; SOFT: {{(bl|b)}} trunc
-; HARD: b trunc
+; FFP4: b trunc
+; FP-ARMv8: vrintz.f64
   %1 = call double @llvm.trunc.f64(double %a)
   ret double %1
 }
 
 declare double     @llvm.rint.f64(double %Val)
 define double @rint_d(double %a) {
 ; CHECK-LABEL: rint_d:
 ; SOFT: {{(bl|b)}} rint
-; HARD: b rint
+; VFP4: b rint
+; FP-ARMv8: vrintx.f64
   %1 = call double @llvm.rint.f64(double %a)
   ret double %1
 }
 
 declare double     @llvm.nearbyint.f64(double %Val)
 define double @nearbyint_d(double %a) {
 ; CHECK-LABEL: nearbyint_d:
 ; SOFT: {{(bl|b)}} nearbyint
-; HARD: b nearbyint
+; VFP4: b nearbyint
+; FP-ARMv8: vrintr.f64
   %1 = call double @llvm.nearbyint.f64(double %a)
   ret double %1
 }
 
 declare double     @llvm.round.f64(double %Val)
 define double @round_d(double %a) {
 ; CHECK-LABEL: round_d:
 ; SOFT: {{(bl|b)}} round
-; HARD: b round
+; VFP4: b round
+; FP-ARMv8: vrinta.f64
   %1 = call double @llvm.round.f64(double %a)
   ret double %1
 }
 
 declare double     @llvm.fmuladd.f64(double %a, double %b, double %c)
 define double @fmuladd_d(double %a, double %b, double %c) {
 ; CHECK-LABEL: fmuladd_d:
 ; SOFT: bl __aeabi_dmul
 ; SOFT: bl __aeabi_dadd
-; NEON: vmul.f64
-; NEON: vadd.f64
-; VFP: vmla.f64
+; VFP4: vmul.f64
+; VFP4: vadd.f64
+; FP-ARMv8: vmla.f64
   %1 = call double @llvm.fmuladd.f64(double %a, double %b, double %c)
   ret double %1
 }
 
 declare i16 @llvm.convert.to.fp16.f64(double %a)
 define i16 @d_to_h(double %a) {
 ; CHECK-LABEL: d_to_h:
 ; SOFT: bl __aeabi_d2h
-; HARD: bl __aeabi_d2h
+; VFP4: bl __aeabi_d2h
+; FP-ARMv8: vcvt{{[bt]}}.f16.f64
   %1 = call i16 @llvm.convert.to.fp16.f64(double %a)
   ret i16 %1
 }
 
 declare double @llvm.convert.from.fp16.f64(i16 %a)
 define double @h_to_d(i16 %a) {
 ; CHECK-LABEL: h_to_d:
 ; NONE: bl __gnu_h2f_ieee
 ; NONE: bl __aeabi_f2d
-; SP: vcvtb.f32.f16
+; SP: vcvt{{[bt]}}.f32.f16
 ; SP: bl __aeabi_f2d
-; DP: vcvtb.f32.f16
-; DP: vcvt.f64.f32
+; VFPv4: vcvt{{[bt]}}.f32.f16
+; VFPv4: vcvt.f64.f32
+; FP-ARMv8: vcvt{{[bt]}}.f64.f16
   %1 = call double @llvm.convert.from.fp16.f64(i16 %a)
   ret double %1
 }

test/CodeGen/Thumb2/float-intrinsics-float.ll

-; RUN: llc < %s -mtriple=thumbv7-none-eabi   -mcpu=cortex-m3 | FileCheck %s -check-prefix=CHECK -check-prefix=SOFT -check-prefix=NONE
-; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m4 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=SP
-; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m7 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP -check-prefix=VFP
-; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-a7 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP -check-prefix=NEON
+; RUN: llc < %s -mtriple=thumbv7-none-eabi   -mcpu=cortex-m3                    | FileCheck %s -check-prefix=CHECK -check-prefix=SOFT -check-prefix=NONE
+; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m4                    | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=SP -check-prefix=VMLA
+; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m7                    | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP -check-prefix=VFP  -check-prefix=FP-ARMv8  -check-prefix=VMLA
+; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m7 -mattr=+fp-only-sp | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=SP -check-prefix=FP-ARMv8 -check-prefix=VMLA
+; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-a7                    | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP -check-prefix=NEON -check-prefix=VFP4 -check-prefix=NO-VMLA
+; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-a57                   | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP -check-prefix=NEON -check-prefix=FP-ARMv8 -check-prefix=VMLA
 
 declare float     @llvm.sqrt.f32(float %Val)
 define float @sqrt_f(float %a) {
 ; CHECK-LABEL: sqrt_f:
 ; SOFT: bl sqrtf
 ; HARD: vsqrt.f32 s0, s0
   %1 = call float @llvm.sqrt.f32(float %a)
   ret float %1
; NEON: vbsl [[REG]], d
   %1 = call float @llvm.copysign.f32(float %a, float %b)
   ret float %1
 }
 
 declare float     @llvm.floor.f32(float %Val)
 define float @floor_f(float %a) {
 ; CHECK-LABEL: floor_f:
 ; SOFT: bl floorf
-; HARD: b floorf
+; VFP4: b floorf
+; FP-ARMv8: vrintm.f32
   %1 = call float @llvm.floor.f32(float %a)
   ret float %1
 }
 
 declare float     @llvm.ceil.f32(float %Val)
 define float @ceil_f(float %a) {
 ; CHECK-LABEL: ceil_f:
 ; SOFT: bl ceilf
-; HARD: b ceilf
+; VFP4: b ceilf
+; FP-ARMv8: vrintp.f32
   %1 = call float @llvm.ceil.f32(float %a)
   ret float %1
 }
 
 declare float     @llvm.trunc.f32(float %Val)
 define float @trunc_f(float %a) {
 ; CHECK-LABEL: trunc_f:
 ; SOFT: bl truncf
-; HARD: b truncf
+; VFP4: b truncf
+; FP-ARMv8: vrintz.f32
   %1 = call float @llvm.trunc.f32(float %a)
   ret float %1
 }
 
 declare float     @llvm.rint.f32(float %Val)
 define float @rint_f(float %a) {
 ; CHECK-LABEL: rint_f:
 ; SOFT: bl rintf
-; HARD: b rintf
+; VFP4: b rintf
+; FP-ARMv8: vrintx.f32
   %1 = call float @llvm.rint.f32(float %a)
   ret float %1
 }
 
 declare float     @llvm.nearbyint.f32(float %Val)
 define float @nearbyint_f(float %a) {
 ; CHECK-LABEL: nearbyint_f:
 ; SOFT: bl nearbyintf
-; HARD: b nearbyintf
+; VFP4: b nearbyintf
+; FP-ARMv8: vrintr.f32
   %1 = call float @llvm.nearbyint.f32(float %a)
   ret float %1
 }
 
 declare float     @llvm.round.f32(float %Val)
 define float @round_f(float %a) {
 ; CHECK-LABEL: round_f:
 ; SOFT: bl roundf
-; HARD: b roundf
+; VFP4: b roundf
+; FP-ARMv8: vrinta.f32
   %1 = call float @llvm.round.f32(float %a)
   ret float %1
 }
 
 ; FIXME: why does cortex-m4 use vmla, while cortex-a7 uses vmul+vadd?
 ; (these should be equivalent, even the rounding is the same)
 declare float     @llvm.fmuladd.f32(float %a, float %b, float %c)
 define float @fmuladd_f(float %a, float %b, float %c) {
 ; CHECK-LABEL: fmuladd_f:
 ; SOFT: bl __aeabi_fmul
 ; SOFT: bl __aeabi_fadd
-; SP: vmla.f32
-; VFP: vmla.f32
-; NEON: vmul.f32
-; NEON: vadd.f32
+; VMLA: vmla.f32
+; NO-VMLA: vmul.f32
+; NO-VMLA: vadd.f32
   %1 = call float @llvm.fmuladd.f32(float %a, float %b, float %c)
   ret float %1
 }
 
 declare i16 @llvm.convert.to.fp16.f32(float %a)
 define i16 @f_to_h(float %a) {
 ; CHECK-LABEL: f_to_h:
 ; SOFT: bl __gnu_f2h_ieee
-; HARD: vcvtb.f16.f32
+; HARD: vcvt{{[bt]}}.f16.f32
   %1 = call i16 @llvm.convert.to.fp16.f32(float %a)
   ret i16 %1
 }
 
 declare float @llvm.convert.from.fp16.f32(i16 %a)
 define float @h_to_f(i16 %a) {
 ; CHECK-LABEL: h_to_f:
 ; SOFT: bl __gnu_h2f_ieee
-; HARD: vcvtb.f32.f16
+; HARD: vcvt{{[bt]}}.f32.f16
   %1 = call float @llvm.convert.from.fp16.f32(i16 %a)
   ret float %1
 }