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Differential D55178

AMDGPU: Add f32 vectors to SGPR register classes
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Authored by arsenm on Dec 2 2018, 12:51 PM.

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nhaehnle
rampitec

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arsenm created this revision.Dec 2 2018, 12:51 PM
Herald added subscribers: t-tye, tpr, dstuttard and 4 others. · View Herald TranscriptDec 2 2018, 12:51 PM
rampitec accepted this revision.Dec 2 2018, 2:57 PM

LGTM

This revision is now accepted and ready to land.Dec 2 2018, 2:57 PM
arsenm closed this revision.Dec 4 2018, 9:54 AM

r348286

Revision Contents

PathSize
lib/
Target/
AMDGPU/
12 lines

Diff 176293

lib/Target/AMDGPU/SIRegisterInfo.td

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} }
// Register class for all scalar registers (SGPRs + Special Registers) // Register class for all scalar registers (SGPRs + Special Registers)
def SReg_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32, def SReg_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,
(add SReg_32_XM0, M0_CLASS, EXEC_LO, EXEC_HI, SReg_32_XEXEC_HI)> { (add SReg_32_XM0, M0_CLASS, EXEC_LO, EXEC_HI, SReg_32_XEXEC_HI)> {
let AllocationPriority = 7; let AllocationPriority = 7;
} }
def SGPR_64 : RegisterClass<"AMDGPU", [v2i32, i64, f64, v4i16, v4f16], 32, (add SGPR_64Regs)> { def SGPR_64 : RegisterClass<"AMDGPU", [v2i32, i64, v2f32, f64, v4i16, v4f16], 32, (add SGPR_64Regs)> {
let CopyCost = 1; let CopyCost = 1;
let AllocationPriority = 8; let AllocationPriority = 8;
} }
def TTMP_64 : RegisterClass<"AMDGPU", [v2i32, i64, f64, v4i16, v4f16], 32, (add TTMP_64Regs)> { def TTMP_64 : RegisterClass<"AMDGPU", [v2i32, i64, f64, v4i16, v4f16], 32, (add TTMP_64Regs)> {
let isAllocatable = 0; let isAllocatable = 0;
} }
def SReg_64_XEXEC : RegisterClass<"AMDGPU", [v2i32, i64, f64, i1, v4i16, v4f16], 32, def SReg_64_XEXEC : RegisterClass<"AMDGPU", [v2i32, i64, v2f32, f64, i1, v4i16, v4f16], 32,
(add SGPR_64, VCC, FLAT_SCR, XNACK_MASK, TTMP_64, TBA, TMA)> { (add SGPR_64, VCC, FLAT_SCR, XNACK_MASK, TTMP_64, TBA, TMA)> {
let CopyCost = 1; let CopyCost = 1;
let AllocationPriority = 8; let AllocationPriority = 8;
} }
def SReg_64 : RegisterClass<"AMDGPU", [v2i32, i64, f64, i1, v4i16, v4f16], 32, def SReg_64 : RegisterClass<"AMDGPU", [v2i32, i64, v2f32, f64, i1, v4i16, v4f16], 32,
(add SReg_64_XEXEC, EXEC)> { (add SReg_64_XEXEC, EXEC)> {
let CopyCost = 1; let CopyCost = 1;
let AllocationPriority = 8; let AllocationPriority = 8;
} }
// Requires 2 s_mov_b64 to copy // Requires 2 s_mov_b64 to copy
let CopyCost = 2 in { let CopyCost = 2 in {
def SGPR_128 : RegisterClass<"AMDGPU", [v4i32, v16i8, v2i64], 32, (add SGPR_128Regs)> { def SGPR_128 : RegisterClass<"AMDGPU", [v4i32, v4f32, v16i8, v2i64], 32, (add SGPR_128Regs)> {
let AllocationPriority = 10; let AllocationPriority = 10;
} }
def TTMP_128 : RegisterClass<"AMDGPU", [v4i32, v16i8, v2i64], 32, (add TTMP_128Regs)> { def TTMP_128 : RegisterClass<"AMDGPU", [v4i32, v4f32, v16i8, v2i64], 32, (add TTMP_128Regs)> {
let isAllocatable = 0; let isAllocatable = 0;
} }
def SReg_128 : RegisterClass<"AMDGPU", [v4i32, v16i8, v2i64, v2f64], 32, def SReg_128 : RegisterClass<"AMDGPU", [v4i32, v4f32, v16i8, v2i64, v2f64], 32,
(add SGPR_128, TTMP_128)> { (add SGPR_128, TTMP_128)> {
let AllocationPriority = 10; let AllocationPriority = 10;
} }
} // End CopyCost = 2 } // End CopyCost = 2
def SGPR_256 : RegisterClass<"AMDGPU", [v8i32, v8f32], 32, (add SGPR_256Regs)> { def SGPR_256 : RegisterClass<"AMDGPU", [v8i32, v8f32], 32, (add SGPR_256Regs)> {
let AllocationPriority = 11; let AllocationPriority = 11;
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