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[ARM][MC] Move information about variadic register defs into tablegen

Authored by olista01 on Nov 23 2018, 3:37 AM.



Currently, variadic operands on an MCInst are assumed to be uses,
because they come after the defs. However, this is not always the case,
for example the Arm/Thumb LDM instructions write to a variable number of

This adds a property of instruction definitions which can be used to
mark variadic operands as defs. This only affects MCInst, because
MachineInstruction already tracks use/def per operand in each instance
of the instruction, so can already represent this.

This property can then be checked in MCInstrDesc, allowing us to remove
some special cases in ARMAsmParser::isITBlockTerminator.

Diff Detail


Event Timeline

olista01 created this revision.Nov 23 2018, 3:37 AM
olista01 updated this revision to Diff 175225.Nov 26 2018, 3:52 AM

Remove special case in MCInstrDesc::mayAffectControlFlow, which is no longer needed.

Nice clean solution, thanks!

I wonder if there are tests that could expose the behaviour but is still consistent enough that won't change from other code-gen updates.

I can't think of any general way to test this, because these properties of MCInsts are not used much. The Thumb instructions which this applies to are tested by test/MC/ARM/implicit-it-generation.s, which has a big list of PC-writing instructions which cannot be used in the middle of an IT block, this patch is NFC for them.

rengolin accepted this revision.Dec 3 2018, 2:06 AM

Right, that one is a hairy test, and I can see how this would break that test if not right. :)

LGTM, thanks!

This revision is now accepted and ready to land.Dec 3 2018, 2:06 AM
This revision was automatically updated to reflect the committed changes.