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[SelectionDAG] Compute known bits and num sign bits for live out vector registers. Use it to add AssertZExt/AssertSExt in the live in basic blocks
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Authored by craig.topper on Nov 19 2018, 2:13 PM.

Details

Summary

We already support this for scalars, but it was explicitly disabled for vectors. In the updated test cases this allows us to see the upper bits are zero to use less multiply instructions to emulate a 64 bit multiply.

This should help with this ispc issue that a coworker pointed me to https://github.com/ispc/ispc/issues/1362

Diff Detail

Event Timeline

craig.topper created this revision.Nov 19 2018, 2:13 PM

Does this patch do anything for PR11730?
https://bugs.llvm.org/show_bug.cgi?id=11730

If so, it would be good to add a test based on that.

lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
700

Code comment isn't correct now.

Update comment

This doesn't help PR11730 at all.

spatel accepted this revision.Nov 19 2018, 6:00 PM

This doesn't help PR11730 at all.

Ok, thanks for checking. LGTM.

This revision is now accepted and ready to land.Nov 19 2018, 6:00 PM
This revision was automatically updated to reflect the committed changes.