[mips][mc] Add basic support for R_MIPS_JALR/R_MICROMIPS_JALR

[vstefanovic]

Summary

R_MIPS_JALR/R_MICROMIPS_JALR can now be parsed in .s files and emitted to .o.
They are still not generated with JALR.

[atanasyan]

lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp

503

Do we really need to make this fixup 64-bit wide? It's a hint for instruction relaxation so 32-bit would be enough.

[vstefanovic]

lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp

503

True.

[vstefanovic]

Addressed comment.

[atanasyan]

LGTM

lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp

return StringSwitch<Optional<MCFixupKind>>(Name)
       .Case("R_MICROMIPS_TLS_DTPREL_LO16",
             (MCFixupKind)Mips::fixup_MICROMIPS_TLS_DTPREL_LO16)
       .Case("R_MICROMIPS_TLS_GD", (MCFixupKind)Mips::fixup_MICROMIPS_TLS_GD)
       .Case("R_MICROMIPS_TLS_LDM", (MCFixupKind)Mips::fixup_MICROMIPS_TLS_LDM)
       .Case("R_MICROMIPS_TLS_TPREL_HI16",
             (MCFixupKind)Mips::fixup_MICROMIPS_TLS_TPREL_HI16)
       .Case("R_MICROMIPS_TLS_TPREL_LO16",
             (MCFixupKind)Mips::fixup_MICROMIPS_TLS_TPREL_LO16)
+      .Case("R_MIPS_JALR", (MCFixupKind)Mips::fixup_Mips_JALR)
+      .Case("R_MICROMIPS_JALR", (MCFixupKind)Mips::fixup_MICROMIPS_JALR)
       .Default(MCAsmBackend::getFixupKind(Name));
 }
 
 const MCFixupKindInfo &MipsAsmBackend::
 getFixupKindInfo(MCFixupKind Kind) const {
   const static MCFixupKindInfo LittleEndianInfos[] = {
     // This table *must* be in same the order of fixup_* kinds in
     // MipsFixupKinds.h.
const static MCFixupKindInfo LittleEndianInfos[] = {
     { "fixup_MICROMIPS_TLS_GD",          0,     16,   0 },
     { "fixup_MICROMIPS_TLS_LDM",         0,     16,   0 },
     { "fixup_MICROMIPS_TLS_DTPREL_HI16", 0,     16,   0 },
     { "fixup_MICROMIPS_TLS_DTPREL_LO16", 0,     16,   0 },
     { "fixup_MICROMIPS_GOTTPREL",        0,     16,   0 },
     { "fixup_MICROMIPS_TLS_TPREL_HI16",  0,     16,   0 },
     { "fixup_MICROMIPS_TLS_TPREL_LO16",  0,     16,   0 },
     { "fixup_Mips_SUB",                  0,     64,   0 },
-    { "fixup_MICROMIPS_SUB",             0,     64,   0 }
+    { "fixup_MICROMIPS_SUB",             0,     64,   0 },
+    { "fixup_Mips_JALR",                 0,     32,   0 },
+    { "fixup_MICROMIPS_JALR",            0,     32,   0 }
   };
   static_assert(array_lengthof(LittleEndianInfos) == Mips::NumTargetFixupKinds,
                 "Not all MIPS little endian fixup kinds added!");
 
   const static MCFixupKindInfo BigEndianInfos[] = {
     // This table *must* be in same the order of fixup_* kinds in
     // MipsFixupKinds.h.
     //
const static MCFixupKindInfo BigEndianInfos[] = {
     { "fixup_MICROMIPS_TLS_GD",          16,     16,   0 },
     { "fixup_MICROMIPS_TLS_LDM",         16,     16,   0 },
     { "fixup_MICROMIPS_TLS_DTPREL_HI16", 16,     16,   0 },
     { "fixup_MICROMIPS_TLS_DTPREL_LO16", 16,     16,   0 },
     { "fixup_MICROMIPS_GOTTPREL",        16,     16,   0 },
     { "fixup_MICROMIPS_TLS_TPREL_HI16",  16,     16,   0 },
     { "fixup_MICROMIPS_TLS_TPREL_LO16",  16,     16,   0 },
     { "fixup_Mips_SUB",                   0,     64,   0 },
-    { "fixup_MICROMIPS_SUB",              0,     64,   0 }
+    { "fixup_MICROMIPS_SUB",              0,     64,   0 },
+    { "fixup_Mips_JALR",                  0,     32,   0 },
+    { "fixup_MICROMIPS_JALR",             0,     32,   0 }
   };
   static_assert(array_lengthof(BigEndianInfos) == Mips::NumTargetFixupKinds,
                 "Not all MIPS big endian fixup kinds added!");
 
   if (Kind < FirstTargetFixupKind)
     return MCAsmBackend::getFixupKindInfo(Kind);
 
   assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
bool MipsAsmBackend::shouldForceRelocation(const MCAssembler &Asm,
   case Mips::fixup_Mips_GOT_LO16:
   case Mips::fixup_Mips_GOTTPREL:
   case Mips::fixup_Mips_DTPREL_HI:
   case Mips::fixup_Mips_DTPREL_LO:
   case Mips::fixup_Mips_TLSGD:
   case Mips::fixup_Mips_TLSLDM:
   case Mips::fixup_Mips_TPREL_HI:
   case Mips::fixup_Mips_TPREL_LO:
+  case Mips::fixup_Mips_JALR:
   case Mips::fixup_MICROMIPS_CALL16:
   case Mips::fixup_MICROMIPS_GOT_DISP:
   case Mips::fixup_MICROMIPS_GOT_PAGE:
   case Mips::fixup_MICROMIPS_GOT_OFST:
   case Mips::fixup_MICROMIPS_GOT16:
   case Mips::fixup_MICROMIPS_GOTTPREL:
   case Mips::fixup_MICROMIPS_TLS_DTPREL_HI16:
   case Mips::fixup_MICROMIPS_TLS_DTPREL_LO16:
   case Mips::fixup_MICROMIPS_TLS_GD:
   case Mips::fixup_MICROMIPS_TLS_LDM:
   case Mips::fixup_MICROMIPS_TLS_TPREL_HI16:
   case Mips::fixup_MICROMIPS_TLS_TPREL_LO16:
+  case Mips::fixup_MICROMIPS_JALR:
     return true;
   }
 }
 
 bool MipsAsmBackend::isMicroMips(const MCSymbol *Sym) const {
   if (const auto *ElfSym = dyn_cast<const MCSymbolELF>(Sym)) {
     if (ElfSym->getOther() & ELF::STO_MIPS_MICROMIPS)
       return true;

lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp

unsigned MipsELFObjectWriter::getRelocType(MCContext &Ctx,
   case Mips::fixup_MICROMIPS_TLS_TPREL_LO16:
     return ELF::R_MICROMIPS_TLS_TPREL_LO16;
   case Mips::fixup_MICROMIPS_SUB:
     return ELF::R_MICROMIPS_SUB;
   case Mips::fixup_MICROMIPS_HIGHER:
     return ELF::R_MICROMIPS_HIGHER;
   case Mips::fixup_MICROMIPS_HIGHEST:
     return ELF::R_MICROMIPS_HIGHEST;
+  case Mips::fixup_Mips_JALR:
+    return ELF::R_MIPS_JALR;
+  case Mips::fixup_MICROMIPS_JALR:
+    return ELF::R_MICROMIPS_JALR;
   }
 
   llvm_unreachable("invalid fixup kind!");
 }
 
 /// Sort relocation table entries by offset except where another order is
 /// required by the MIPS ABI.
 ///

lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h

enum Fixups {
 
     // resulting in - R_MICROMIPS_TLS_TPREL_LO16
     fixup_MICROMIPS_TLS_TPREL_LO16,
 
     // resulting in - R_MIPS_SUB/R_MICROMIPS_SUB
     fixup_Mips_SUB,
     fixup_MICROMIPS_SUB,
 
+    // resulting in - R_MIPS_JALR/R_MICROMIPS_JALR
+    fixup_Mips_JALR,
+    fixup_MICROMIPS_JALR,
+
     // Marker
     LastTargetFixupKind,
     NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind
   };
 } // namespace Mips
 } // namespace llvm
 
 
 #endif

test/MC/Mips/reloc-directive.s

foo:
   .reloc 112, R_MICROMIPS_TLS_GD, 4             # ASM: .reloc 112, R_MICROMIPS_TLS_GD, 4
   nop
   .reloc 116, R_MICROMIPS_TLS_LDM, 4            # ASM: .reloc 116, R_MICROMIPS_TLS_LDM, 4
   nop
   .reloc 120, R_MICROMIPS_TLS_TPREL_HI16, 4     # ASM: .reloc 120, R_MICROMIPS_TLS_TPREL_HI16, 4
   nop
   .reloc 124, R_MICROMIPS_TLS_TPREL_LO16, 4     # ASM: .reloc 124, R_MICROMIPS_TLS_TPREL_LO16, 4
   nop
+  .reloc 128, R_MIPS_JALR, 4            # ASM: .reloc 128, R_MIPS_JALR, 4
+  nop
+  .reloc 132, R_MICROMIPS_JALR, 4       # ASM: .reloc 132, R_MICROMIPS_JALR, 4
+  nop
 
 # OBJ-O32-LABEL: Name: .text
 # OBJ-O32:       0000: 00000000 00000000 00000008 00000000
 # OBJ-O32-NEXT:  0010: 00000000 00000004 00000000 00000000
 # OBJ-O32-NEXT:  0020: 00000004 00000004 00000004 00000000
 # OBJ-O32-NEXT:  0030: 00000004 00000000 00000000 00000000
 # OBJ-O32-NEXT:  0040: 00000000 00000000 00000000 00000000
 # OBJ-O32-NEXT:  0050: 00000000 00000004 00000004 00000004
 # OBJ-O32-NEXT:  0060: 00000000 00000000 00000000 00000000
 # OBJ-O32-NEXT:  0070: 00000000 00000000 00000000 00000000
+# OBJ-O32-NEXT:  0080: 00000000 00000000
 # OBJ-O32-LABEL: }
 # OBJ-O32-LABEL: Relocations [
 # OBJ-O32:       0x0 R_MIPS_NONE .text 0x0
 # OBJ-O32-NEXT:  0x4 R_MIPS_NONE .text 0x0
 # OBJ-O32-NEXT:  0x8 R_MIPS_32 .text 0x0
 # OBJ-O32-NEXT:  0xC R_MIPS_NONE -   0x0
 # OBJ-O32-NEXT:  0x10 R_MIPS_CALL_HI16 - 0x0
 # OBJ-O32-NEXT:  0x14 R_MIPS_CALL_LO16 - 0x0

 # OBJ-O32-NEXT:  0x5C R_MICROMIPS_GOT_OFST - 0x0
 # OBJ-O32-NEXT:  0x64 R_MICROMIPS_TLS_GOTTPREL - 0x0
 # OBJ-O32-NEXT:  0x68 R_MICROMIPS_TLS_DTPREL_HI16 - 0x0
 # OBJ-O32-NEXT:  0x6C R_MICROMIPS_TLS_DTPREL_LO16 - 0x0
 # OBJ-O32-NEXT:  0x70 R_MICROMIPS_TLS_GD - 0x0
 # OBJ-O32-NEXT:  0x74 R_MICROMIPS_TLS_LDM - 0x0
 # OBJ-O32-NEXT:  0x78 R_MICROMIPS_TLS_TPREL_HI16 - 0x0
 # OBJ-O32-NEXT:  0x7C R_MICROMIPS_TLS_TPREL_LO16 - 0x0
+# OBJ-O32-NEXT:  0x80 R_MIPS_JALR - 0x0
+# OBJ-O32-NEXT:  0x84 R_MICROMIPS_JALR - 0x0
 # OBJ-O32-NEXT:  0x1C R_MIPS_GOT16 - 0x0
 # OBJ-O32-NEXT:  0x60 R_MICROMIPS_GOT16 - 0x0
 
 # OBJ-N32-LABEL: Name: .text
 # OBJ-N32:       0000: 00000000 00000000 00000000 00000000
 # OBJ-N32-NEXT:  0010: 00000000 00000000 00000000 00000000
 # OBJ-N32-NEXT:  0020: 00000000 00000000 00000000 00000000
 # OBJ-N32-NEXT:  0030: 00000000 00000000 00000000 00000000
 # OBJ-N32-NEXT:  0040: 00000000 00000000 00000000 00000000
 # OBJ-N32-NEXT:  0050: 00000000 00000000 00000000 00000000
 # OBJ-N32-NEXT:  0060: 00000000 00000000 00000000 00000000
 # OBJ-N32-NEXT:  0070: 00000000 00000000 00000000 00000000
+# OBJ-N32-NEXT:  0080: 00000000 00000000
 # OBJ-N32-LABEL: }
 # OBJ-N32-LABEL: Relocations [
 
 # OBJ-N32:       0x4 R_MIPS_NONE .text 0x0
 # OBJ-N32-NEXT:  0x0 R_MIPS_NONE .text 0x4
 # OBJ-N32-NEXT:  0x8 R_MIPS_32   .text 0x8
 # OBJ-N32-NEXT:  0xC R_MIPS_NONE -     0x0
 # OBJ-N32-NEXT:  0x10 R_MIPS_CALL_HI16 - 0x4

 # OBJ-N32-NEXT:  0x60 R_MICROMIPS_GOT16 - 0x4
 # OBJ-N32-NEXT:  0x64 R_MICROMIPS_TLS_GOTTPREL - 0x4
 # OBJ-N32-NEXT:  0x68 R_MICROMIPS_TLS_DTPREL_HI16 - 0x4
 # OBJ-N32-NEXT:  0x6C R_MICROMIPS_TLS_DTPREL_LO16 - 0x4
 # OBJ-N32-NEXT:  0x70 R_MICROMIPS_TLS_GD - 0x4
 # OBJ-N32-NEXT:  0x74 R_MICROMIPS_TLS_LDM - 0x4
 # OBJ-N32-NEXT:  0x78 R_MICROMIPS_TLS_TPREL_HI16 - 0x4
 # OBJ-N32-NEXT:  0x7C R_MICROMIPS_TLS_TPREL_LO16 - 0x4
+# OBJ-N32-NEXT:  0x80 R_MIPS_JALR - 0x4
+# OBJ-N32-NEXT:  0x84 R_MICROMIPS_JALR - 0x4
 
 # OBJ-N64-LABEL: Name: .text
 # OBJ-N64:       0000: 00000000 00000000 00000000 00000000
 # OBJ-N64-NEXT:  0010: 00000000 00000000 00000000 00000000
 # OBJ-N64-NEXT:  0020: 00000000 00000000 00000000 00000000
 # OBJ-N64-NEXT:  0030: 00000000 00000000 00000000 00000000
 # OBJ-N64-NEXT:  0040: 00000000 00000000 00000000 00000000
 # OBJ-N64-NEXT:  0050: 00000000 00000000 00000000 00000000
 # OBJ-N64-NEXT:  0060: 00000000 00000000 00000000 00000000
 # OBJ-N64-NEXT:  0070: 00000000 00000000 00000000 00000000
+# OBJ-N64-NEXT:  0080: 00000000 00000000
 # OBJ-N64-LABEL: }
 # OBJ-N64-LABEL: Relocations [
 # OBJ-N64:       0x4 R_MIPS_NONE/R_MIPS_NONE/R_MIPS_NONE .text 0x0
 # OBJ-N64-NEXT:  0x0 R_MIPS_NONE/R_MIPS_NONE/R_MIPS_NONE .text 0x4
 # OBJ-N64-NEXT:  0x8 R_MIPS_32/R_MIPS_NONE/R_MIPS_NONE .text 0x8
 # OBJ-N64-NEXT:  0xC R_MIPS_NONE/R_MIPS_NONE/R_MIPS_NONE -   0x0
 # OBJ-N64-NEXT:  0x10 R_MIPS_CALL_HI16/R_MIPS_NONE/R_MIPS_NONE - 0x4
 # OBJ-N64-NEXT:  0x14 R_MIPS_CALL_LO16/R_MIPS_NONE/R_MIPS_NONE - 0x4

 # OBJ-N64-NEXT:  0x60 R_MICROMIPS_GOT16/R_MIPS_NONE/R_MIPS_NONE - 0x4
 # OBJ-N64-NEXT:  0x64 R_MICROMIPS_TLS_GOTTPREL/R_MIPS_NONE/R_MIPS_NONE - 0x4
 # OBJ-N64-NEXT:  0x68 R_MICROMIPS_TLS_DTPREL_HI16/R_MIPS_NONE/R_MIPS_NONE - 0x4
 # OBJ-N64-NEXT:  0x6C R_MICROMIPS_TLS_DTPREL_LO16/R_MIPS_NONE/R_MIPS_NONE - 0x4
 # OBJ-N64-NEXT:  0x70 R_MICROMIPS_TLS_GD/R_MIPS_NONE/R_MIPS_NONE - 0x4
 # OBJ-N64-NEXT:  0x74 R_MICROMIPS_TLS_LDM/R_MIPS_NONE/R_MIPS_NONE - 0x4
 # OBJ-N64-NEXT:  0x78 R_MICROMIPS_TLS_TPREL_HI16/R_MIPS_NONE/R_MIPS_NONE - 0x4
 # OBJ-N64-NEXT:  0x7C R_MICROMIPS_TLS_TPREL_LO16/R_MIPS_NONE/R_MIPS_NONE - 0x4
+# OBJ-N64-NEXT:  0x80 R_MIPS_JALR/R_MIPS_NONE/R_MIPS_NONE - 0x4
+# OBJ-N64-NEXT:  0x84 R_MICROMIPS_JALR/R_MIPS_NONE/R_MIPS_NONE - 0x4