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Differential D54679

[TargetLowering] Improve SimplifyDemandedVectorElts/SimplifyDemandedBits support
ClosedPublic

Authored by RKSimon on Nov 18 2018, 3:10 PM.

Details

Reviewers
efriedma
craig.topper
spatel
lebedev.ri
Commits
rGb356d0463e77: [TargetLowering] Improve SimplifyDemandedVectorElts/SimplifyDemandedBits support
rL347301: [TargetLowering] Improve SimplifyDemandedVectorElts/SimplifyDemandedBits support
Summary

For bitcast nodes from larger element types, add the ability for SimplifyDemandedVectorElts to call SimplifyDemandedBits by merging the elts mask to a bits mask.

I've raised https://bugs.llvm.org/show_bug.cgi?id=39689 to deal with the few places where SimplifyDemandedBits's lack of vector handling is a problem.

Diff Detail

Repository
rL LLVM

Event Timeline

RKSimon created this revision.Nov 18 2018, 3:10 PM
RKSimon updated this revision to Diff 174614.Nov 19 2018, 7:39 AM

Use APInt::setBits instead of APInt::insertBits

Added TODO comment highlighting shuffle regression

spatel accepted this revision.Nov 19 2018, 9:59 AM

LGTM

This revision is now accepted and ready to land.Nov 19 2018, 9:59 AM
RKSimon mentioned this in rL347240: [X86] Attempt to improve v32i8/v64i8 multiply lowering by applying the v16i8….Nov 19 2018, 12:21 PM
RKSimon mentioned this in rL347300: [X86][SSE] Lower immediately to PACKUS instead of VECTOR_SHUFFLE..Nov 20 2018, 3:49 AM
Closed by commit rL347301: [TargetLowering] Improve SimplifyDemandedVectorElts/SimplifyDemandedBits support (authored by RKSimon). · Explain WhyNov 20 2018, 4:05 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
lib/
CodeGen/
SelectionDAG/
TargetLowering.cpp
TargetLowering.cpp (revision 347176)
16 lines
test/
CodeGen/
X86/
known-bits-vector.ll
known-bits-vector.ll (revision 347176)
12 lines
known-signbits-vector.ll
known-signbits-vector.ll (revision 347176)
12 lines
reduce-trunc-shl.ll
reduce-trunc-shl.ll (revision 347176)
6 lines
shrink_vmul.ll
shrink_vmul.ll (revision 347176)
50 lines
vector-trunc-math-widen.ll
vector-trunc-math-widen.ll (revision 347176)
257 lines
vector-trunc-math.ll
vector-trunc-math.ll (revision 347176)
257 lines

Diff 174546

lib/CodeGen/SelectionDAG/TargetLowering.cpp

Show First 20 Lines • Show All 1,454 Lines • ▼ Show 20 Lines if ((NumElts % NumSrcElts) == 0) {
for (unsigned i = 0; i != NumElts; ++i) for (unsigned i = 0; i != NumElts; ++i)
if (DemandedElts[i]) if (DemandedElts[i])
SrcDemandedElts.setBit(i / Scale); SrcDemandedElts.setBit(i / Scale);
if (SimplifyDemandedVectorElts(Src, SrcDemandedElts, SrcUndef, SrcZero, if (SimplifyDemandedVectorElts(Src, SrcDemandedElts, SrcUndef, SrcZero,
TLO, Depth + 1)) TLO, Depth + 1))
return true; return true;
// Try calling SimplifyDemandedBits, converting demanded elts to the bits
// of the large element.
// TODO - bigendian once we have test coverage.
if (TLO.DAG.getDataLayout().isLittleEndian()) {
APInt EltBits = APInt::getAllOnesValue(EltSizeInBits);
unsigned SrcEltSizeInBits = SrcVT.getScalarSizeInBits();
APInt SrcDemandedBits = APInt::getNullValue(SrcEltSizeInBits);
for (unsigned i = 0; i != NumElts; ++i)
if (DemandedElts[i])
SrcDemandedBits.insertBits(EltBits, (i % Scale) * EltSizeInBits);
KnownBits Known;
if (SimplifyDemandedBits(Src, SrcDemandedBits, Known, TLO, Depth + 1))
return true;
}
// If the src element is zero/undef then all the output elements will be - // If the src element is zero/undef then all the output elements will be -
// only demanded elements are guaranteed to be correct. // only demanded elements are guaranteed to be correct.
for (unsigned i = 0; i != NumSrcElts; ++i) { for (unsigned i = 0; i != NumSrcElts; ++i) {
if (SrcDemandedElts[i]) { if (SrcDemandedElts[i]) {
if (SrcZero[i]) if (SrcZero[i])
KnownZero.setBits(i * Scale, (i + 1) * Scale); KnownZero.setBits(i * Scale, (i + 1) * Scale);
if (SrcUndef[i]) if (SrcUndef[i])
KnownUndef.setBits(i * Scale, (i + 1) * Scale); KnownUndef.setBits(i * Scale, (i + 1) * Scale);
▲ Show 20 Lines • Show All 3,595 Lines • Show Last 20 Lines

test/CodeGen/X86/known-bits-vector.ll

Show First 20 Lines • Show All 152 Lines • ▼ Show 20 Lines; X64-NEXT: retq
%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 2, i32 3, i32 3> %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 2, i32 3, i32 3>
%3 = uitofp <4 x i32> %2 to <4 x float> %3 = uitofp <4 x i32> %2 to <4 x float>
ret <4 x float> %3 ret <4 x float> %3
} }
define <4 x float> @knownbits_mask_or_shuffle_uitofp(<4 x i32> %a0) nounwind { define <4 x float> @knownbits_mask_or_shuffle_uitofp(<4 x i32> %a0) nounwind {
; X32-LABEL: knownbits_mask_or_shuffle_uitofp: ; X32-LABEL: knownbits_mask_or_shuffle_uitofp:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: vpor {{\.LCPI.*}}, %xmm0, %xmm0 ; X32-NEXT: vmovaps {{.*#+}} xmm0 = [6.5535E+4,6.5535E+4,6.5535E+4,6.5535E+4]
; X32-NEXT: vpxor %xmm1, %xmm1, %xmm1
; X32-NEXT: vpshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,4,6,6]
; X32-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
; X32-NEXT: vcvtdq2ps %xmm0, %xmm0
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: knownbits_mask_or_shuffle_uitofp: ; X64-LABEL: knownbits_mask_or_shuffle_uitofp:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: vpor {{.*}}(%rip), %xmm0, %xmm0 ; X64-NEXT: vmovaps {{.*#+}} xmm0 = [6.5535E+4,6.5535E+4,6.5535E+4,6.5535E+4]
; X64-NEXT: vpxor %xmm1, %xmm1, %xmm1
; X64-NEXT: vpshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,4,6,6]
; X64-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
; X64-NEXT: vcvtdq2ps %xmm0, %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
%1 = and <4 x i32> %a0, <i32 -1, i32 -1, i32 255, i32 4085> %1 = and <4 x i32> %a0, <i32 -1, i32 -1, i32 255, i32 4085>
%2 = or <4 x i32> %1, <i32 65535, i32 65535, i32 65535, i32 65535> %2 = or <4 x i32> %1, <i32 65535, i32 65535, i32 65535, i32 65535>
%3 = shufflevector <4 x i32> %2, <4 x i32> undef, <4 x i32> <i32 2, i32 2, i32 3, i32 3> %3 = shufflevector <4 x i32> %2, <4 x i32> undef, <4 x i32> <i32 2, i32 2, i32 3, i32 3>
%4 = uitofp <4 x i32> %3 to <4 x float> %4 = uitofp <4 x i32> %3 to <4 x float>
ret <4 x float> %4 ret <4 x float> %4
} }
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test/CodeGen/X86/known-signbits-vector.ll

Show First 20 Lines • Show All 233 Lines • ▼ Show 20 Lines
; X32-LABEL: signbits_ashr_concat_ashr_extract_sitofp: ; X32-LABEL: signbits_ashr_concat_ashr_extract_sitofp:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[1,3,2,3] ; X32-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[1,3,2,3]
; X32-NEXT: vcvtdq2pd %xmm0, %xmm0 ; X32-NEXT: vcvtdq2pd %xmm0, %xmm0
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: signbits_ashr_concat_ashr_extract_sitofp: ; X64-LABEL: signbits_ashr_concat_ashr_extract_sitofp:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[1,3,2,3] ; X64-NEXT: vpsrlq $32, %xmm0, %xmm0
; X64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; X64-NEXT: vcvtdq2pd %xmm0, %xmm0 ; X64-NEXT: vcvtdq2pd %xmm0, %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
%1 = ashr <2 x i64> %a0, <i64 16, i64 16> %1 = ashr <2 x i64> %a0, <i64 16, i64 16>
%2 = shufflevector <2 x i64> %1, <2 x i64> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> %2 = shufflevector <2 x i64> %1, <2 x i64> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
%3 = shufflevector <4 x i64> %a1, <4 x i64> %2, <4 x i32> <i32 0, i32 1, i32 4, i32 5> %3 = shufflevector <4 x i64> %a1, <4 x i64> %2, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
%4 = ashr <4 x i64> %3, <i64 16, i64 16, i64 16, i64 16> %4 = ashr <4 x i64> %3, <i64 16, i64 16, i64 16, i64 16>
%5 = shufflevector <4 x i64> %4, <4 x i64> undef, <2 x i32> <i32 2, i32 3> %5 = shufflevector <4 x i64> %4, <4 x i64> undef, <2 x i32> <i32 2, i32 3>
%6 = sitofp <2 x i64> %5 to <2 x double> %6 = sitofp <2 x i64> %5 to <2 x double>
ret <2 x double> %6 ret <2 x double> %6
} }
define float @signbits_ashr_sext_sextinreg_and_extract_sitofp(<2 x i64> %a0, <2 x i64> %a1, i32 %a2) nounwind { define float @signbits_ashr_sext_sextinreg_and_extract_sitofp(<2 x i64> %a0, <2 x i64> %a1, i32 %a2) nounwind {
; X32-LABEL: signbits_ashr_sext_sextinreg_and_extract_sitofp: ; X32-LABEL: signbits_ashr_sext_sextinreg_and_extract_sitofp:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: pushl %eax ; X32-NEXT: pushl %eax
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: vpsrlq $60, %xmm0, %xmm2 ; X32-NEXT: vpsrlq $60, %xmm0, %xmm2
; X32-NEXT: vpsrlq $61, %xmm0, %xmm0 ; X32-NEXT: vpsrlq $61, %xmm0, %xmm0
; X32-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm2[4,5,6,7] ; X32-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm2[4,5,6,7]
; X32-NEXT: vmovdqa {{.*#+}} xmm2 = [4,0,0,0,8,0,0,0] ; X32-NEXT: vmovdqa {{.*#+}} xmm2 = [4,0,0,0,8,0,0,0]
; X32-NEXT: vpxor %xmm2, %xmm0, %xmm0 ; X32-NEXT: vpxor %xmm2, %xmm0, %xmm0
; X32-NEXT: vpsubq %xmm2, %xmm0, %xmm0 ; X32-NEXT: vpsubq %xmm2, %xmm0, %xmm0
; X32-NEXT: vpinsrd $0, %eax, %xmm1, %xmm1 ; X32-NEXT: vpinsrd $0, {{[0-9]+}}(%esp), %xmm1, %xmm1
; X32-NEXT: sarl $31, %eax
; X32-NEXT: vpinsrd $1, %eax, %xmm1, %xmm1
; X32-NEXT: vpsllq $20, %xmm1, %xmm1
; X32-NEXT: vpsrad $20, %xmm1, %xmm2
; X32-NEXT: vpsrlq $20, %xmm1, %xmm1
; X32-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7]
; X32-NEXT: vpand %xmm1, %xmm0, %xmm0 ; X32-NEXT: vpand %xmm1, %xmm0, %xmm0
; X32-NEXT: vmovd %xmm0, %eax ; X32-NEXT: vmovd %xmm0, %eax
; X32-NEXT: vcvtsi2ssl %eax, %xmm3, %xmm0 ; X32-NEXT: vcvtsi2ssl %eax, %xmm3, %xmm0
; X32-NEXT: vmovss %xmm0, (%esp) ; X32-NEXT: vmovss %xmm0, (%esp)
; X32-NEXT: flds (%esp) ; X32-NEXT: flds (%esp)
; X32-NEXT: popl %eax ; X32-NEXT: popl %eax
; X32-NEXT: retl ; X32-NEXT: retl
; ;
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test/CodeGen/X86/reduce-trunc-shl.ll

Show First 20 Lines • Show All 66 Lines • ▼ Show 20 Lines
define <8 x i16> @trunc_shl_17_v8i16_v8i32(<8 x i32> %a) { define <8 x i16> @trunc_shl_17_v8i16_v8i32(<8 x i32> %a) {
; SSE2-LABEL: trunc_shl_17_v8i16_v8i32: ; SSE2-LABEL: trunc_shl_17_v8i16_v8i32:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: xorps %xmm0, %xmm0 ; SSE2-NEXT: xorps %xmm0, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; AVX2-LABEL: trunc_shl_17_v8i16_v8i32: ; AVX2-LABEL: trunc_shl_17_v8i16_v8i32:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpslld $17, %ymm0, %ymm0 ; AVX2-NEXT: vxorps %xmm0, %xmm0, %xmm0
; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
; AVX2-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq ; AVX2-NEXT: retq
%shl = shl <8 x i32> %a, <i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17> %shl = shl <8 x i32> %a, <i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17>
%conv = trunc <8 x i32> %shl to <8 x i16> %conv = trunc <8 x i32> %shl to <8 x i16>
ret <8 x i16> %conv ret <8 x i16> %conv
} }
define void @trunc_shl_31_i32_i64(i32* %out, i64* %in) { define void @trunc_shl_31_i32_i64(i32* %out, i64* %in) {
; SSE2-LABEL: trunc_shl_31_i32_i64: ; SSE2-LABEL: trunc_shl_31_i32_i64:
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test/CodeGen/X86/shrink_vmul.ll

Show First 20 Lines • Show All 1,148 Lines • ▼ Show 20 Lines
; X86-SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,0,2,1,4,5,6,7] ; X86-SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,0,2,1,4,5,6,7]
; X86-SSE-NEXT: psrad $16, %xmm0 ; X86-SSE-NEXT: psrad $16, %xmm0
; X86-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,1,3] ; X86-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,1,3]
; X86-SSE-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero ; X86-SSE-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
; X86-SSE-NEXT: pxor %xmm2, %xmm2 ; X86-SSE-NEXT: pxor %xmm2, %xmm2
; X86-SSE-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3] ; X86-SSE-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3]
; X86-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,1,1,3] ; X86-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,1,1,3]
; X86-SSE-NEXT: pmuludq %xmm0, %xmm1 ; X86-SSE-NEXT: pmuludq %xmm0, %xmm1
; X86-SSE-NEXT: pmuludq %xmm0, %xmm2 ; X86-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,2,2,3]
; X86-SSE-NEXT: psllq $32, %xmm2
; X86-SSE-NEXT: paddq %xmm1, %xmm2
; X86-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3]
; X86-SSE-NEXT: movq %xmm0, (%esi,%ecx,4) ; X86-SSE-NEXT: movq %xmm0, (%esi,%ecx,4)
; X86-SSE-NEXT: popl %esi ; X86-SSE-NEXT: popl %esi
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
; ;
; X86-AVX-LABEL: mul_2xi16_sext_zext: ; X86-AVX-LABEL: mul_2xi16_sext_zext:
; X86-AVX: # %bb.0: # %entry ; X86-AVX: # %bb.0: # %entry
; X86-AVX-NEXT: pushl %esi ; X86-AVX-NEXT: pushl %esi
; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax
Show All 17 Lines
; X64-SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,0,2,1,4,5,6,7] ; X64-SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,0,2,1,4,5,6,7]
; X64-SSE-NEXT: psrad $16, %xmm0 ; X64-SSE-NEXT: psrad $16, %xmm0
; X64-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,1,3] ; X64-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,1,3]
; X64-SSE-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero ; X64-SSE-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
; X64-SSE-NEXT: pxor %xmm2, %xmm2 ; X64-SSE-NEXT: pxor %xmm2, %xmm2
; X64-SSE-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3] ; X64-SSE-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3]
; X64-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,1,1,3] ; X64-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,1,1,3]
; X64-SSE-NEXT: pmuludq %xmm0, %xmm1 ; X64-SSE-NEXT: pmuludq %xmm0, %xmm1
; X64-SSE-NEXT: pmuludq %xmm0, %xmm2 ; X64-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,2,2,3]
; X64-SSE-NEXT: psllq $32, %xmm2
; X64-SSE-NEXT: paddq %xmm1, %xmm2
; X64-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3]
; X64-SSE-NEXT: movq %xmm0, (%rax,%rdx,4) ; X64-SSE-NEXT: movq %xmm0, (%rax,%rdx,4)
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
; ;
; X64-AVX-LABEL: mul_2xi16_sext_zext: ; X64-AVX-LABEL: mul_2xi16_sext_zext:
; X64-AVX: # %bb.0: # %entry ; X64-AVX: # %bb.0: # %entry
; X64-AVX-NEXT: movq {{.*}}(%rip), %rax ; X64-AVX-NEXT: movq {{.*}}(%rip), %rax
; X64-AVX-NEXT: vpmovsxwq (%rdi,%rdx), %xmm0 ; X64-AVX-NEXT: vpmovsxwq (%rdi,%rdx), %xmm0
; X64-AVX-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero ; X64-AVX-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
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; X86-SSE: # %bb.0: # %entry ; X86-SSE: # %bb.0: # %entry
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-SSE-NEXT: movl c, %edx ; X86-SSE-NEXT: movl c, %edx
; X86-SSE-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero ; X86-SSE-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86-SSE-NEXT: pxor %xmm1, %xmm1 ; X86-SSE-NEXT: pxor %xmm1, %xmm1
; X86-SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3] ; X86-SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
; X86-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,1,3] ; X86-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,1,3]
; X86-SSE-NEXT: movdqa {{.*#+}} xmm2 = <0,u,65536,u> ; X86-SSE-NEXT: pmuludq {{\.LCPI.*}}, %xmm0
; X86-SSE-NEXT: pmuludq %xmm2, %xmm1
; X86-SSE-NEXT: movdqa %xmm2, %xmm3
; X86-SSE-NEXT: psrlq $32, %xmm3
; X86-SSE-NEXT: pmuludq %xmm0, %xmm3
; X86-SSE-NEXT: paddq %xmm1, %xmm3
; X86-SSE-NEXT: psllq $32, %xmm3
; X86-SSE-NEXT: pmuludq %xmm2, %xmm0
; X86-SSE-NEXT: paddq %xmm3, %xmm0
; X86-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] ; X86-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; X86-SSE-NEXT: movq %xmm0, (%edx,%eax,4) ; X86-SSE-NEXT: movq %xmm0, (%edx,%eax,4)
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
; ;
; X86-AVX-LABEL: mul_2xi16_varconst3: ; X86-AVX-LABEL: mul_2xi16_varconst3:
; X86-AVX: # %bb.0: # %entry ; X86-AVX: # %bb.0: # %entry
; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X64-SSE-LABEL: mul_2xi16_varconst3: ; X64-SSE-LABEL: mul_2xi16_varconst3:
; X64-SSE: # %bb.0: # %entry ; X64-SSE: # %bb.0: # %entry
; X64-SSE-NEXT: movq {{.*}}(%rip), %rax ; X64-SSE-NEXT: movq {{.*}}(%rip), %rax
; X64-SSE-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero ; X64-SSE-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X64-SSE-NEXT: pxor %xmm1, %xmm1 ; X64-SSE-NEXT: pxor %xmm1, %xmm1
; X64-SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3] ; X64-SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
; X64-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,1,3] ; X64-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,1,3]
; X64-SSE-NEXT: movl $65536, %ecx # imm = 0x10000 ; X64-SSE-NEXT: movl $65536, %ecx # imm = 0x10000
; X64-SSE-NEXT: movq %rcx, %xmm2 ; X64-SSE-NEXT: movq %rcx, %xmm1
; X64-SSE-NEXT: pslldq {{.*#+}} xmm2 = zero,zero,zero,zero,zero,zero,zero,zero,xmm2[0,1,2,3,4,5,6,7] ; X64-SSE-NEXT: pslldq {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,zero,zero,xmm1[0,1,2,3,4,5,6,7]
; X64-SSE-NEXT: pmuludq %xmm2, %xmm0 ; X64-SSE-NEXT: pmuludq %xmm0, %xmm1
; X64-SSE-NEXT: pmuludq %xmm1, %xmm2 ; X64-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,2,2,3]
; X64-SSE-NEXT: psllq $32, %xmm2
; X64-SSE-NEXT: paddq %xmm0, %xmm2
; X64-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3]
; X64-SSE-NEXT: movq %xmm0, (%rax,%rsi,4) ; X64-SSE-NEXT: movq %xmm0, (%rax,%rsi,4)
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
; ;
; X64-AVX-LABEL: mul_2xi16_varconst3: ; X64-AVX-LABEL: mul_2xi16_varconst3:
; X64-AVX: # %bb.0: # %entry ; X64-AVX: # %bb.0: # %entry
; X64-AVX-NEXT: movq {{.*}}(%rip), %rax ; X64-AVX-NEXT: movq {{.*}}(%rip), %rax
; X64-AVX-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero ; X64-AVX-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X64-AVX-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero ; X64-AVX-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
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; X86-SSE: # %bb.0: # %entry ; X86-SSE: # %bb.0: # %entry
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-SSE-NEXT: movl c, %edx ; X86-SSE-NEXT: movl c, %edx
; X86-SSE-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero ; X86-SSE-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86-SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,0,2,1,4,5,6,7] ; X86-SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,0,2,1,4,5,6,7]
; X86-SSE-NEXT: psrad $16, %xmm0 ; X86-SSE-NEXT: psrad $16, %xmm0
; X86-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,1,3] ; X86-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,1,3]
; X86-SSE-NEXT: movdqa {{.*#+}} xmm1 = <0,u,32768,u> ; X86-SSE-NEXT: pmuludq {{\.LCPI.*}}, %xmm0
; X86-SSE-NEXT: pxor %xmm2, %xmm2
; X86-SSE-NEXT: pmuludq %xmm1, %xmm2
; X86-SSE-NEXT: movdqa %xmm1, %xmm3
; X86-SSE-NEXT: psrlq $32, %xmm3
; X86-SSE-NEXT: pmuludq %xmm0, %xmm3
; X86-SSE-NEXT: paddq %xmm2, %xmm3
; X86-SSE-NEXT: psllq $32, %xmm3
; X86-SSE-NEXT: pmuludq %xmm1, %xmm0
; X86-SSE-NEXT: paddq %xmm3, %xmm0
; X86-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] ; X86-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; X86-SSE-NEXT: movq %xmm0, (%edx,%eax,4) ; X86-SSE-NEXT: movq %xmm0, (%edx,%eax,4)
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
; ;
; X86-AVX-LABEL: mul_2xi16_varconst4: ; X86-AVX-LABEL: mul_2xi16_varconst4:
; X86-AVX: # %bb.0: # %entry ; X86-AVX: # %bb.0: # %entry
; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X64-SSE-NEXT: movq {{.*}}(%rip), %rax ; X64-SSE-NEXT: movq {{.*}}(%rip), %rax
; X64-SSE-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero ; X64-SSE-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X64-SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,0,2,1,4,5,6,7] ; X64-SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,0,2,1,4,5,6,7]
; X64-SSE-NEXT: psrad $16, %xmm0 ; X64-SSE-NEXT: psrad $16, %xmm0
; X64-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,1,3] ; X64-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,1,3]
; X64-SSE-NEXT: movl $32768, %ecx # imm = 0x8000 ; X64-SSE-NEXT: movl $32768, %ecx # imm = 0x8000
; X64-SSE-NEXT: movq %rcx, %xmm1 ; X64-SSE-NEXT: movq %rcx, %xmm1
; X64-SSE-NEXT: pslldq {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,zero,zero,xmm1[0,1,2,3,4,5,6,7] ; X64-SSE-NEXT: pslldq {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,zero,zero,xmm1[0,1,2,3,4,5,6,7]
; X64-SSE-NEXT: pmuludq %xmm1, %xmm0 ; X64-SSE-NEXT: pmuludq %xmm0, %xmm1
; X64-SSE-NEXT: pxor %xmm2, %xmm2 ; X64-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,2,2,3]
; X64-SSE-NEXT: pmuludq %xmm1, %xmm2
; X64-SSE-NEXT: psllq $32, %xmm2
; X64-SSE-NEXT: paddq %xmm0, %xmm2
; X64-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3]
; X64-SSE-NEXT: movq %xmm0, (%rax,%rsi,4) ; X64-SSE-NEXT: movq %xmm0, (%rax,%rsi,4)
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
; ;
; X64-AVX-LABEL: mul_2xi16_varconst4: ; X64-AVX-LABEL: mul_2xi16_varconst4:
; X64-AVX: # %bb.0: # %entry ; X64-AVX: # %bb.0: # %entry
; X64-AVX-NEXT: movq {{.*}}(%rip), %rax ; X64-AVX-NEXT: movq {{.*}}(%rip), %rax
; X64-AVX-NEXT: vpmovsxwq (%rdi,%rsi), %xmm0 ; X64-AVX-NEXT: vpmovsxwq (%rdi,%rsi), %xmm0
; X64-AVX-NEXT: movl $32768, %ecx # imm = 0x8000 ; X64-AVX-NEXT: movl $32768, %ecx # imm = 0x8000
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test/CodeGen/X86/vector-trunc-math-widen.ll

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; ;
; mul ; mul
; ;
define <4 x i32> @trunc_mul_v4i64_v4i32(<4 x i64> %a0, <4 x i64> %a1) nounwind { define <4 x i32> @trunc_mul_v4i64_v4i32(<4 x i64> %a0, <4 x i64> %a1) nounwind {
; SSE-LABEL: trunc_mul_v4i64_v4i32: ; SSE-LABEL: trunc_mul_v4i64_v4i32:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movdqa %xmm1, %xmm4
; SSE-NEXT: psrlq $32, %xmm4
; SSE-NEXT: pmuludq %xmm3, %xmm4
; SSE-NEXT: movdqa %xmm3, %xmm5
; SSE-NEXT: psrlq $32, %xmm5
; SSE-NEXT: pmuludq %xmm1, %xmm5
; SSE-NEXT: paddq %xmm4, %xmm5
; SSE-NEXT: psllq $32, %xmm5
; SSE-NEXT: pmuludq %xmm3, %xmm1 ; SSE-NEXT: pmuludq %xmm3, %xmm1
; SSE-NEXT: paddq %xmm5, %xmm1
; SSE-NEXT: movdqa %xmm0, %xmm3
; SSE-NEXT: psrlq $32, %xmm3
; SSE-NEXT: pmuludq %xmm2, %xmm3
; SSE-NEXT: movdqa %xmm2, %xmm4
; SSE-NEXT: psrlq $32, %xmm4
; SSE-NEXT: pmuludq %xmm0, %xmm4
; SSE-NEXT: paddq %xmm3, %xmm4
; SSE-NEXT: psllq $32, %xmm4
; SSE-NEXT: pmuludq %xmm2, %xmm0 ; SSE-NEXT: pmuludq %xmm2, %xmm0
; SSE-NEXT: paddq %xmm4, %xmm0
; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2] ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: trunc_mul_v4i64_v4i32: ; AVX1-LABEL: trunc_mul_v4i64_v4i32:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
; AVX1-NEXT: vshufps {{.*#+}} xmm1 = xmm1[0,2],xmm2[0,2] ; AVX1-NEXT: vshufps {{.*#+}} xmm1 = xmm1[0,2],xmm2[0,2]
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
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%1 = mul <8 x i32> %a0, %a1 %1 = mul <8 x i32> %a0, %a1
%2 = trunc <8 x i32> %1 to <8 x i16> %2 = trunc <8 x i32> %1 to <8 x i16>
ret <8 x i16> %2 ret <8 x i16> %2
} }
define <16 x i8> @trunc_mul_v16i64_v16i8(<16 x i64> %a0, <16 x i64> %a1) nounwind { define <16 x i8> @trunc_mul_v16i64_v16i8(<16 x i64> %a0, <16 x i64> %a1) nounwind {
; SSE-LABEL: trunc_mul_v16i64_v16i8: ; SSE-LABEL: trunc_mul_v16i64_v16i8:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm8 ; SSE-NEXT: pmuludq {{[0-9]+}}(%rsp), %xmm0
; SSE-NEXT: movdqa %xmm0, %xmm9 ; SSE-NEXT: pmuludq {{[0-9]+}}(%rsp), %xmm1
; SSE-NEXT: psrlq $32, %xmm9 ; SSE-NEXT: pmuludq {{[0-9]+}}(%rsp), %xmm2
; SSE-NEXT: pmuludq %xmm8, %xmm9 ; SSE-NEXT: pmuludq {{[0-9]+}}(%rsp), %xmm3
; SSE-NEXT: movdqa %xmm8, %xmm10 ; SSE-NEXT: pmuludq {{[0-9]+}}(%rsp), %xmm4
; SSE-NEXT: psrlq $32, %xmm10 ; SSE-NEXT: pmuludq {{[0-9]+}}(%rsp), %xmm5
; SSE-NEXT: pmuludq %xmm0, %xmm10 ; SSE-NEXT: pmuludq {{[0-9]+}}(%rsp), %xmm6
; SSE-NEXT: paddq %xmm9, %xmm10 ; SSE-NEXT: pmuludq {{[0-9]+}}(%rsp), %xmm7
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm9
; SSE-NEXT: psllq $32, %xmm10
; SSE-NEXT: pmuludq %xmm8, %xmm0
; SSE-NEXT: paddq %xmm10, %xmm0
; SSE-NEXT: movdqa %xmm1, %xmm8
; SSE-NEXT: psrlq $32, %xmm8
; SSE-NEXT: pmuludq %xmm9, %xmm8
; SSE-NEXT: movdqa %xmm9, %xmm10
; SSE-NEXT: psrlq $32, %xmm10
; SSE-NEXT: pmuludq %xmm1, %xmm10
; SSE-NEXT: paddq %xmm8, %xmm10
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm8
; SSE-NEXT: psllq $32, %xmm10
; SSE-NEXT: pmuludq %xmm9, %xmm1
; SSE-NEXT: paddq %xmm10, %xmm1
; SSE-NEXT: movdqa %xmm2, %xmm9
; SSE-NEXT: psrlq $32, %xmm9
; SSE-NEXT: pmuludq %xmm8, %xmm9
; SSE-NEXT: movdqa %xmm8, %xmm10
; SSE-NEXT: psrlq $32, %xmm10
; SSE-NEXT: pmuludq %xmm2, %xmm10
; SSE-NEXT: paddq %xmm9, %xmm10
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm9
; SSE-NEXT: psllq $32, %xmm10
; SSE-NEXT: pmuludq %xmm8, %xmm2
; SSE-NEXT: paddq %xmm10, %xmm2
; SSE-NEXT: movdqa %xmm3, %xmm8
; SSE-NEXT: psrlq $32, %xmm8
; SSE-NEXT: pmuludq %xmm9, %xmm8
; SSE-NEXT: movdqa %xmm9, %xmm10
; SSE-NEXT: psrlq $32, %xmm10
; SSE-NEXT: pmuludq %xmm3, %xmm10
; SSE-NEXT: paddq %xmm8, %xmm10
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm8
; SSE-NEXT: psllq $32, %xmm10
; SSE-NEXT: pmuludq %xmm9, %xmm3
; SSE-NEXT: paddq %xmm10, %xmm3
; SSE-NEXT: movdqa %xmm4, %xmm9
; SSE-NEXT: psrlq $32, %xmm9
; SSE-NEXT: pmuludq %xmm8, %xmm9
; SSE-NEXT: movdqa %xmm8, %xmm10
; SSE-NEXT: psrlq $32, %xmm10
; SSE-NEXT: pmuludq %xmm4, %xmm10
; SSE-NEXT: paddq %xmm9, %xmm10
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm9
; SSE-NEXT: psllq $32, %xmm10
; SSE-NEXT: pmuludq %xmm8, %xmm4
; SSE-NEXT: paddq %xmm10, %xmm4
; SSE-NEXT: movdqa %xmm5, %xmm8
; SSE-NEXT: psrlq $32, %xmm8
; SSE-NEXT: pmuludq %xmm9, %xmm8
; SSE-NEXT: movdqa %xmm9, %xmm10
; SSE-NEXT: psrlq $32, %xmm10
; SSE-NEXT: pmuludq %xmm5, %xmm10
; SSE-NEXT: paddq %xmm8, %xmm10
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm8
; SSE-NEXT: psllq $32, %xmm10
; SSE-NEXT: pmuludq %xmm9, %xmm5
; SSE-NEXT: paddq %xmm10, %xmm5
; SSE-NEXT: movdqa %xmm6, %xmm9
; SSE-NEXT: psrlq $32, %xmm9
; SSE-NEXT: pmuludq %xmm8, %xmm9
; SSE-NEXT: movdqa %xmm8, %xmm10
; SSE-NEXT: psrlq $32, %xmm10
; SSE-NEXT: pmuludq %xmm6, %xmm10
; SSE-NEXT: paddq %xmm9, %xmm10
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm9
; SSE-NEXT: psllq $32, %xmm10
; SSE-NEXT: pmuludq %xmm8, %xmm6
; SSE-NEXT: paddq %xmm10, %xmm6
; SSE-NEXT: movdqa %xmm7, %xmm8
; SSE-NEXT: psrlq $32, %xmm8
; SSE-NEXT: pmuludq %xmm9, %xmm8
; SSE-NEXT: movdqa %xmm9, %xmm10
; SSE-NEXT: psrlq $32, %xmm10
; SSE-NEXT: pmuludq %xmm7, %xmm10
; SSE-NEXT: paddq %xmm8, %xmm10
; SSE-NEXT: pmuludq %xmm9, %xmm7
; SSE-NEXT: psllq $32, %xmm10
; SSE-NEXT: paddq %xmm10, %xmm7
; SSE-NEXT: movdqa {{.*#+}} xmm8 = [255,0,0,0,0,0,0,0,255,0,0,0,0,0,0,0] ; SSE-NEXT: movdqa {{.*#+}} xmm8 = [255,0,0,0,0,0,0,0,255,0,0,0,0,0,0,0]
; SSE-NEXT: pand %xmm8, %xmm7 ; SSE-NEXT: pand %xmm8, %xmm7
; SSE-NEXT: pand %xmm8, %xmm6 ; SSE-NEXT: pand %xmm8, %xmm6
; SSE-NEXT: packuswb %xmm7, %xmm6 ; SSE-NEXT: packuswb %xmm7, %xmm6
; SSE-NEXT: pand %xmm8, %xmm5 ; SSE-NEXT: pand %xmm8, %xmm5
; SSE-NEXT: pand %xmm8, %xmm4 ; SSE-NEXT: pand %xmm8, %xmm4
; SSE-NEXT: packuswb %xmm5, %xmm4 ; SSE-NEXT: packuswb %xmm5, %xmm4
; SSE-NEXT: packuswb %xmm6, %xmm4 ; SSE-NEXT: packuswb %xmm6, %xmm4
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; ;
; mul to constant ; mul to constant
; ;
define <4 x i32> @trunc_mul_const_v4i64_v4i32(<4 x i64> %a0) nounwind { define <4 x i32> @trunc_mul_const_v4i64_v4i32(<4 x i64> %a0) nounwind {
; SSE-LABEL: trunc_mul_const_v4i64_v4i32: ; SSE-LABEL: trunc_mul_const_v4i64_v4i32:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movdqa {{.*#+}} xmm2 = [2,3]
; SSE-NEXT: movdqa %xmm1, %xmm3
; SSE-NEXT: pmuludq %xmm2, %xmm3
; SSE-NEXT: psrlq $32, %xmm1
; SSE-NEXT: pmuludq %xmm2, %xmm1
; SSE-NEXT: psllq $32, %xmm1
; SSE-NEXT: paddq %xmm3, %xmm1
; SSE-NEXT: movl $1, %eax ; SSE-NEXT: movl $1, %eax
; SSE-NEXT: movq %rax, %xmm2 ; SSE-NEXT: movq %rax, %xmm2
; SSE-NEXT: pslldq {{.*#+}} xmm2 = zero,zero,zero,zero,zero,zero,zero,zero,xmm2[0,1,2,3,4,5,6,7] ; SSE-NEXT: pslldq {{.*#+}} xmm2 = zero,zero,zero,zero,zero,zero,zero,zero,xmm2[0,1,2,3,4,5,6,7]
; SSE-NEXT: movdqa %xmm0, %xmm3
; SSE-NEXT: pmuludq %xmm2, %xmm3
; SSE-NEXT: psrlq $32, %xmm0
; SSE-NEXT: pmuludq %xmm2, %xmm0 ; SSE-NEXT: pmuludq %xmm2, %xmm0
; SSE-NEXT: psllq $32, %xmm0 ; SSE-NEXT: pmuludq {{.*}}(%rip), %xmm1
; SSE-NEXT: paddq %xmm3, %xmm0
; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2] ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: trunc_mul_const_v4i64_v4i32: ; AVX1-LABEL: trunc_mul_const_v4i64_v4i32:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX1-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2] ; AVX1-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
; AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0 ; AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
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} }
define <16 x i8> @trunc_mul_const_v16i64_v16i8(<16 x i64> %a0) nounwind { define <16 x i8> @trunc_mul_const_v16i64_v16i8(<16 x i64> %a0) nounwind {
; SSE-LABEL: trunc_mul_const_v16i64_v16i8: ; SSE-LABEL: trunc_mul_const_v16i64_v16i8:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movl $1, %eax ; SSE-NEXT: movl $1, %eax
; SSE-NEXT: movq %rax, %xmm8 ; SSE-NEXT: movq %rax, %xmm8
; SSE-NEXT: pslldq {{.*#+}} xmm8 = zero,zero,zero,zero,zero,zero,zero,zero,xmm8[0,1,2,3,4,5,6,7] ; SSE-NEXT: pslldq {{.*#+}} xmm8 = zero,zero,zero,zero,zero,zero,zero,zero,xmm8[0,1,2,3,4,5,6,7]
; SSE-NEXT: movdqa %xmm0, %xmm9
; SSE-NEXT: pmuludq %xmm8, %xmm9
; SSE-NEXT: psrlq $32, %xmm0
; SSE-NEXT: pmuludq %xmm8, %xmm0 ; SSE-NEXT: pmuludq %xmm8, %xmm0
; SSE-NEXT: psllq $32, %xmm0 ; SSE-NEXT: pmuludq {{.*}}(%rip), %xmm1
; SSE-NEXT: paddq %xmm9, %xmm0 ; SSE-NEXT: pmuludq {{.*}}(%rip), %xmm2
; SSE-NEXT: movdqa {{.*#+}} xmm8 = [2,3] ; SSE-NEXT: pmuludq {{.*}}(%rip), %xmm3
; SSE-NEXT: movdqa %xmm1, %xmm9 ; SSE-NEXT: pmuludq {{.*}}(%rip), %xmm4
; SSE-NEXT: pmuludq %xmm8, %xmm9 ; SSE-NEXT: pmuludq {{.*}}(%rip), %xmm5
; SSE-NEXT: psrlq $32, %xmm1 ; SSE-NEXT: pmuludq {{.*}}(%rip), %xmm6
; SSE-NEXT: pmuludq %xmm8, %xmm1 ; SSE-NEXT: pmuludq {{.*}}(%rip), %xmm7
; SSE-NEXT: psllq $32, %xmm1
; SSE-NEXT: paddq %xmm9, %xmm1
; SSE-NEXT: movdqa {{.*#+}} xmm8 = [4,5]
; SSE-NEXT: movdqa %xmm2, %xmm9
; SSE-NEXT: pmuludq %xmm8, %xmm9
; SSE-NEXT: psrlq $32, %xmm2
; SSE-NEXT: pmuludq %xmm8, %xmm2
; SSE-NEXT: psllq $32, %xmm2
; SSE-NEXT: paddq %xmm9, %xmm2
; SSE-NEXT: movdqa {{.*#+}} xmm8 = [6,7]
; SSE-NEXT: movdqa %xmm3, %xmm9
; SSE-NEXT: pmuludq %xmm8, %xmm9
; SSE-NEXT: psrlq $32, %xmm3
; SSE-NEXT: pmuludq %xmm8, %xmm3
; SSE-NEXT: psllq $32, %xmm3
; SSE-NEXT: paddq %xmm9, %xmm3
; SSE-NEXT: movdqa {{.*#+}} xmm8 = [8,9]
; SSE-NEXT: movdqa %xmm4, %xmm9
; SSE-NEXT: pmuludq %xmm8, %xmm9
; SSE-NEXT: psrlq $32, %xmm4
; SSE-NEXT: pmuludq %xmm8, %xmm4
; SSE-NEXT: psllq $32, %xmm4
; SSE-NEXT: paddq %xmm9, %xmm4
; SSE-NEXT: movdqa {{.*#+}} xmm8 = [10,11]
; SSE-NEXT: movdqa %xmm5, %xmm9
; SSE-NEXT: pmuludq %xmm8, %xmm9
; SSE-NEXT: psrlq $32, %xmm5
; SSE-NEXT: pmuludq %xmm8, %xmm5
; SSE-NEXT: psllq $32, %xmm5
; SSE-NEXT: paddq %xmm9, %xmm5
; SSE-NEXT: movdqa {{.*#+}} xmm8 = [12,13]
; SSE-NEXT: movdqa %xmm6, %xmm9
; SSE-NEXT: pmuludq %xmm8, %xmm9
; SSE-NEXT: psrlq $32, %xmm6
; SSE-NEXT: pmuludq %xmm8, %xmm6
; SSE-NEXT: psllq $32, %xmm6
; SSE-NEXT: paddq %xmm9, %xmm6
; SSE-NEXT: movdqa {{.*#+}} xmm8 = [14,15]
; SSE-NEXT: movdqa %xmm7, %xmm9
; SSE-NEXT: pmuludq %xmm8, %xmm9
; SSE-NEXT: psrlq $32, %xmm7
; SSE-NEXT: pmuludq %xmm8, %xmm7
; SSE-NEXT: psllq $32, %xmm7
; SSE-NEXT: paddq %xmm9, %xmm7
; SSE-NEXT: movdqa {{.*#+}} xmm8 = [255,0,0,0,0,0,0,0,255,0,0,0,0,0,0,0] ; SSE-NEXT: movdqa {{.*#+}} xmm8 = [255,0,0,0,0,0,0,0,255,0,0,0,0,0,0,0]
; SSE-NEXT: pand %xmm8, %xmm7 ; SSE-NEXT: pand %xmm8, %xmm7
; SSE-NEXT: pand %xmm8, %xmm6 ; SSE-NEXT: pand %xmm8, %xmm6
; SSE-NEXT: packuswb %xmm7, %xmm6 ; SSE-NEXT: packuswb %xmm7, %xmm6
; SSE-NEXT: pand %xmm8, %xmm5 ; SSE-NEXT: pand %xmm8, %xmm5
; SSE-NEXT: pand %xmm8, %xmm4 ; SSE-NEXT: pand %xmm8, %xmm4
; SSE-NEXT: packuswb %xmm5, %xmm4 ; SSE-NEXT: packuswb %xmm5, %xmm4
; SSE-NEXT: packuswb %xmm6, %xmm4 ; SSE-NEXT: packuswb %xmm6, %xmm4
▲ Show 20 Lines • Show All 2,694 Lines • ▼ Show 20 Lines
; complex patterns - often created by vectorizer ; complex patterns - often created by vectorizer
; ;
define <4 x i32> @mul_add_const_v4i64_v4i32(<4 x i32> %a0, <4 x i32> %a1) nounwind { define <4 x i32> @mul_add_const_v4i64_v4i32(<4 x i32> %a0, <4 x i32> %a1) nounwind {
; SSE-LABEL: mul_add_const_v4i64_v4i32: ; SSE-LABEL: mul_add_const_v4i64_v4i32:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm0[0,1,1,3] ; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm0[0,1,1,3]
; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm0[2,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm0[2,1,3,3]
; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm1[0,1,1,3] ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,1,1,3]
; SSE-NEXT: pmuludq %xmm2, %xmm0
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,1,3,3]
; SSE-NEXT: pmuludq %xmm1, %xmm3 ; SSE-NEXT: pmuludq %xmm3, %xmm1
; SSE-NEXT: pxor %xmm0, %xmm0
; SSE-NEXT: pmuludq %xmm0, %xmm1
; SSE-NEXT: psllq $32, %xmm1
; SSE-NEXT: paddq %xmm3, %xmm1
; SSE-NEXT: pmuludq %xmm4, %xmm2
; SSE-NEXT: pmuludq %xmm4, %xmm0
; SSE-NEXT: psllq $32, %xmm0
; SSE-NEXT: paddq %xmm2, %xmm0
; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2] ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
; SSE-NEXT: paddd {{.*}}(%rip), %xmm0 ; SSE-NEXT: paddd {{.*}}(%rip), %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: mul_add_const_v4i64_v4i32: ; AVX-LABEL: mul_add_const_v4i64_v4i32:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpmulld %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vpmulld %xmm1, %xmm0, %xmm0
; AVX-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0 ; AVX-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%1 = sext <4 x i32> %a0 to <4 x i64> %1 = sext <4 x i32> %a0 to <4 x i64>
%2 = sext <4 x i32> %a1 to <4 x i64> %2 = sext <4 x i32> %a1 to <4 x i64>
%3 = mul <4 x i64> %1, %2 %3 = mul <4 x i64> %1, %2
%4 = add <4 x i64> %3, <i64 -3, i64 -1, i64 1, i64 3> %4 = add <4 x i64> %3, <i64 -3, i64 -1, i64 1, i64 3>
%5 = trunc <4 x i64> %4 to <4 x i32> %5 = trunc <4 x i64> %4 to <4 x i32>
ret <4 x i32> %5 ret <4 x i32> %5
} }
define <4 x i32> @mul_add_self_v4i64_v4i32(<4 x i32> %a0, <4 x i32> %a1) nounwind { define <4 x i32> @mul_add_self_v4i64_v4i32(<4 x i32> %a0, <4 x i32> %a1) nounwind {
; SSE-LABEL: mul_add_self_v4i64_v4i32: ; SSE-LABEL: mul_add_self_v4i64_v4i32:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm0[2,3,0,1] ; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm0[0,1,1,3]
; SSE-NEXT: movdqa %xmm3, %xmm4 ; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm0[2,1,3,3]
; SSE-NEXT: psrad $31, %xmm4 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,1,1,3]
; SSE-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm4[0],xmm3[1],xmm4[1] ; SSE-NEXT: pmuludq %xmm2, %xmm0
; SSE-NEXT: movdqa %xmm0, %xmm5 ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,1,3,3]
; SSE-NEXT: psrad $31, %xmm5 ; SSE-NEXT: pmuludq %xmm3, %xmm1
; SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm5[0],xmm0[1],xmm5[1] ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
; SSE-NEXT: pshufd {{.*#+}} xmm6 = xmm1[2,3,0,1] ; SSE-NEXT: paddd %xmm0, %xmm0
; SSE-NEXT: movdqa %xmm6, %xmm7
; SSE-NEXT: psrad $31, %xmm7
; SSE-NEXT: punpckldq {{.*#+}} xmm6 = xmm6[0],xmm7[0],xmm6[1],xmm7[1]
; SSE-NEXT: movdqa %xmm1, %xmm2
; SSE-NEXT: psrad $31, %xmm2
; SSE-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,1,1,3]
; SSE-NEXT: pmuludq %xmm0, %xmm2
; SSE-NEXT: pmuludq %xmm1, %xmm0
; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm5[0,1,1,3]
; SSE-NEXT: pmuludq %xmm1, %xmm5
; SSE-NEXT: paddq %xmm5, %xmm2
; SSE-NEXT: psllq $32, %xmm2
; SSE-NEXT: paddq %xmm0, %xmm2
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm7[0,1,1,3]
; SSE-NEXT: pmuludq %xmm3, %xmm0
; SSE-NEXT: pmuludq %xmm6, %xmm3
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm4[0,1,1,3]
; SSE-NEXT: pmuludq %xmm6, %xmm1
; SSE-NEXT: paddq %xmm1, %xmm0
; SSE-NEXT: psllq $32, %xmm0
; SSE-NEXT: paddq %xmm3, %xmm0
; SSE-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[0,2]
; SSE-NEXT: paddd %xmm2, %xmm2
; SSE-NEXT: movdqa %xmm2, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: mul_add_self_v4i64_v4i32: ; AVX-LABEL: mul_add_self_v4i64_v4i32:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpmulld %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vpmulld %xmm1, %xmm0, %xmm0
; AVX-NEXT: vpaddd %xmm0, %xmm0, %xmm0 ; AVX-NEXT: vpaddd %xmm0, %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%1 = sext <4 x i32> %a0 to <4 x i64> %1 = sext <4 x i32> %a0 to <4 x i64>
%2 = sext <4 x i32> %a1 to <4 x i64> %2 = sext <4 x i32> %a1 to <4 x i64>
%3 = mul <4 x i64> %1, %2 %3 = mul <4 x i64> %1, %2
%4 = add <4 x i64> %3, %3 %4 = add <4 x i64> %3, %3
%5 = trunc <4 x i64> %4 to <4 x i32> %5 = trunc <4 x i64> %4 to <4 x i32>
ret <4 x i32> %5 ret <4 x i32> %5
} }
define <4 x i32> @mul_add_multiuse_v4i64_v4i32(<4 x i32> %a0, <4 x i32> %a1) nounwind { define <4 x i32> @mul_add_multiuse_v4i64_v4i32(<4 x i32> %a0, <4 x i32> %a1) nounwind {
; SSE-LABEL: mul_add_multiuse_v4i64_v4i32: ; SSE-LABEL: mul_add_multiuse_v4i64_v4i32:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm0[0,1,1,3] ; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm0[0,1,1,3]
; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm0[2,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm0[2,1,3,3]
; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm1[0,1,1,3] ; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm1[0,1,1,3]
; SSE-NEXT: pmuludq %xmm2, %xmm4
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,1,3,3]
; SSE-NEXT: pmuludq %xmm1, %xmm3 ; SSE-NEXT: pmuludq %xmm3, %xmm1
; SSE-NEXT: pxor %xmm5, %xmm5 ; SSE-NEXT: shufps {{.*#+}} xmm4 = xmm4[0,2],xmm1[0,2]
; SSE-NEXT: pmuludq %xmm5, %xmm1 ; SSE-NEXT: paddd %xmm4, %xmm0
; SSE-NEXT: psllq $32, %xmm1
; SSE-NEXT: paddq %xmm3, %xmm1
; SSE-NEXT: pmuludq %xmm4, %xmm2
; SSE-NEXT: pmuludq %xmm4, %xmm5
; SSE-NEXT: psllq $32, %xmm5
; SSE-NEXT: paddq %xmm2, %xmm5
; SSE-NEXT: shufps {{.*#+}} xmm5 = xmm5[0,2],xmm1[0,2]
; SSE-NEXT: paddd %xmm5, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: mul_add_multiuse_v4i64_v4i32: ; AVX-LABEL: mul_add_multiuse_v4i64_v4i32:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpmulld %xmm1, %xmm0, %xmm1 ; AVX-NEXT: vpmulld %xmm1, %xmm0, %xmm1
; AVX-NEXT: vpaddd %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vpaddd %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%1 = sext <4 x i32> %a0 to <4 x i64> %1 = sext <4 x i32> %a0 to <4 x i64>
%2 = sext <4 x i32> %a1 to <4 x i64> %2 = sext <4 x i32> %a1 to <4 x i64>
%3 = mul <4 x i64> %1, %2 %3 = mul <4 x i64> %1, %2
%4 = add <4 x i64> %1, %3 %4 = add <4 x i64> %1, %3
%5 = trunc <4 x i64> %4 to <4 x i32> %5 = trunc <4 x i64> %4 to <4 x i32>
ret <4 x i32> %5 ret <4 x i32> %5
} }

test/CodeGen/X86/vector-trunc-math.ll

Show First 20 Lines • Show All 1,817 Lines • ▼ Show 20 Lines
; ;
; mul ; mul
; ;
define <4 x i32> @trunc_mul_v4i64_v4i32(<4 x i64> %a0, <4 x i64> %a1) nounwind { define <4 x i32> @trunc_mul_v4i64_v4i32(<4 x i64> %a0, <4 x i64> %a1) nounwind {
; SSE-LABEL: trunc_mul_v4i64_v4i32: ; SSE-LABEL: trunc_mul_v4i64_v4i32:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movdqa %xmm1, %xmm4
; SSE-NEXT: psrlq $32, %xmm4
; SSE-NEXT: pmuludq %xmm3, %xmm4
; SSE-NEXT: movdqa %xmm3, %xmm5
; SSE-NEXT: psrlq $32, %xmm5
; SSE-NEXT: pmuludq %xmm1, %xmm5
; SSE-NEXT: paddq %xmm4, %xmm5
; SSE-NEXT: psllq $32, %xmm5
; SSE-NEXT: pmuludq %xmm3, %xmm1 ; SSE-NEXT: pmuludq %xmm3, %xmm1
; SSE-NEXT: paddq %xmm5, %xmm1
; SSE-NEXT: movdqa %xmm0, %xmm3
; SSE-NEXT: psrlq $32, %xmm3
; SSE-NEXT: pmuludq %xmm2, %xmm3
; SSE-NEXT: movdqa %xmm2, %xmm4
; SSE-NEXT: psrlq $32, %xmm4
; SSE-NEXT: pmuludq %xmm0, %xmm4
; SSE-NEXT: paddq %xmm3, %xmm4
; SSE-NEXT: psllq $32, %xmm4
; SSE-NEXT: pmuludq %xmm2, %xmm0 ; SSE-NEXT: pmuludq %xmm2, %xmm0
; SSE-NEXT: paddq %xmm4, %xmm0
; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2] ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: trunc_mul_v4i64_v4i32: ; AVX1-LABEL: trunc_mul_v4i64_v4i32:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
; AVX1-NEXT: vshufps {{.*#+}} xmm1 = xmm1[0,2],xmm2[0,2] ; AVX1-NEXT: vshufps {{.*#+}} xmm1 = xmm1[0,2],xmm2[0,2]
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
▲ Show 20 Lines • Show All 230 Lines • ▼ Show 20 Lines; AVX512-NEXT: retq
%1 = mul <8 x i32> %a0, %a1 %1 = mul <8 x i32> %a0, %a1
%2 = trunc <8 x i32> %1 to <8 x i16> %2 = trunc <8 x i32> %1 to <8 x i16>
ret <8 x i16> %2 ret <8 x i16> %2
} }
define <16 x i8> @trunc_mul_v16i64_v16i8(<16 x i64> %a0, <16 x i64> %a1) nounwind { define <16 x i8> @trunc_mul_v16i64_v16i8(<16 x i64> %a0, <16 x i64> %a1) nounwind {
; SSE-LABEL: trunc_mul_v16i64_v16i8: ; SSE-LABEL: trunc_mul_v16i64_v16i8:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm8 ; SSE-NEXT: pmuludq {{[0-9]+}}(%rsp), %xmm0
; SSE-NEXT: movdqa %xmm0, %xmm9 ; SSE-NEXT: pmuludq {{[0-9]+}}(%rsp), %xmm1
; SSE-NEXT: psrlq $32, %xmm9 ; SSE-NEXT: pmuludq {{[0-9]+}}(%rsp), %xmm2
; SSE-NEXT: pmuludq %xmm8, %xmm9 ; SSE-NEXT: pmuludq {{[0-9]+}}(%rsp), %xmm3
; SSE-NEXT: movdqa %xmm8, %xmm10 ; SSE-NEXT: pmuludq {{[0-9]+}}(%rsp), %xmm4
; SSE-NEXT: psrlq $32, %xmm10 ; SSE-NEXT: pmuludq {{[0-9]+}}(%rsp), %xmm5
; SSE-NEXT: pmuludq %xmm0, %xmm10 ; SSE-NEXT: pmuludq {{[0-9]+}}(%rsp), %xmm6
; SSE-NEXT: paddq %xmm9, %xmm10 ; SSE-NEXT: pmuludq {{[0-9]+}}(%rsp), %xmm7
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm9
; SSE-NEXT: psllq $32, %xmm10
; SSE-NEXT: pmuludq %xmm8, %xmm0
; SSE-NEXT: paddq %xmm10, %xmm0
; SSE-NEXT: movdqa %xmm1, %xmm8
; SSE-NEXT: psrlq $32, %xmm8
; SSE-NEXT: pmuludq %xmm9, %xmm8
; SSE-NEXT: movdqa %xmm9, %xmm10
; SSE-NEXT: psrlq $32, %xmm10
; SSE-NEXT: pmuludq %xmm1, %xmm10
; SSE-NEXT: paddq %xmm8, %xmm10
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm8
; SSE-NEXT: psllq $32, %xmm10
; SSE-NEXT: pmuludq %xmm9, %xmm1
; SSE-NEXT: paddq %xmm10, %xmm1
; SSE-NEXT: movdqa %xmm2, %xmm9
; SSE-NEXT: psrlq $32, %xmm9
; SSE-NEXT: pmuludq %xmm8, %xmm9
; SSE-NEXT: movdqa %xmm8, %xmm10
; SSE-NEXT: psrlq $32, %xmm10
; SSE-NEXT: pmuludq %xmm2, %xmm10
; SSE-NEXT: paddq %xmm9, %xmm10
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm9
; SSE-NEXT: psllq $32, %xmm10
; SSE-NEXT: pmuludq %xmm8, %xmm2
; SSE-NEXT: paddq %xmm10, %xmm2
; SSE-NEXT: movdqa %xmm3, %xmm8
; SSE-NEXT: psrlq $32, %xmm8
; SSE-NEXT: pmuludq %xmm9, %xmm8
; SSE-NEXT: movdqa %xmm9, %xmm10
; SSE-NEXT: psrlq $32, %xmm10
; SSE-NEXT: pmuludq %xmm3, %xmm10
; SSE-NEXT: paddq %xmm8, %xmm10
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm8
; SSE-NEXT: psllq $32, %xmm10
; SSE-NEXT: pmuludq %xmm9, %xmm3
; SSE-NEXT: paddq %xmm10, %xmm3
; SSE-NEXT: movdqa %xmm4, %xmm9
; SSE-NEXT: psrlq $32, %xmm9
; SSE-NEXT: pmuludq %xmm8, %xmm9
; SSE-NEXT: movdqa %xmm8, %xmm10
; SSE-NEXT: psrlq $32, %xmm10
; SSE-NEXT: pmuludq %xmm4, %xmm10
; SSE-NEXT: paddq %xmm9, %xmm10
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm9
; SSE-NEXT: psllq $32, %xmm10
; SSE-NEXT: pmuludq %xmm8, %xmm4
; SSE-NEXT: paddq %xmm10, %xmm4
; SSE-NEXT: movdqa %xmm5, %xmm8
; SSE-NEXT: psrlq $32, %xmm8
; SSE-NEXT: pmuludq %xmm9, %xmm8
; SSE-NEXT: movdqa %xmm9, %xmm10
; SSE-NEXT: psrlq $32, %xmm10
; SSE-NEXT: pmuludq %xmm5, %xmm10
; SSE-NEXT: paddq %xmm8, %xmm10
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm8
; SSE-NEXT: psllq $32, %xmm10
; SSE-NEXT: pmuludq %xmm9, %xmm5
; SSE-NEXT: paddq %xmm10, %xmm5
; SSE-NEXT: movdqa %xmm6, %xmm9
; SSE-NEXT: psrlq $32, %xmm9
; SSE-NEXT: pmuludq %xmm8, %xmm9
; SSE-NEXT: movdqa %xmm8, %xmm10
; SSE-NEXT: psrlq $32, %xmm10
; SSE-NEXT: pmuludq %xmm6, %xmm10
; SSE-NEXT: paddq %xmm9, %xmm10
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm9
; SSE-NEXT: psllq $32, %xmm10
; SSE-NEXT: pmuludq %xmm8, %xmm6
; SSE-NEXT: paddq %xmm10, %xmm6
; SSE-NEXT: movdqa %xmm7, %xmm8
; SSE-NEXT: psrlq $32, %xmm8
; SSE-NEXT: pmuludq %xmm9, %xmm8
; SSE-NEXT: movdqa %xmm9, %xmm10
; SSE-NEXT: psrlq $32, %xmm10
; SSE-NEXT: pmuludq %xmm7, %xmm10
; SSE-NEXT: paddq %xmm8, %xmm10
; SSE-NEXT: pmuludq %xmm9, %xmm7
; SSE-NEXT: psllq $32, %xmm10
; SSE-NEXT: paddq %xmm10, %xmm7
; SSE-NEXT: movdqa {{.*#+}} xmm8 = [255,0,0,0,0,0,0,0,255,0,0,0,0,0,0,0] ; SSE-NEXT: movdqa {{.*#+}} xmm8 = [255,0,0,0,0,0,0,0,255,0,0,0,0,0,0,0]
; SSE-NEXT: pand %xmm8, %xmm7 ; SSE-NEXT: pand %xmm8, %xmm7
; SSE-NEXT: pand %xmm8, %xmm6 ; SSE-NEXT: pand %xmm8, %xmm6
; SSE-NEXT: packuswb %xmm7, %xmm6 ; SSE-NEXT: packuswb %xmm7, %xmm6
; SSE-NEXT: pand %xmm8, %xmm5 ; SSE-NEXT: pand %xmm8, %xmm5
; SSE-NEXT: pand %xmm8, %xmm4 ; SSE-NEXT: pand %xmm8, %xmm4
; SSE-NEXT: packuswb %xmm5, %xmm4 ; SSE-NEXT: packuswb %xmm5, %xmm4
; SSE-NEXT: packuswb %xmm6, %xmm4 ; SSE-NEXT: packuswb %xmm6, %xmm4
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; ;
; mul to constant ; mul to constant
; ;
define <4 x i32> @trunc_mul_const_v4i64_v4i32(<4 x i64> %a0) nounwind { define <4 x i32> @trunc_mul_const_v4i64_v4i32(<4 x i64> %a0) nounwind {
; SSE-LABEL: trunc_mul_const_v4i64_v4i32: ; SSE-LABEL: trunc_mul_const_v4i64_v4i32:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movdqa {{.*#+}} xmm2 = [2,3]
; SSE-NEXT: movdqa %xmm1, %xmm3
; SSE-NEXT: pmuludq %xmm2, %xmm3
; SSE-NEXT: psrlq $32, %xmm1
; SSE-NEXT: pmuludq %xmm2, %xmm1
; SSE-NEXT: psllq $32, %xmm1
; SSE-NEXT: paddq %xmm3, %xmm1
; SSE-NEXT: movl $1, %eax ; SSE-NEXT: movl $1, %eax
; SSE-NEXT: movq %rax, %xmm2 ; SSE-NEXT: movq %rax, %xmm2
; SSE-NEXT: pslldq {{.*#+}} xmm2 = zero,zero,zero,zero,zero,zero,zero,zero,xmm2[0,1,2,3,4,5,6,7] ; SSE-NEXT: pslldq {{.*#+}} xmm2 = zero,zero,zero,zero,zero,zero,zero,zero,xmm2[0,1,2,3,4,5,6,7]
; SSE-NEXT: movdqa %xmm0, %xmm3
; SSE-NEXT: pmuludq %xmm2, %xmm3
; SSE-NEXT: psrlq $32, %xmm0
; SSE-NEXT: pmuludq %xmm2, %xmm0 ; SSE-NEXT: pmuludq %xmm2, %xmm0
; SSE-NEXT: psllq $32, %xmm0 ; SSE-NEXT: pmuludq {{.*}}(%rip), %xmm1
; SSE-NEXT: paddq %xmm3, %xmm0
; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2] ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: trunc_mul_const_v4i64_v4i32: ; AVX1-LABEL: trunc_mul_const_v4i64_v4i32:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX1-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2] ; AVX1-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
; AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0 ; AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
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} }
define <16 x i8> @trunc_mul_const_v16i64_v16i8(<16 x i64> %a0) nounwind { define <16 x i8> @trunc_mul_const_v16i64_v16i8(<16 x i64> %a0) nounwind {
; SSE-LABEL: trunc_mul_const_v16i64_v16i8: ; SSE-LABEL: trunc_mul_const_v16i64_v16i8:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movl $1, %eax ; SSE-NEXT: movl $1, %eax
; SSE-NEXT: movq %rax, %xmm8 ; SSE-NEXT: movq %rax, %xmm8
; SSE-NEXT: pslldq {{.*#+}} xmm8 = zero,zero,zero,zero,zero,zero,zero,zero,xmm8[0,1,2,3,4,5,6,7] ; SSE-NEXT: pslldq {{.*#+}} xmm8 = zero,zero,zero,zero,zero,zero,zero,zero,xmm8[0,1,2,3,4,5,6,7]
; SSE-NEXT: movdqa %xmm0, %xmm9
; SSE-NEXT: pmuludq %xmm8, %xmm9
; SSE-NEXT: psrlq $32, %xmm0
; SSE-NEXT: pmuludq %xmm8, %xmm0 ; SSE-NEXT: pmuludq %xmm8, %xmm0
; SSE-NEXT: psllq $32, %xmm0 ; SSE-NEXT: pmuludq {{.*}}(%rip), %xmm1
; SSE-NEXT: paddq %xmm9, %xmm0 ; SSE-NEXT: pmuludq {{.*}}(%rip), %xmm2
; SSE-NEXT: movdqa {{.*#+}} xmm8 = [2,3] ; SSE-NEXT: pmuludq {{.*}}(%rip), %xmm3
; SSE-NEXT: movdqa %xmm1, %xmm9 ; SSE-NEXT: pmuludq {{.*}}(%rip), %xmm4
; SSE-NEXT: pmuludq %xmm8, %xmm9 ; SSE-NEXT: pmuludq {{.*}}(%rip), %xmm5
; SSE-NEXT: psrlq $32, %xmm1 ; SSE-NEXT: pmuludq {{.*}}(%rip), %xmm6
; SSE-NEXT: pmuludq %xmm8, %xmm1 ; SSE-NEXT: pmuludq {{.*}}(%rip), %xmm7
; SSE-NEXT: psllq $32, %xmm1
; SSE-NEXT: paddq %xmm9, %xmm1
; SSE-NEXT: movdqa {{.*#+}} xmm8 = [4,5]
; SSE-NEXT: movdqa %xmm2, %xmm9
; SSE-NEXT: pmuludq %xmm8, %xmm9
; SSE-NEXT: psrlq $32, %xmm2
; SSE-NEXT: pmuludq %xmm8, %xmm2
; SSE-NEXT: psllq $32, %xmm2
; SSE-NEXT: paddq %xmm9, %xmm2
; SSE-NEXT: movdqa {{.*#+}} xmm8 = [6,7]
; SSE-NEXT: movdqa %xmm3, %xmm9
; SSE-NEXT: pmuludq %xmm8, %xmm9
; SSE-NEXT: psrlq $32, %xmm3
; SSE-NEXT: pmuludq %xmm8, %xmm3
; SSE-NEXT: psllq $32, %xmm3
; SSE-NEXT: paddq %xmm9, %xmm3
; SSE-NEXT: movdqa {{.*#+}} xmm8 = [8,9]
; SSE-NEXT: movdqa %xmm4, %xmm9
; SSE-NEXT: pmuludq %xmm8, %xmm9
; SSE-NEXT: psrlq $32, %xmm4
; SSE-NEXT: pmuludq %xmm8, %xmm4
; SSE-NEXT: psllq $32, %xmm4
; SSE-NEXT: paddq %xmm9, %xmm4
; SSE-NEXT: movdqa {{.*#+}} xmm8 = [10,11]
; SSE-NEXT: movdqa %xmm5, %xmm9
; SSE-NEXT: pmuludq %xmm8, %xmm9
; SSE-NEXT: psrlq $32, %xmm5
; SSE-NEXT: pmuludq %xmm8, %xmm5
; SSE-NEXT: psllq $32, %xmm5
; SSE-NEXT: paddq %xmm9, %xmm5
; SSE-NEXT: movdqa {{.*#+}} xmm8 = [12,13]
; SSE-NEXT: movdqa %xmm6, %xmm9
; SSE-NEXT: pmuludq %xmm8, %xmm9
; SSE-NEXT: psrlq $32, %xmm6
; SSE-NEXT: pmuludq %xmm8, %xmm6
; SSE-NEXT: psllq $32, %xmm6
; SSE-NEXT: paddq %xmm9, %xmm6
; SSE-NEXT: movdqa {{.*#+}} xmm8 = [14,15]
; SSE-NEXT: movdqa %xmm7, %xmm9
; SSE-NEXT: pmuludq %xmm8, %xmm9
; SSE-NEXT: psrlq $32, %xmm7
; SSE-NEXT: pmuludq %xmm8, %xmm7
; SSE-NEXT: psllq $32, %xmm7
; SSE-NEXT: paddq %xmm9, %xmm7
; SSE-NEXT: movdqa {{.*#+}} xmm8 = [255,0,0,0,0,0,0,0,255,0,0,0,0,0,0,0] ; SSE-NEXT: movdqa {{.*#+}} xmm8 = [255,0,0,0,0,0,0,0,255,0,0,0,0,0,0,0]
; SSE-NEXT: pand %xmm8, %xmm7 ; SSE-NEXT: pand %xmm8, %xmm7
; SSE-NEXT: pand %xmm8, %xmm6 ; SSE-NEXT: pand %xmm8, %xmm6
; SSE-NEXT: packuswb %xmm7, %xmm6 ; SSE-NEXT: packuswb %xmm7, %xmm6
; SSE-NEXT: pand %xmm8, %xmm5 ; SSE-NEXT: pand %xmm8, %xmm5
; SSE-NEXT: pand %xmm8, %xmm4 ; SSE-NEXT: pand %xmm8, %xmm4
; SSE-NEXT: packuswb %xmm5, %xmm4 ; SSE-NEXT: packuswb %xmm5, %xmm4
; SSE-NEXT: packuswb %xmm6, %xmm4 ; SSE-NEXT: packuswb %xmm6, %xmm4
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; complex patterns - often created by vectorizer ; complex patterns - often created by vectorizer
; ;
define <4 x i32> @mul_add_const_v4i64_v4i32(<4 x i32> %a0, <4 x i32> %a1) nounwind { define <4 x i32> @mul_add_const_v4i64_v4i32(<4 x i32> %a0, <4 x i32> %a1) nounwind {
; SSE-LABEL: mul_add_const_v4i64_v4i32: ; SSE-LABEL: mul_add_const_v4i64_v4i32:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm0[0,1,1,3] ; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm0[0,1,1,3]
; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm0[2,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm0[2,1,3,3]
; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm1[0,1,1,3] ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,1,1,3]
; SSE-NEXT: pmuludq %xmm2, %xmm0
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,1,3,3]
; SSE-NEXT: pmuludq %xmm1, %xmm3 ; SSE-NEXT: pmuludq %xmm3, %xmm1
; SSE-NEXT: pxor %xmm0, %xmm0
; SSE-NEXT: pmuludq %xmm0, %xmm1
; SSE-NEXT: psllq $32, %xmm1
; SSE-NEXT: paddq %xmm3, %xmm1
; SSE-NEXT: pmuludq %xmm4, %xmm2
; SSE-NEXT: pmuludq %xmm4, %xmm0
; SSE-NEXT: psllq $32, %xmm0
; SSE-NEXT: paddq %xmm2, %xmm0
; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2] ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
; SSE-NEXT: paddd {{.*}}(%rip), %xmm0 ; SSE-NEXT: paddd {{.*}}(%rip), %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: mul_add_const_v4i64_v4i32: ; AVX-LABEL: mul_add_const_v4i64_v4i32:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpmulld %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vpmulld %xmm1, %xmm0, %xmm0
; AVX-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0 ; AVX-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%1 = sext <4 x i32> %a0 to <4 x i64> %1 = sext <4 x i32> %a0 to <4 x i64>
%2 = sext <4 x i32> %a1 to <4 x i64> %2 = sext <4 x i32> %a1 to <4 x i64>
%3 = mul <4 x i64> %1, %2 %3 = mul <4 x i64> %1, %2
%4 = add <4 x i64> %3, <i64 -3, i64 -1, i64 1, i64 3> %4 = add <4 x i64> %3, <i64 -3, i64 -1, i64 1, i64 3>
%5 = trunc <4 x i64> %4 to <4 x i32> %5 = trunc <4 x i64> %4 to <4 x i32>
ret <4 x i32> %5 ret <4 x i32> %5
} }
define <4 x i32> @mul_add_self_v4i64_v4i32(<4 x i32> %a0, <4 x i32> %a1) nounwind { define <4 x i32> @mul_add_self_v4i64_v4i32(<4 x i32> %a0, <4 x i32> %a1) nounwind {
; SSE-LABEL: mul_add_self_v4i64_v4i32: ; SSE-LABEL: mul_add_self_v4i64_v4i32:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm0[2,3,0,1] ; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm0[0,1,1,3]
; SSE-NEXT: movdqa %xmm3, %xmm4 ; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm0[2,1,3,3]
; SSE-NEXT: psrad $31, %xmm4 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,1,1,3]
; SSE-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm4[0],xmm3[1],xmm4[1] ; SSE-NEXT: pmuludq %xmm2, %xmm0
; SSE-NEXT: movdqa %xmm0, %xmm5 ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,1,3,3]
; SSE-NEXT: psrad $31, %xmm5 ; SSE-NEXT: pmuludq %xmm3, %xmm1
; SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm5[0],xmm0[1],xmm5[1] ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
; SSE-NEXT: pshufd {{.*#+}} xmm6 = xmm1[2,3,0,1] ; SSE-NEXT: paddd %xmm0, %xmm0
; SSE-NEXT: movdqa %xmm6, %xmm7
; SSE-NEXT: psrad $31, %xmm7
; SSE-NEXT: punpckldq {{.*#+}} xmm6 = xmm6[0],xmm7[0],xmm6[1],xmm7[1]
; SSE-NEXT: movdqa %xmm1, %xmm2
; SSE-NEXT: psrad $31, %xmm2
; SSE-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,1,1,3]
; SSE-NEXT: pmuludq %xmm0, %xmm2
; SSE-NEXT: pmuludq %xmm1, %xmm0
; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm5[0,1,1,3]
; SSE-NEXT: pmuludq %xmm1, %xmm5
; SSE-NEXT: paddq %xmm5, %xmm2
; SSE-NEXT: psllq $32, %xmm2
; SSE-NEXT: paddq %xmm0, %xmm2
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm7[0,1,1,3]
; SSE-NEXT: pmuludq %xmm3, %xmm0
; SSE-NEXT: pmuludq %xmm6, %xmm3
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm4[0,1,1,3]
; SSE-NEXT: pmuludq %xmm6, %xmm1
; SSE-NEXT: paddq %xmm1, %xmm0
; SSE-NEXT: psllq $32, %xmm0
; SSE-NEXT: paddq %xmm3, %xmm0
; SSE-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[0,2]
; SSE-NEXT: paddd %xmm2, %xmm2
; SSE-NEXT: movdqa %xmm2, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: mul_add_self_v4i64_v4i32: ; AVX-LABEL: mul_add_self_v4i64_v4i32:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpmulld %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vpmulld %xmm1, %xmm0, %xmm0
; AVX-NEXT: vpaddd %xmm0, %xmm0, %xmm0 ; AVX-NEXT: vpaddd %xmm0, %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%1 = sext <4 x i32> %a0 to <4 x i64> %1 = sext <4 x i32> %a0 to <4 x i64>
%2 = sext <4 x i32> %a1 to <4 x i64> %2 = sext <4 x i32> %a1 to <4 x i64>
%3 = mul <4 x i64> %1, %2 %3 = mul <4 x i64> %1, %2
%4 = add <4 x i64> %3, %3 %4 = add <4 x i64> %3, %3
%5 = trunc <4 x i64> %4 to <4 x i32> %5 = trunc <4 x i64> %4 to <4 x i32>
ret <4 x i32> %5 ret <4 x i32> %5
} }
define <4 x i32> @mul_add_multiuse_v4i64_v4i32(<4 x i32> %a0, <4 x i32> %a1) nounwind { define <4 x i32> @mul_add_multiuse_v4i64_v4i32(<4 x i32> %a0, <4 x i32> %a1) nounwind {
; SSE-LABEL: mul_add_multiuse_v4i64_v4i32: ; SSE-LABEL: mul_add_multiuse_v4i64_v4i32:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm0[0,1,1,3] ; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm0[0,1,1,3]
; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm0[2,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm0[2,1,3,3]
; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm1[0,1,1,3] ; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm1[0,1,1,3]
; SSE-NEXT: pmuludq %xmm2, %xmm4
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,1,3,3]
; SSE-NEXT: pmuludq %xmm1, %xmm3 ; SSE-NEXT: pmuludq %xmm3, %xmm1
; SSE-NEXT: pxor %xmm5, %xmm5 ; SSE-NEXT: shufps {{.*#+}} xmm4 = xmm4[0,2],xmm1[0,2]
; SSE-NEXT: pmuludq %xmm5, %xmm1 ; SSE-NEXT: paddd %xmm4, %xmm0
; SSE-NEXT: psllq $32, %xmm1
; SSE-NEXT: paddq %xmm3, %xmm1
; SSE-NEXT: pmuludq %xmm4, %xmm2
; SSE-NEXT: pmuludq %xmm4, %xmm5
; SSE-NEXT: psllq $32, %xmm5
; SSE-NEXT: paddq %xmm2, %xmm5
; SSE-NEXT: shufps {{.*#+}} xmm5 = xmm5[0,2],xmm1[0,2]
; SSE-NEXT: paddd %xmm5, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: mul_add_multiuse_v4i64_v4i32: ; AVX-LABEL: mul_add_multiuse_v4i64_v4i32:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpmulld %xmm1, %xmm0, %xmm1 ; AVX-NEXT: vpmulld %xmm1, %xmm0, %xmm1
; AVX-NEXT: vpaddd %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vpaddd %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%1 = sext <4 x i32> %a0 to <4 x i64> %1 = sext <4 x i32> %a0 to <4 x i64>
%2 = sext <4 x i32> %a1 to <4 x i64> %2 = sext <4 x i32> %a1 to <4 x i64>
%3 = mul <4 x i64> %1, %2 %3 = mul <4 x i64> %1, %2
%4 = add <4 x i64> %1, %3 %4 = add <4 x i64> %1, %3
%5 = trunc <4 x i64> %4 to <4 x i32> %5 = trunc <4 x i64> %4 to <4 x i32>
ret <4 x i32> %5 ret <4 x i32> %5
} }