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Differential D54440

Fixed DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT i1 handling
ClosedPublic

Authored by rampitec on Nov 12 2018, 12:51 PM.

Details

Reviewers
arsenm
Commits
rG35de877e8c3b: Fixed DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT i1 handling
rL346795: Fixed DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT i1 handling
Summary

Legalizer used to request an ext load from i8 to i1 when promoting
vector element type to i8. Fixed.

Diff Detail

Repository
rL LLVM

Event Timeline

rampitec created this revision.Nov 12 2018, 12:51 PM
Herald added a subscriber: wdng. · View Herald TranscriptNov 12 2018, 12:51 PM
rampitec mentioned this in D54351: [AMDGPU] combine extractelement into several selects.Nov 12 2018, 12:51 PM
rampitec updated this revision to Diff 173750.Nov 12 2018, 1:32 PM

Added stripped test (a relevant portion) from D54351.

Herald added subscribers: nhaehnle, jvesely. · View Herald TranscriptNov 12 2018, 1:32 PM
rampitec edited the summary of this revision. (Show Details)Nov 12 2018, 1:32 PM
arsenm added a comment.Nov 12 2018, 3:17 PM

I’m not sure this will use the right memory layout

rampitec added a comment.EditedNov 12 2018, 3:19 PM
In D54440#1296242, @arsenm wrote:

I’m not sure this will use the right memory layout

If you look at line 1922 it just uses i8 regardless. This might be a separate issue. The issue addressed here is when an extload requested from wider to a narrower type.

arsenm accepted this revision.Nov 13 2018, 9:00 AM

LGTM, but add a fixme since something will be necessary

This revision is now accepted and ready to land.Nov 13 2018, 9:00 AM
rampitec updated this revision to Diff 173870.Nov 13 2018, 9:40 AM

Added comment.

Closed by commit rL346795: Fixed DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT i1 handling (authored by rampitec). · Explain WhyNov 13 2018, 12:29 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
CodeGen/
SelectionDAG/
9 lines
test/
CodeGen/
AMDGPU/
28 lines

Diff 173914

llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

Show First 20 Lines • Show All 1,928 Lines • ▼ Show 20 LinesSDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
SDValue StackPtr = DAG.CreateStackTemporary(VecVT); SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
auto &MF = DAG.getMachineFunction(); auto &MF = DAG.getMachineFunction();
auto FrameIndex = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex(); auto FrameIndex = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
auto PtrInfo = MachinePointerInfo::getFixedStack(MF, FrameIndex); auto PtrInfo = MachinePointerInfo::getFixedStack(MF, FrameIndex);
SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, PtrInfo); SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, PtrInfo);
// Load back the required element. // Load back the required element.
StackPtr = TLI.getVectorElementPointer(DAG, StackPtr, VecVT, Idx); StackPtr = TLI.getVectorElementPointer(DAG, StackPtr, VecVT, Idx);
// FIXME: This is to handle i1 vectors with elements promoted to i8.
// i1 vector handling needs general improvement.
if (N->getValueType(0).bitsLT(EltVT)) {
SDValue Load = DAG.getLoad(EltVT, dl, Store, StackPtr,
MachinePointerInfo::getUnknownStack(DAG.getMachineFunction()));
return DAG.getZExtOrTrunc(Load, dl, N->getValueType(0));
}
return DAG.getExtLoad( return DAG.getExtLoad(
ISD::EXTLOAD, dl, N->getValueType(0), Store, StackPtr, ISD::EXTLOAD, dl, N->getValueType(0), Store, StackPtr,
MachinePointerInfo::getUnknownStack(DAG.getMachineFunction()), EltVT); MachinePointerInfo::getUnknownStack(DAG.getMachineFunction()), EltVT);
} }
SDValue DAGTypeLegalizer::SplitVecOp_ExtVecInRegOp(SDNode *N) { SDValue DAGTypeLegalizer::SplitVecOp_ExtVecInRegOp(SDNode *N) {
SDValue Lo, Hi; SDValue Lo, Hi;
▲ Show 20 Lines • Show All 2,528 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/AMDGPU/extract_vector_dynelt.ll

; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN %s
; GCN-LABEL: {{^}}bit4_extelt:
; GCN-DAG: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0
; GCN-DAG: v_mov_b32_e32 [[ONE:v[0-9]+]], 1
; GCN-DAG: buffer_store_byte [[ZERO]],
; GCN-DAG: buffer_store_byte [[ONE]],
; GCN-DAG: buffer_store_byte [[ZERO]],
; GCN-DAG: buffer_store_byte [[ONE]],
; GCN: buffer_load_ubyte [[LOAD:v[0-9]+]],
; GCN: v_and_b32_e32 [[RES:v[0-9]+]], 1, [[LOAD]]
; GCN: flat_store_dword v[{{[0-9:]+}}], [[RES]]
define amdgpu_kernel void @bit4_extelt(i32 addrspace(1)* %out, i32 %sel) {
entry:
%ext = extractelement <4 x i1> <i1 0, i1 1, i1 0, i1 1>, i32 %sel
%zext = zext i1 %ext to i32
store i32 %zext, i32 addrspace(1)* %out
ret void
}
; GCN-LABEL: {{^}}bit128_extelt:
define amdgpu_kernel void @bit128_extelt(i32 addrspace(1)* %out, i32 %sel) {
entry:
%ext = extractelement <128 x i1> <i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0>, i32 %sel
%zext = zext i1 %ext to i32
store i32 %zext, i32 addrspace(1)* %out
ret void
}