[SelectionDAG] Handle constant range [0,1) in lowerRangeToAssertZExt

[scott.linder]

Summary

lowerRangeToAssertZExt currently relies on something like EarlyCSE having eliminated the constant range [0,1). At -O0 this leads to an assert.

[rampitec]

LGTM

[nhaehnle]

test/CodeGen/AMDGPU/zext-lid.ll

49 ↗

(On Diff #171772)

Needs an OPT-LABEL

[scott.linder]

Add lit LABEL for test case

[nhaehnle]

LGTM

llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

SDValue SelectionDAGBuilder::lowerRangeToAssertZExt(SelectionDAG &DAG,
   if (CR.isFullSet() || CR.isEmptySet() || CR.isWrappedSet())
     return Op;
 
   APInt Lo = CR.getUnsignedMin();
   if (!Lo.isMinValue())
     return Op;
 
   APInt Hi = CR.getUnsignedMax();
-  unsigned Bits = Hi.getActiveBits();
+  unsigned Bits = std::max(Hi.getActiveBits(),
+                           static_cast<unsigned>(IntegerType::MIN_INT_BITS));
 
   EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), Bits);
 
   SDLoc SL = getCurSDLoc();
 
   SDValue ZExt = DAG.getNode(ISD::AssertZext, SL, Op.getValueType(), Op,
                              DAG.getValueType(SmallVT));
   unsigned NumVals = Op.getNode()->getNumValues();

llvm/trunk/test/CodeGen/AMDGPU/zext-lid.ll

 ; RUN: llc -march=amdgcn < %s | FileCheck %s
+; RUN: llc -O0 -march=amdgcn < %s | FileCheck %s
 ; RUN: opt -S -mtriple=amdgcn-- -amdgpu-lower-intrinsics < %s | FileCheck -check-prefix=OPT %s
 
 ; CHECK-NOT: and_b32
 
 ; OPT-LABEL: @zext_grp_size_128
 ; OPT: tail call i32 @llvm.amdgcn.workitem.id.x(), !range !0
 ; OPT: tail call i32 @llvm.amdgcn.workitem.id.y(), !range !0
 ; OPT: tail call i32 @llvm.amdgcn.workitem.id.z(), !range !0
bb:
   store i32 %tmp3, i32 addrspace(1)* %tmp4, align 4
   %tmp5 = tail call i32 @llvm.amdgcn.workitem.id.z()
   %tmp6 = and i32 %tmp5, 1
   %tmp7 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 2
   store i32 %tmp6, i32 addrspace(1)* %tmp7, align 4
   ret void
 }
 
+; When EarlyCSE is not run this call produces a range max with 0 active bits,
+; which is a special case as an AssertZext from width 0 is invalid.
+; OPT-LABEL: @zext_grp_size_1x1x1
+; OPT: tail call i32 @llvm.amdgcn.workitem.id.x(), !range !4
+define amdgpu_kernel void @zext_grp_size_1x1x1(i32 addrspace(1)* nocapture %arg) #0 !reqd_work_group_size !1 {
+  %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
+  %tmp1 = and i32 %tmp, 1
+  store i32 %tmp1, i32 addrspace(1)* %arg, align 4
+  ret void
+}
+
 ; OPT-LABEL: @zext_grp_size_512
-; OPT: tail call i32 @llvm.amdgcn.workitem.id.x(), !range !5
-; OPT: tail call i32 @llvm.amdgcn.workitem.id.y(), !range !5
-; OPT: tail call i32 @llvm.amdgcn.workitem.id.z(), !range !5
+; OPT: tail call i32 @llvm.amdgcn.workitem.id.x(), !range !6
+; OPT: tail call i32 @llvm.amdgcn.workitem.id.y(), !range !6
+; OPT: tail call i32 @llvm.amdgcn.workitem.id.z(), !range !6
 define amdgpu_kernel void @zext_grp_size_512(i32 addrspace(1)* nocapture %arg) #1 {
 bb:
   %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
   %tmp1 = and i32 %tmp, 65535
   store i32 %tmp1, i32 addrspace(1)* %arg, align 4
   %tmp2 = tail call i32 @llvm.amdgcn.workitem.id.y()
   %tmp3 = and i32 %tmp2, 65535
   %tmp4 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 1

 entry:
   %id = tail call i32 @llvm.amdgcn.workitem.id.x()
   %and = and i32 %id, 1023
   store i32 %and, i32 addrspace(1)* %out, align 4
   ret void
 }
 
 ; OPT-LABEL: @func_test_workitem_id_x_default_range(
-; OPT: tail call i32 @llvm.amdgcn.workitem.id.x(), !range !6
+; OPT: tail call i32 @llvm.amdgcn.workitem.id.x(), !range !7
 define void @func_test_workitem_id_x_default_range(i32 addrspace(1)* nocapture %out) #4 {
 entry:
   %id = tail call i32 @llvm.amdgcn.workitem.id.x()
   %and = and i32 %id, 1023
   store i32 %and, i32 addrspace(1)* %out, align 4
   ret void
 }
 
 declare i32 @llvm.amdgcn.workitem.id.x() #2
 
 declare i32 @llvm.amdgcn.workitem.id.y() #2
 
 declare i32 @llvm.amdgcn.workitem.id.z() #2
 
 attributes #0 = { nounwind "amdgpu-flat-work-group-size"="64,128" }
 attributes #1 = { nounwind "amdgpu-flat-work-group-size"="512,512" }
 attributes #2 = { nounwind readnone speculatable }
 attributes #3 = { nounwind readnone }
 attributes #4 = { nounwind }
 
 !0 = !{i32 32, i32 4, i32 1}
+!1 = !{i32 1, i32 1, i32 1}
 
 ; OPT: !0 = !{i32 0, i32 128}
 ; OPT: !1 = !{i32 32, i32 4, i32 1}
 ; OPT: !2 = !{i32 0, i32 32}
 ; OPT: !3 = !{i32 0, i32 4}
 ; OPT: !4 = !{i32 0, i32 1}
-; OPT: !5 = !{i32 0, i32 512}
-; OPT: !6 = !{i32 0, i32 1024}
+; OPT: !5 = !{i32 1, i32 1, i32 1}
+; OPT: !6 = !{i32 0, i32 512}
+; OPT: !7 = !{i32 0, i32 1024}