Check shouldReduceLoadWidth from SimplifySetCC

[rampitec]

Summary

SimplifySetCC could shrink a load without checking for
profitability or legality of such shink with a target.

Added checks to prevent shrinking of aligned scalar loads
in AMDGPU below dword as scalar engine does not support it.

[arsenm]

lib/Target/AMDGPU/AMDGPUISelLowering.cpp

676–677

What about the load from uniform global that uses a scalar load?

[arsenm]

lib/Target/AMDGPU/AMDGPUISelLowering.cpp

676–677

Also the address space check should go before the isUNiformMMO

[rampitec]

lib/Target/AMDGPU/AMDGPUISelLowering.cpp

676–677

Something else prevents it, but I have added a check for completeness.

[rampitec]

Added global address check and changed order of checks.

[arsenm]

LGTM

lib/CodeGen/SelectionDAG/TargetLowering.cpp

if (DCI.isBeforeLegalize() &&
               break;
             }
             newMask <<= width;
           }
         }
       }
       if (bestWidth) {
         EVT newVT = EVT::getIntegerVT(*DAG.getContext(), bestWidth);
-        if (newVT.isRound()) {
+        if (newVT.isRound() &&
+            shouldReduceLoadWidth(Lod, ISD::NON_EXTLOAD, newVT)) {
           EVT PtrType = Lod->getOperand(1).getValueType();
           SDValue Ptr = Lod->getBasePtr();
           if (bestOffset != 0)
             Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
                               DAG.getConstant(bestOffset, dl, PtrType));
           unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset);
           SDValue NewLoad = DAG.getLoad(
               newVT, dl, Lod->getChain(), Ptr,

lib/Target/AMDGPU/AMDGPUISelLowering.cpp

bool AMDGPUTargetLowering::shouldReduceLoadWidth(SDNode *N,
 
   // If we are reducing to a 32-bit load, this is always better.
   if (NewSize == 32)
     return true;
 
   EVT OldVT = N->getValueType(0);
   unsigned OldSize = OldVT.getStoreSizeInBits();
 
+  MemSDNode *MN = cast<MemSDNode>(N);
+  unsigned AS = MN->getAddressSpace();
+  // Do not shrink an aligned scalar load to sub-dword.
+  // Scalar engine cannot do sub-dword loads.
+  if (OldSize >= 32 && NewSize < 32 && MN->getAlignment() >= 4 &&
+      (AS == AMDGPUAS::CONSTANT_ADDRESS ||
+       AS == AMDGPUAS::CONSTANT_ADDRESS_32BIT ||
+       (isa<LoadSDNode>(N) &&
+        AS == AMDGPUAS::GLOBAL_ADDRESS && MN->isInvariant())) &&
+      AMDGPUInstrInfo::isUniformMMO(MN->getMemOperand()))
+    return false;
+
   // Don't produce extloads from sub 32-bit types. SI doesn't have scalar
   // extloads, so doing one requires using a buffer_load. In cases where we
   // still couldn't use a scalar load, using the wider load shouldn't really
   // hurt anything.
 
   // If the old size already had to be an extload, there's no harm in continuing
   // to reduce the width.
   return (OldSize < 32);

test/CodeGen/AMDGPU/setcc-limit-load-shrink.ll

+; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
+
+; GCN-LABEL: {{^}}const_load_no_shrink_dword_to_unaligned_byte:
+; GCN: s_load_dword [[LD:s[0-9]+]],
+; GCN: s_bfe_i32 s{{[0-9]+}}, [[LD]], 0x10013
+define amdgpu_kernel void @const_load_no_shrink_dword_to_unaligned_byte(i32 addrspace(1)* %out, i32 addrspace(4)* %in, i32 %x) {
+  %ptr = getelementptr i32, i32 addrspace(4)* %in, i32 %x
+  %load = load i32, i32 addrspace(4)* %ptr, align 4
+  %and = and i32 %load, 524288
+  %cmp = icmp eq i32 %and, 0
+  %sel = select i1 %cmp, i32 0, i32 -1
+  store i32 %sel, i32 addrspace(1)* %out
+  ret void
+}
+
+; GCN-LABEL: const_load_no_shrink_dword_to_aligned_byte:
+; GCN: s_load_dword [[LD:s[0-9]+]],
+; GCN: s_bfe_i32 s{{[0-9]+}}, [[LD]], 0x10003
+define amdgpu_kernel void @const_load_no_shrink_dword_to_aligned_byte(i32 addrspace(1)* %out, i32 addrspace(4)* %in, i32 %x) {
+  %ptr = getelementptr i32, i32 addrspace(4)* %in, i32 %x
+  %load = load i32, i32 addrspace(4)* %ptr, align 4
+  %and = and i32 %load, 8
+  %cmp = icmp eq i32 %and, 0
+  %sel = select i1 %cmp, i32 0, i32 -1
+  store i32 %sel, i32 addrspace(1)* %out
+  ret void
+}
+
+; GCN-LABEL: global_load_no_shrink_dword_to_unaligned_byte:
+; GCN: s_load_dword [[LD:s[0-9]+]],
+; GCN: s_bfe_i32 s{{[0-9]+}}, [[LD]], 0x10013
+define amdgpu_kernel void @global_load_no_shrink_dword_to_unaligned_byte(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in, i32 %x) {
+  %ptr = getelementptr i32, i32 addrspace(1)* %in, i32 %x
+  %load = load i32, i32 addrspace(1)* %ptr, align 4
+  %and = and i32 %load, 524288
+  %cmp = icmp eq i32 %and, 0
+  %sel = select i1 %cmp, i32 0, i32 -1
+  store i32 %sel, i32 addrspace(1)* %out
+  ret void
+}
+
+; GCN-LABEL: global_load_no_shrink_dword_to_aligned_byte:
+; GCN: s_load_dword [[LD:s[0-9]+]],
+; GCN: s_bfe_i32 s{{[0-9]+}}, [[LD]], 0x10003
+define amdgpu_kernel void @global_load_no_shrink_dword_to_aligned_byte(i32 addrspace(1)* %out, i32 addrspace(1)* %in, i32 %x) {
+  %ptr = getelementptr i32, i32 addrspace(1)* %in, i32 %x
+  %load = load i32, i32 addrspace(1)* %ptr, align 4
+  %and = and i32 %load, 8
+  %cmp = icmp eq i32 %and, 0
+  %sel = select i1 %cmp, i32 0, i32 -1
+  store i32 %sel, i32 addrspace(1)* %out
+  ret void
+}
+
+; GCN-LABEL: const_load_shrink_dword_to_unaligned_byte:
+; GCN: global_load_ushort
+define amdgpu_kernel void @const_load_shrink_dword_to_unaligned_byte(i32 addrspace(1)* %out, i32 addrspace(4)* %in, i32 %x) {
+  %ptr = getelementptr i32, i32 addrspace(4)* %in, i32 %x
+  %load = load i32, i32 addrspace(4)* %ptr, align 2
+  %and = and i32 %load, 524288
+  %cmp = icmp eq i32 %and, 0
+  %sel = select i1 %cmp, i32 0, i32 -1
+  store i32 %sel, i32 addrspace(1)* %out
+  ret void
+}