[RISCV] Avoid unnecessary XOR for seteq/setne 0

[jrtc27]

Ping?

[asb]

Great catch, thanks. I know there's good test coverage for by virtue of it being a common pattern, but could you please add a more targeted unit test to e.g. test/CodeGen/RISCV/i32-icmp.ll? Otherwise, looks good to me.

[jrtc27]

Added explicit test cases to test/CodeGen/RISCV/i32-icmp.ll.

[asb]

Looks good to me, thanks!

lib/Target/RISCV/RISCVInstrInfo.td

 
 def : PatGprGpr<setlt, SLT>;
 def : PatGprSimm12<setlt, SLTI>;
 def : PatGprGpr<setult, SLTU>;
 def : PatGprSimm12<setult, SLTIU>;
 
 // Define pattern expansions for setcc operations that aren't directly
 // handled by a RISC-V instruction.
+def : Pat<(seteq GPR:$rs1, 0), (SLTIU GPR:$rs1, 1)>;
 def : Pat<(seteq GPR:$rs1, GPR:$rs2), (SLTIU (XOR GPR:$rs1, GPR:$rs2), 1)>;
+def : Pat<(setne GPR:$rs1, 0), (SLTU X0, GPR:$rs1)>;
 def : Pat<(setne GPR:$rs1, GPR:$rs2), (SLTU X0, (XOR GPR:$rs1, GPR:$rs2))>;
 def : Pat<(setugt GPR:$rs1, GPR:$rs2), (SLTU GPR:$rs2, GPR:$rs1)>;
 def : Pat<(setuge GPR:$rs1, GPR:$rs2), (XORI (SLTU GPR:$rs1, GPR:$rs2), 1)>;
 def : Pat<(setule GPR:$rs1, GPR:$rs2), (XORI (SLTU GPR:$rs2, GPR:$rs1), 1)>;
 def : Pat<(setgt GPR:$rs1, GPR:$rs2), (SLT GPR:$rs2, GPR:$rs1)>;
 def : Pat<(setge GPR:$rs1, GPR:$rs2), (XORI (SLT GPR:$rs1, GPR:$rs2), 1)>;
 def : Pat<(setle GPR:$rs1, GPR:$rs2), (XORI (SLT GPR:$rs2, GPR:$rs1), 1)>;
 

test/CodeGen/RISCV/calling-conv.ll

 ; RV32I-FPELIM-NEXT:    lw a3, 8(a1)
 ; RV32I-FPELIM-NEXT:    lw a4, 8(a0)
 ; RV32I-FPELIM-NEXT:    xor a3, a4, a3
 ; RV32I-FPELIM-NEXT:    lw a1, 0(a1)
 ; RV32I-FPELIM-NEXT:    lw a0, 0(a0)
 ; RV32I-FPELIM-NEXT:    xor a0, a0, a1
 ; RV32I-FPELIM-NEXT:    or a0, a0, a3
 ; RV32I-FPELIM-NEXT:    or a0, a0, a2
-; RV32I-FPELIM-NEXT:    xor a0, a0, zero
 ; RV32I-FPELIM-NEXT:    seqz a0, a0
 ; RV32I-FPELIM-NEXT:    ret
 ;
 ; RV32I-WITHFP-LABEL: callee_large_scalars:
 ; RV32I-WITHFP:       # %bb.0:
 ; RV32I-WITHFP-NEXT:    addi sp, sp, -16
 ; RV32I-WITHFP-NEXT:    sw ra, 12(sp)
 ; RV32I-WITHFP-NEXT:    sw s0, 8(sp)
 ; RV32I-WITHFP-NEXT:    addi s0, sp, 16
 ; RV32I-WITHFP-NEXT:    lw a2, 12(a1)
 ; RV32I-WITHFP-NEXT:    lw a3, 12(a0)
 ; RV32I-WITHFP-NEXT:    xor a2, a3, a2
 ; RV32I-WITHFP-NEXT:    lw a3, 4(a1)
 ; RV32I-WITHFP-NEXT:    lw a4, 4(a0)
 ; RV32I-WITHFP-NEXT:    xor a3, a4, a3
 ; RV32I-WITHFP-NEXT:    or a2, a3, a2
 ; RV32I-WITHFP-NEXT:    lw a3, 8(a1)
 ; RV32I-WITHFP-NEXT:    lw a4, 8(a0)
 ; RV32I-WITHFP-NEXT:    xor a3, a4, a3
 ; RV32I-WITHFP-NEXT:    lw a1, 0(a1)
 ; RV32I-WITHFP-NEXT:    lw a0, 0(a0)
 ; RV32I-WITHFP-NEXT:    xor a0, a0, a1
 ; RV32I-WITHFP-NEXT:    or a0, a0, a3
 ; RV32I-WITHFP-NEXT:    or a0, a0, a2
-; RV32I-WITHFP-NEXT:    xor a0, a0, zero
 ; RV32I-WITHFP-NEXT:    seqz a0, a0
 ; RV32I-WITHFP-NEXT:    lw s0, 8(sp)
 ; RV32I-WITHFP-NEXT:    lw ra, 12(sp)
 ; RV32I-WITHFP-NEXT:    addi sp, sp, 16
 ; RV32I-WITHFP-NEXT:    ret
   %b_bitcast = bitcast fp128 %b to i128
   %1 = icmp eq i128 %a, %b_bitcast
   %2 = zext i1 %1 to i32

 ; RV32I-FPELIM-NEXT:    lw a2, 8(a0)
 ; RV32I-FPELIM-NEXT:    lw a3, 8(a7)
 ; RV32I-FPELIM-NEXT:    xor a2, a3, a2
 ; RV32I-FPELIM-NEXT:    lw a0, 0(a0)
 ; RV32I-FPELIM-NEXT:    lw a3, 0(a7)
 ; RV32I-FPELIM-NEXT:    xor a0, a3, a0
 ; RV32I-FPELIM-NEXT:    or a0, a0, a2
 ; RV32I-FPELIM-NEXT:    or a0, a0, a1
-; RV32I-FPELIM-NEXT:    xor a0, a0, zero
 ; RV32I-FPELIM-NEXT:    seqz a0, a0
 ; RV32I-FPELIM-NEXT:    ret
 ;
 ; RV32I-WITHFP-LABEL: callee_large_scalars_exhausted_regs:
 ; RV32I-WITHFP:       # %bb.0:
 ; RV32I-WITHFP-NEXT:    addi sp, sp, -16
 ; RV32I-WITHFP-NEXT:    sw ra, 12(sp)
 ; RV32I-WITHFP-NEXT:    sw s0, 8(sp)

 ; RV32I-WITHFP-NEXT:    lw a2, 8(a0)
 ; RV32I-WITHFP-NEXT:    lw a3, 8(a7)
 ; RV32I-WITHFP-NEXT:    xor a2, a3, a2
 ; RV32I-WITHFP-NEXT:    lw a0, 0(a0)
 ; RV32I-WITHFP-NEXT:    lw a3, 0(a7)
 ; RV32I-WITHFP-NEXT:    xor a0, a3, a0
 ; RV32I-WITHFP-NEXT:    or a0, a0, a2
 ; RV32I-WITHFP-NEXT:    or a0, a0, a1
-; RV32I-WITHFP-NEXT:    xor a0, a0, zero
 ; RV32I-WITHFP-NEXT:    seqz a0, a0
 ; RV32I-WITHFP-NEXT:    lw s0, 8(sp)
 ; RV32I-WITHFP-NEXT:    lw ra, 12(sp)
 ; RV32I-WITHFP-NEXT:    addi sp, sp, 16
 ; RV32I-WITHFP-NEXT:    ret
   %j_bitcast = bitcast fp128 %j to i128
   %1 = icmp eq i128 %h, %j_bitcast
   %2 = zext i1 %1 to i32

 
 define i32 @callee_many_scalars(i8 %a, i16 %b, i32 %c, i64 %d, i32 %e, i32 %f, i64 %g, i32 %h) nounwind {
 ; RV32I-FPELIM-LABEL: callee_many_scalars:
 ; RV32I-FPELIM:       # %bb.0:
 ; RV32I-FPELIM-NEXT:    lw t0, 0(sp)
 ; RV32I-FPELIM-NEXT:    xor a4, a4, t0
 ; RV32I-FPELIM-NEXT:    xor a3, a3, a7
 ; RV32I-FPELIM-NEXT:    or a3, a3, a4
-; RV32I-FPELIM-NEXT:    xor a3, a3, zero
 ; RV32I-FPELIM-NEXT:    lui a4, 16
 ; RV32I-FPELIM-NEXT:    addi a4, a4, -1
 ; RV32I-FPELIM-NEXT:    and a1, a1, a4
 ; RV32I-FPELIM-NEXT:    andi a0, a0, 255
 ; RV32I-FPELIM-NEXT:    add a0, a0, a1
 ; RV32I-FPELIM-NEXT:    add a0, a0, a2
 ; RV32I-FPELIM-NEXT:    seqz a1, a3
 ; RV32I-FPELIM-NEXT:    add a0, a1, a0
 ; RV32I-FPELIM-NEXT:    add a0, a0, a5
 ; RV32I-FPELIM-NEXT:    add a0, a0, a6
 ; RV32I-FPELIM-NEXT:    lw a1, 4(sp)
 ; RV32I-FPELIM-NEXT:    add a0, a0, a1
 ; RV32I-FPELIM-NEXT:    ret
 ;
 ; RV32I-WITHFP-LABEL: callee_many_scalars:
 ; RV32I-WITHFP:       # %bb.0:
 ; RV32I-WITHFP-NEXT:    addi sp, sp, -16
 ; RV32I-WITHFP-NEXT:    sw ra, 12(sp)
 ; RV32I-WITHFP-NEXT:    sw s0, 8(sp)
 ; RV32I-WITHFP-NEXT:    addi s0, sp, 16
 ; RV32I-WITHFP-NEXT:    lw t0, 0(s0)
 ; RV32I-WITHFP-NEXT:    xor a4, a4, t0
 ; RV32I-WITHFP-NEXT:    xor a3, a3, a7
 ; RV32I-WITHFP-NEXT:    or a3, a3, a4
-; RV32I-WITHFP-NEXT:    xor a3, a3, zero
 ; RV32I-WITHFP-NEXT:    lui a4, 16
 ; RV32I-WITHFP-NEXT:    addi a4, a4, -1
 ; RV32I-WITHFP-NEXT:    and a1, a1, a4
 ; RV32I-WITHFP-NEXT:    andi a0, a0, 255
 ; RV32I-WITHFP-NEXT:    add a0, a0, a1
 ; RV32I-WITHFP-NEXT:    add a0, a0, a2
 ; RV32I-WITHFP-NEXT:    seqz a1, a3
 ; RV32I-WITHFP-NEXT:    add a0, a1, a0

 ; RV32I-FPELIM-NEXT:    lui a0, 56
 ; RV32I-FPELIM-NEXT:    addi s1, a0, 580
 ; RV32I-FPELIM-NEXT:    call callee_small_scalar_ret
 ; RV32I-FPELIM-NEXT:    xor a1, a1, s1
 ; RV32I-FPELIM-NEXT:    lui a2, 200614
 ; RV32I-FPELIM-NEXT:    addi a2, a2, 647
 ; RV32I-FPELIM-NEXT:    xor a0, a0, a2
 ; RV32I-FPELIM-NEXT:    or a0, a0, a1
-; RV32I-FPELIM-NEXT:    xor a0, a0, zero
 ; RV32I-FPELIM-NEXT:    seqz a0, a0
 ; RV32I-FPELIM-NEXT:    lw s1, 8(sp)
 ; RV32I-FPELIM-NEXT:    lw ra, 12(sp)
 ; RV32I-FPELIM-NEXT:    addi sp, sp, 16
 ; RV32I-FPELIM-NEXT:    ret
 ;
 ; RV32I-WITHFP-LABEL: caller_small_scalar_ret:
 ; RV32I-WITHFP:       # %bb.0:
 ; RV32I-WITHFP-NEXT:    addi sp, sp, -16
 ; RV32I-WITHFP-NEXT:    sw ra, 12(sp)
 ; RV32I-WITHFP-NEXT:    sw s0, 8(sp)
 ; RV32I-WITHFP-NEXT:    sw s1, 4(sp)
 ; RV32I-WITHFP-NEXT:    addi s0, sp, 16
 ; RV32I-WITHFP-NEXT:    lui a0, 56
 ; RV32I-WITHFP-NEXT:    addi s1, a0, 580
 ; RV32I-WITHFP-NEXT:    call callee_small_scalar_ret
 ; RV32I-WITHFP-NEXT:    xor a1, a1, s1
 ; RV32I-WITHFP-NEXT:    lui a2, 200614
 ; RV32I-WITHFP-NEXT:    addi a2, a2, 647
 ; RV32I-WITHFP-NEXT:    xor a0, a0, a2
 ; RV32I-WITHFP-NEXT:    or a0, a0, a1
-; RV32I-WITHFP-NEXT:    xor a0, a0, zero
 ; RV32I-WITHFP-NEXT:    seqz a0, a0
 ; RV32I-WITHFP-NEXT:    lw s1, 4(sp)
 ; RV32I-WITHFP-NEXT:    lw s0, 8(sp)
 ; RV32I-WITHFP-NEXT:    lw ra, 12(sp)
 ; RV32I-WITHFP-NEXT:    addi sp, sp, 16
 ; RV32I-WITHFP-NEXT:    ret
   %1 = call i64 @callee_small_scalar_ret()
   %2 = icmp eq i64 987654321234567, %1

test/CodeGen/RISCV/fp128.ll

 ; RV32I-NEXT:    sw a1, 36(sp)
 ; RV32I-NEXT:    lw a1, 8(a0)
 ; RV32I-NEXT:    sw a1, 32(sp)
 ; RV32I-NEXT:    lw a0, 4(a0)
 ; RV32I-NEXT:    sw a0, 28(sp)
 ; RV32I-NEXT:    addi a0, sp, 24
 ; RV32I-NEXT:    addi a1, sp, 8
 ; RV32I-NEXT:    call __netf2
-; RV32I-NEXT:    xor a0, a0, zero
 ; RV32I-NEXT:    snez a0, a0
 ; RV32I-NEXT:    lw ra, 44(sp)
 ; RV32I-NEXT:    addi sp, sp, 48
 ; RV32I-NEXT:    ret
   %1 = load fp128, fp128* @x, align 16
   %2 = load fp128, fp128* @y, align 16
   %cmp = fcmp une fp128 %1, %2
   %3 = zext i1 %cmp to i32

test/CodeGen/RISCV/get-setcc-result-type.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV32I %s
 
 define void @getSetCCResultType(<4 x i32>* %p, <4 x i32>* %q) {
 ; RV32I-LABEL: getSetCCResultType:
 ; RV32I:       # %bb.0: # %entry
 ; RV32I-NEXT:    lw a1, 12(a0)
-; RV32I-NEXT:    xor a1, a1, zero
 ; RV32I-NEXT:    seqz a1, a1
 ; RV32I-NEXT:    neg a1, a1
 ; RV32I-NEXT:    sw a1, 12(a0)
 ; RV32I-NEXT:    lw a1, 8(a0)
-; RV32I-NEXT:    xor a1, a1, zero
 ; RV32I-NEXT:    seqz a1, a1
 ; RV32I-NEXT:    neg a1, a1
 ; RV32I-NEXT:    sw a1, 8(a0)
 ; RV32I-NEXT:    lw a1, 4(a0)
-; RV32I-NEXT:    xor a1, a1, zero
 ; RV32I-NEXT:    seqz a1, a1
 ; RV32I-NEXT:    neg a1, a1
 ; RV32I-NEXT:    sw a1, 4(a0)
 ; RV32I-NEXT:    lw a1, 0(a0)
-; RV32I-NEXT:    xor a1, a1, zero
 ; RV32I-NEXT:    seqz a1, a1
 ; RV32I-NEXT:    neg a1, a1
 ; RV32I-NEXT:    sw a1, 0(a0)
 ; RV32I-NEXT:    ret
 entry:
   %0 = load <4 x i32>, <4 x i32>* %p, align 16
   %cmp = icmp eq <4 x i32> %0, zeroinitializer
   %sext = sext <4 x i1> %cmp to <4 x i32>
   store <4 x i32> %sext, <4 x i32>* %p, align 16
   ret void
 }

test/CodeGen/RISCV/umulo-128-legalisation-lowering.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=riscv32 -mattr=+m | FileCheck %s --check-prefixes=RISCV32
 
 define { i128, i8 } @muloti_test(i128 %l, i128 %r) unnamed_addr #0 {
 ; RISCV32-LABEL: muloti_test:
 ; RISCV32:       # %bb.0: # %start
-; RISCV32-NEXT:    addi sp, sp, -80
-; RISCV32-NEXT:    sw ra, 76(sp)
-; RISCV32-NEXT:    sw s1, 72(sp)
-; RISCV32-NEXT:    sw s2, 68(sp)
-; RISCV32-NEXT:    sw s3, 64(sp)
-; RISCV32-NEXT:    sw s4, 60(sp)
-; RISCV32-NEXT:    sw s5, 56(sp)
-; RISCV32-NEXT:    sw s6, 52(sp)
-; RISCV32-NEXT:    sw s7, 48(sp)
+; RISCV32-NEXT:    addi sp, sp, -96
+; RISCV32-NEXT:    sw ra, 92(sp)
+; RISCV32-NEXT:    sw s1, 88(sp)
+; RISCV32-NEXT:    sw s2, 84(sp)
+; RISCV32-NEXT:    sw s3, 80(sp)
+; RISCV32-NEXT:    sw s4, 76(sp)
+; RISCV32-NEXT:    sw s5, 72(sp)
+; RISCV32-NEXT:    sw s6, 68(sp)
+; RISCV32-NEXT:    sw s7, 64(sp)
+; RISCV32-NEXT:    sw s8, 60(sp)
 ; RISCV32-NEXT:    mv s3, a2
 ; RISCV32-NEXT:    mv s1, a1
 ; RISCV32-NEXT:    mv s2, a0
-; RISCV32-NEXT:    sw zero, 12(sp)
-; RISCV32-NEXT:    sw zero, 8(sp)
-; RISCV32-NEXT:    sw zero, 28(sp)
-; RISCV32-NEXT:    sw zero, 24(sp)
+; RISCV32-NEXT:    mv s4, zero
+; RISCV32-NEXT:    sw zero, 20(sp)
+; RISCV32-NEXT:    sw zero, 16(sp)
+; RISCV32-NEXT:    sw zero, 36(sp)
+; RISCV32-NEXT:    sw zero, 32(sp)
 ; RISCV32-NEXT:    lw s5, 4(a2)
-; RISCV32-NEXT:    sw s5, 4(sp)
-; RISCV32-NEXT:    lw s6, 0(a2)
-; RISCV32-NEXT:    sw s6, 0(sp)
-; RISCV32-NEXT:    lw s4, 4(a1)
-; RISCV32-NEXT:    sw s4, 20(sp)
-; RISCV32-NEXT:    lw s7, 0(a1)
-; RISCV32-NEXT:    sw s7, 16(sp)
-; RISCV32-NEXT:    addi a0, sp, 32
-; RISCV32-NEXT:    addi a1, sp, 16
-; RISCV32-NEXT:    mv a2, sp
+; RISCV32-NEXT:    sw s5, 12(sp)
+; RISCV32-NEXT:    lw s7, 0(a2)
+; RISCV32-NEXT:    sw s7, 8(sp)
+; RISCV32-NEXT:    lw s6, 4(a1)
+; RISCV32-NEXT:    sw s6, 28(sp)
+; RISCV32-NEXT:    lw s8, 0(a1)
+; RISCV32-NEXT:    sw s8, 24(sp)
+; RISCV32-NEXT:    addi a0, sp, 40
+; RISCV32-NEXT:    addi a1, sp, 24
+; RISCV32-NEXT:    addi a2, sp, 8
 ; RISCV32-NEXT:    call __multi3
-; RISCV32-NEXT:    lw t1, 12(s1)
+; RISCV32-NEXT:    lw t2, 12(s1)
 ; RISCV32-NEXT:    lw a1, 8(s1)
 ; RISCV32-NEXT:    mul a0, s5, a1
-; RISCV32-NEXT:    mul a2, t1, s6
+; RISCV32-NEXT:    mul a2, t2, s7
 ; RISCV32-NEXT:    add a0, a2, a0
-; RISCV32-NEXT:    lw t5, 12(s3)
+; RISCV32-NEXT:    lw t3, 12(s3)
 ; RISCV32-NEXT:    lw a3, 8(s3)
-; RISCV32-NEXT:    mul a2, s4, a3
-; RISCV32-NEXT:    mul a4, t5, s7
+; RISCV32-NEXT:    mul a2, s6, a3
+; RISCV32-NEXT:    mul a4, t3, s8
 ; RISCV32-NEXT:    add a2, a4, a2
-; RISCV32-NEXT:    mul a4, a3, s7
-; RISCV32-NEXT:    mul a5, a1, s6
-; RISCV32-NEXT:    add s1, a5, a4
-; RISCV32-NEXT:    sltu a4, s1, a5
-; RISCV32-NEXT:    mulhu a6, a3, s7
+; RISCV32-NEXT:    mul a4, a3, s8
+; RISCV32-NEXT:    mul a5, a1, s7
+; RISCV32-NEXT:    add a4, a5, a4
+; RISCV32-NEXT:    sltu a5, a4, a5
+; RISCV32-NEXT:    mulhu a6, a3, s8
 ; RISCV32-NEXT:    add a7, a6, a2
-; RISCV32-NEXT:    mulhu t2, a1, s6
-; RISCV32-NEXT:    add t4, t2, a0
-; RISCV32-NEXT:    add a0, t4, a7
-; RISCV32-NEXT:    add a0, a0, a4
-; RISCV32-NEXT:    xor a2, s5, zero
-; RISCV32-NEXT:    snez a2, a2
-; RISCV32-NEXT:    xor a4, t1, zero
-; RISCV32-NEXT:    snez a4, a4
-; RISCV32-NEXT:    and a2, a4, a2
-; RISCV32-NEXT:    xor a4, s4, zero
-; RISCV32-NEXT:    snez a4, a4
-; RISCV32-NEXT:    xor a5, t5, zero
-; RISCV32-NEXT:    snez a5, a5
-; RISCV32-NEXT:    and a4, a5, a4
-; RISCV32-NEXT:    mulhu a5, t5, s7
-; RISCV32-NEXT:    xor a5, a5, zero
-; RISCV32-NEXT:    snez a5, a5
-; RISCV32-NEXT:    or t0, a4, a5
-; RISCV32-NEXT:    mulhu a4, t1, s6
-; RISCV32-NEXT:    xor a4, a4, zero
-; RISCV32-NEXT:    snez a4, a4
-; RISCV32-NEXT:    or t3, a2, a4
-; RISCV32-NEXT:    lw a4, 44(sp)
-; RISCV32-NEXT:    add a5, a4, a0
-; RISCV32-NEXT:    lw a2, 40(sp)
-; RISCV32-NEXT:    add a0, a2, s1
-; RISCV32-NEXT:    sltu t6, a0, a2
-; RISCV32-NEXT:    add s1, a5, t6
-; RISCV32-NEXT:    beq s1, a4, .LBB0_2
+; RISCV32-NEXT:    mulhu t0, a1, s7
+; RISCV32-NEXT:    add t1, t0, a0
+; RISCV32-NEXT:    add a0, t1, a7
+; RISCV32-NEXT:    add a2, a0, a5
+; RISCV32-NEXT:    lw a0, 52(sp)
+; RISCV32-NEXT:    add a5, a0, a2
+; RISCV32-NEXT:    lw a2, 48(sp)
+; RISCV32-NEXT:    add t4, a2, a4
+; RISCV32-NEXT:    sltu s1, t4, a2
+; RISCV32-NEXT:    add a4, a5, s1
+; RISCV32-NEXT:    beq a4, a0, .LBB0_2
 ; RISCV32-NEXT:  # %bb.1: # %start
-; RISCV32-NEXT:    sltu t6, s1, a4
+; RISCV32-NEXT:    sltu s1, a4, a0
 ; RISCV32-NEXT:  .LBB0_2: # %start
-; RISCV32-NEXT:    xor a4, s1, a4
-; RISCV32-NEXT:    xor a2, a0, a2
-; RISCV32-NEXT:    or a2, a2, a4
-; RISCV32-NEXT:    sltu t2, t4, t2
-; RISCV32-NEXT:    mulhu a4, s5, a1
-; RISCV32-NEXT:    xor a4, a4, zero
-; RISCV32-NEXT:    snez a4, a4
-; RISCV32-NEXT:    or t3, t3, a4
-; RISCV32-NEXT:    sltu a6, a7, a6
-; RISCV32-NEXT:    mulhu a4, s4, a3
-; RISCV32-NEXT:    xor a4, a4, zero
-; RISCV32-NEXT:    snez a4, a4
-; RISCV32-NEXT:    or a4, t0, a4
-; RISCV32-NEXT:    lw a5, 36(sp)
-; RISCV32-NEXT:    sw a5, 4(s2)
-; RISCV32-NEXT:    lw a5, 32(sp)
-; RISCV32-NEXT:    sw a5, 0(s2)
-; RISCV32-NEXT:    sw a0, 8(s2)
-; RISCV32-NEXT:    sw s1, 12(s2)
-; RISCV32-NEXT:    mv a0, zero
-; RISCV32-NEXT:    beqz a2, .LBB0_4
+; RISCV32-NEXT:    xor a0, a4, a0
+; RISCV32-NEXT:    xor a2, t4, a2
+; RISCV32-NEXT:    or a0, a2, a0
+; RISCV32-NEXT:    beq a0, s4, .LBB0_4
 ; RISCV32-NEXT:  # %bb.3: # %start
-; RISCV32-NEXT:    mv a0, t6
+; RISCV32-NEXT:    mv s4, s1
 ; RISCV32-NEXT:  .LBB0_4: # %start
-; RISCV32-NEXT:    or a2, a4, a6
-; RISCV32-NEXT:    or a4, t3, t2
-; RISCV32-NEXT:    or a3, a3, t5
-; RISCV32-NEXT:    or a1, a1, t1
-; RISCV32-NEXT:    xor a1, a1, zero
-; RISCV32-NEXT:    xor a3, a3, zero
+; RISCV32-NEXT:    snez a0, s5
+; RISCV32-NEXT:    snez a2, t2
+; RISCV32-NEXT:    and a0, a2, a0
+; RISCV32-NEXT:    snez a2, s6
+; RISCV32-NEXT:    snez a5, t3
+; RISCV32-NEXT:    and a2, a5, a2
+; RISCV32-NEXT:    mulhu a5, t3, s8
+; RISCV32-NEXT:    snez a5, a5
+; RISCV32-NEXT:    or a2, a2, a5
+; RISCV32-NEXT:    mulhu a5, t2, s7
+; RISCV32-NEXT:    snez a5, a5
+; RISCV32-NEXT:    or a0, a0, a5
+; RISCV32-NEXT:    sltu t0, t1, t0
+; RISCV32-NEXT:    mulhu s1, s5, a1
+; RISCV32-NEXT:    snez s1, s1
+; RISCV32-NEXT:    or a0, a0, s1
+; RISCV32-NEXT:    sltu s1, a7, a6
+; RISCV32-NEXT:    mulhu a5, s6, a3
+; RISCV32-NEXT:    snez a5, a5
+; RISCV32-NEXT:    or a2, a2, a5
+; RISCV32-NEXT:    lw a5, 44(sp)
+; RISCV32-NEXT:    sw a5, 4(s2)
+; RISCV32-NEXT:    lw a5, 40(sp)
+; RISCV32-NEXT:    sw a5, 0(s2)
+; RISCV32-NEXT:    sw t4, 8(s2)
+; RISCV32-NEXT:    sw a4, 12(s2)
+; RISCV32-NEXT:    or a2, a2, s1
+; RISCV32-NEXT:    or a0, a0, t0
+; RISCV32-NEXT:    or a1, a1, t2
+; RISCV32-NEXT:    or a3, a3, t3
 ; RISCV32-NEXT:    snez a3, a3
 ; RISCV32-NEXT:    snez a1, a1
 ; RISCV32-NEXT:    and a1, a1, a3
-; RISCV32-NEXT:    or a1, a1, a4
-; RISCV32-NEXT:    or a1, a1, a2
 ; RISCV32-NEXT:    or a0, a1, a0
+; RISCV32-NEXT:    or a0, a0, a2
+; RISCV32-NEXT:    or a0, a0, s4
 ; RISCV32-NEXT:    andi a0, a0, 1
 ; RISCV32-NEXT:    sb a0, 16(s2)
-; RISCV32-NEXT:    lw s7, 48(sp)
-; RISCV32-NEXT:    lw s6, 52(sp)
-; RISCV32-NEXT:    lw s5, 56(sp)
-; RISCV32-NEXT:    lw s4, 60(sp)
-; RISCV32-NEXT:    lw s3, 64(sp)
-; RISCV32-NEXT:    lw s2, 68(sp)
-; RISCV32-NEXT:    lw s1, 72(sp)
-; RISCV32-NEXT:    lw ra, 76(sp)
-; RISCV32-NEXT:    addi sp, sp, 80
+; RISCV32-NEXT:    lw s8, 60(sp)
+; RISCV32-NEXT:    lw s7, 64(sp)
+; RISCV32-NEXT:    lw s6, 68(sp)
+; RISCV32-NEXT:    lw s5, 72(sp)
+; RISCV32-NEXT:    lw s4, 76(sp)
+; RISCV32-NEXT:    lw s3, 80(sp)
+; RISCV32-NEXT:    lw s2, 84(sp)
+; RISCV32-NEXT:    lw s1, 88(sp)
+; RISCV32-NEXT:    lw ra, 92(sp)
+; RISCV32-NEXT:    addi sp, sp, 96
 ; RISCV32-NEXT:    ret
 start:
   %0 = tail call { i128, i1 } @llvm.umul.with.overflow.i128(i128 %l, i128 %r) #2
   %1 = extractvalue { i128, i1 } %0, 0
   %2 = extractvalue { i128, i1 } %0, 1
   %3 = zext i1 %2 to i8
   %4 = insertvalue { i128, i8 } undef, i128 %1, 0
   %5 = insertvalue { i128, i8 } %4, i8 %3, 1