[OpenMP][NVPTX] Enable default scheduling for parallel for in non-SPMD cases.

[gtbercea]

Summary

This patch enables the choosing of the default schedule for parallel for loops even in non-SPMD cases.

[ABataev]

lib/CodeGen/CGOpenMPRuntimeNVPTX.h

350 ↗

(On Diff #170216)

Why do you need to change the type of the parameter?

[gtbercea]

Refactor.

[ABataev]

What about tests?

[gtbercea]

Add test.

[ABataev]

test/OpenMP/nvptx_parallel_for_codegen.cpp

44 ↗

(On Diff #171310)

Do not use names of the IR vars, use regular expressions.

[gtbercea]

Add test.

[gtbercea]

ping

[ABataev]

LG

cfe/trunk/lib/CodeGen/CGOpenMPRuntimeNVPTX.cpp

void CGOpenMPRuntimeNVPTX::getDefaultDistScheduleAndChunk(
     CodeGenFunction &CGF, const OMPLoopDirective &S,
     OpenMPDistScheduleClauseKind &ScheduleKind,
     llvm::Value *&Chunk) const {
   if (getExecutionMode() == CGOpenMPRuntimeNVPTX::EM_SPMD) {
     ScheduleKind = OMPC_DIST_SCHEDULE_static;
     Chunk = CGF.EmitScalarConversion(getNVPTXNumThreads(CGF),
         CGF.getContext().getIntTypeForBitwidth(32, /*Signed=*/0),
         S.getIterationVariable()->getType(), S.getBeginLoc());
+    return;
   }
+  CGOpenMPRuntime::getDefaultDistScheduleAndChunk(
+      CGF, S, ScheduleKind, Chunk);
 }
 
 void CGOpenMPRuntimeNVPTX::getDefaultScheduleAndChunk(
     CodeGenFunction &CGF, const OMPLoopDirective &S,
     OpenMPScheduleClauseKind &ScheduleKind,
     llvm::Value *&Chunk) const {
-  if (getExecutionMode() == CGOpenMPRuntimeNVPTX::EM_SPMD) {
-    ScheduleKind = OMPC_SCHEDULE_static;
-    Chunk = CGF.Builder.getIntN(CGF.getContext().getTypeSize(
-        S.getIterationVariable()->getType()), 1);
-  }
-}

cfe/trunk/test/OpenMP/nvptx_parallel_for_codegen.cpp

 // CHECK: alloca
 // CHECK: alloca
 // CHECK: alloca
 // CHECK: alloca
 // CHECK: [[OMP_IV:%.*]] = alloca i32
 // CHECK: store i32 0, {{.*}} [[OMP_LB:%.+]],
 // CHECK: store i32 9, {{.*}} [[OMP_UB:%.+]],
 // CHECK: store i32 1, {{.*}} [[OMP_ST:%.+]],
-// CHECK: call void @__kmpc_for_static_init_4({{.*}} i32 34, {{.*}} [[OMP_LB]], {{.*}} [[OMP_UB]], {{.*}} [[OMP_ST]], i32 1, i32 1)
+// CHECK: call void @__kmpc_for_static_init_4({{.*}} i32 33, {{.*}} [[OMP_LB]], {{.*}} [[OMP_UB]], {{.*}} [[OMP_ST]], i32 1, i32 1)
+// CHECK: br label %[[OMP_DISPATCH_COND:.+]]
+
+// CHECK: [[OMP_DISPATCH_COND]]
 // CHECK: [[OMP_UB_1:%.+]] = load {{.*}} [[OMP_UB]]
 // CHECK: [[COMP_1:%.+]] = icmp sgt {{.*}} [[OMP_UB_1]]
 // CHECK: br i1 [[COMP_1]], label %[[COND_TRUE:.+]], label %[[COND_FALSE:.+]]
 
 // CHECK: [[COND_TRUE]]
 // CHECK: br label %[[COND_END:.+]]
 
 // CHECK: [[COND_FALSE]]
 // CHECK: [[OMP_UB_2:%.+]] = load {{.*}}* [[OMP_UB]]
 // CHECK: br label %[[COND_END]]
 
 // CHECK: [[COND_END]]
 // CHECK: [[COND_RES:%.+]] = phi i32 [ 9, %[[COND_TRUE]] ], [ [[OMP_UB_2]], %[[COND_FALSE]] ]
 // CHECK: store i32 [[COND_RES]], i32* [[OMP_UB]]
 // CHECK: [[OMP_LB_1:%.+]] = load i32, i32* [[OMP_LB]]
 // CHECK: store i32 [[OMP_LB_1]], i32* [[OMP_IV]]
+// CHECK: [[OMP_IV_1:%.+]] = load i32, i32* [[OMP_IV]]
+// CHECK: [[OMP_UB_3:%.+]] = load i32, i32* [[OMP_UB]]
+// CHECK: [[COMP_2:%.+]] = icmp sle i32 [[OMP_IV_1]], [[OMP_UB_3]]
+// CHECK: br i1 [[COMP_2]], label %[[DISPATCH_BODY:.+]], label %[[DISPATCH_END:.+]]
+
+// CHECK: [[DISPATCH_BODY]]
 // CHECK: br label %[[OMP_INNER_FOR_COND:.+]]
 
 // CHECK: [[OMP_INNER_FOR_COND]]
 // CHECK: [[OMP_IV_2:%.+]] = load i32, i32* [[OMP_IV]]
 // CHECK: [[OMP_UB_4:%.+]] = load i32, i32* [[OMP_UB]]
 // CHECK: [[COMP_3:%.+]] = icmp sle i32 [[OMP_IV_2]], [[OMP_UB_4]]
 // CHECK: br i1 [[COMP_3]], label %[[OMP_INNER_FOR_BODY:.+]], label %[[OMP_INNER_FOR_END:.+]]
 
 // CHECK: [[OMP_INNER_FOR_BODY]]
 // CHECK: br label %[[OMP_BODY_CONTINUE:.+]]
 
 // CHECK: [[OMP_BODY_CONTINUE]]
 // CHECK: br label %[[OMP_INNER_FOR_INC:.+]]
 
 // CHECK: [[OMP_INNER_FOR_INC]]
 // CHECK: [[OMP_IV_3:%.+]] = load i32, i32* [[OMP_IV]]
 // CHECK: [[ADD_1:%.+]] = add nsw i32 [[OMP_IV_3]], 1
 // CHECK: store i32 [[ADD_1]], i32* [[OMP_IV]]
 // CHECK: br label %[[OMP_INNER_FOR_COND]]
 
-// CHECK: [[OMP_INNER_FOR_END]]
+// CHECK: [[OMP_INNER_FOR_COND]]
+// CHECK: br label %[[OMP_DISPATCH_INC:.+]]
+
+// CHECK: [[OMP_DISPATCH_INC]]
+// CHECK: [[OMP_LB_2:%.+]] = load i32, i32* [[OMP_LB]]
+// CHECK: [[OMP_ST_1:%.+]] = load i32, i32* [[OMP_ST]]
+// CHECK: [[ADD_2:%.+]] = add nsw i32 [[OMP_LB_2]], [[OMP_ST_1]]
+// CHECK: store i32 [[ADD_2]], i32* [[OMP_LB]]
+// CHECK: [[OMP_UB_5:%.+]] = load i32, i32* [[OMP_UB]]
+// CHECK: [[OMP_ST_2:%.+]] = load i32, i32* [[OMP_ST]]
+// CHECK: [[ADD_3:%.+]] = add nsw i32 [[OMP_UB_5]], [[OMP_ST_2]]
+// CHECK: store i32 [[ADD_3]], i32* [[OMP_UB]]
+
+// CHECK: [[DISPATCH_END]]
 // CHECK: call void @__kmpc_for_static_fini(
 // CHECK: ret void
 
 #endif