[PowerPC] Exploit power9 new instruction setb

[jedilyn]

Summary

; Function Attrs: norecurse nounwind readnone
define i64 @_Z4setbxx(i64, i64) local_unnamed_addr #0 {
  %3 = icmp slt i64 %0, %1
  %4 = icmp ne i64 %0, %1
  %5 = zext i1 %4 to i64
  %6 = select i1 %3, i64 -1, i64 %5
  ret i64 %6
}

Current seq: (11 cycs)

xor 6, 3, 4
li 5, -1
addic 7, 6, -1
cmpd    3, 4
subfe 6, 7, 6
isel 3, 5, 6, 0
blr

Expected seq: (8 cycs)

cmpd    3, 4
setb 3, 0
blr

[nemanjai]

Since the logic in the switch statement is difficult to follow, I ended up having to test this patch with a script that tries all combinations of comparisons, results and operand order in order to convince myself that it doesn't emit a setb when it is not valid to do so. Everything checks out there, but I don't really have an easy way of testing whether any opportunities are missed.
I am really hoping that you can simplify the logic in that switch to make it easier to follow.

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

85 ↗

(On Diff #169664)

Perhaps Number of compares lowered to setb.

4136 ↗

(On Diff #169664)

Please explain why we will select an isel if this condition is satisfied.

4157 ↗

(On Diff #169664)

It is not clear to me why we can just swap these without changing the condition code.

4197 ↗

(On Diff #169664)

I think expressions such as this are extremely difficult to follow. Perhaps the expressions for computing the Boolean output parameters can be simplified using the fact that unsigned comparisons have the property CC & 0x8 != 0, etc.?

llvm/lib/Target/PowerPC/PPCInstr64Bit.td

776 ↗

(On Diff #169664)

As a matter of custom, we put these into PPCInstrInfo.td.

[jedilyn]

Thanks a lot for your time @nemanjai , such a good idea to use script to verify various combination. I'm sorry I can't actually get your point about simplifying the logic in the switch block. Each case check in the switch seems not too much and exactly follow the patterns in above comments nearing the case, people can easily map the checks to patterns there. Do I miss something there? Could you kindly clarify more on that? Thanks in advance!

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

4136 ↗

(On Diff #169664)

OK, will add more comments here.

4157 ↗

(On Diff #169664)

This code is only for having internal select_cc, the ir looks like:
i64 = select_cc t2, t4, Constant:i64<-1>, Constant:i64<1>, setlt:ch
Line 4126-4127 already ensure the outside select_cc uses seteq and true value zero.
So inner select_cc can be represented as:
(t2 < t4)? -1: 1;

Since we want to canonicalize all innerSel to have true value 1 and false value -1, it actually implicitly swap values 1 and -1, so we only need to explictly swaps two comparision operands t2 and t4.
After the swapping it's changed to:
(t4 < t2)? 1: -1
It's already equivelant to the original expression, we don't need to swap the condition code.

4197 ↗

(On Diff #169664)

Sorry, I can't really catch your point here. The condition expression is to check all expected pattern listed in above close comments, they should be consistent. I'm not clear on what is difficult to follow? The condition combination or the NeedSwapOps computation?

llvm/lib/Target/PowerPC/PPCInstr64Bit.td

776 ↗

(On Diff #169664)

I was originally intended to move SETB to PPCInstrInfo.td, but I found this instruction is flagged as PPC64 only. I searched around in PPCInstrInfo.td and can't find any similar cases, so I didn't think it's a good idea to move one 64bit only instruction out of PPCInstr64Bit.td.

[jedilyn]

Addressed some comments from Nemanja.

[jedilyn]

llvm/lib/Target/PowerPC/PPCInstr64Bit.td

776 ↗

(On Diff #169664)

Does it make sense to still keep it in PPCInstr64Bit.td?

[jedilyn]

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

85 ↗

(On Diff #171628)

Need one more period "." at the end , will fix it with any possible updates for below unresolved comments.

[jedilyn]

gentle ping...

[jedilyn]

gentle ping...

[jedilyn]

gentle ping.... this is a patch for Power9 setb exploitation

[jsji]

Mostly good to me except some minor changes. @nemanjai Do you have any further comments regarding @jedilyn 's latest update? Thanks.

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

4710 ↗

(On Diff #171628)

Can we explain more why we need to avoid seteq optimization in SelectCC?

llvm/test/CodeGen/PowerPC/ppc64-P9-setb.ll

1 ↗

(On Diff #171628)

Please add new testcase in a NFC patch before this, and only show different due to this opt here. Thanks.

[jedilyn]

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

4710 ↗

(On Diff #171628)

OK, I'll update it. The following called SelectCC has some specific handling on seteq case.

llvm/test/CodeGen/PowerPC/ppc64-P9-setb.ll

1 ↗

(On Diff #171628)

Got it, I'll make a NFC patch.

[jedilyn]

Addressed Jinsong's comments.

[jsji]

LGTM, thanks for exploiting setb!

llvm/trunk/lib/Target/PowerPC/P9InstrResources.td

 def : InstRW<[P9_ALU_3C, IP_EXEC_1C, DISP_1C, DISP_1C],
       (instrs
     (instregex "XSMAX(C|J)?DP$"),
     (instregex "XSMIN(C|J)?DP$"),
     (instregex "XSCMP(EQ|EXP|GE|GT|O|U)DP$"),
     (instregex "CNT(L|T)Z(D|W)(8)?(o)?$"),
     (instregex "POPCNT(D|W)$"),
     (instregex "CMPB(8)?$"),
+    (instregex "SETB(8)?$"),
     XSTDIVDP,
     XSTSQRTDP,
     XSXSIGDP,
     XSCVSPDPN,
-    SETB,
     BPERMD
 )>;
 
 // Standard Dispatch ALU operation for 2 cycles. Only one slice used.
 def : InstRW<[P9_ALU_2C, IP_EXEC_1C, DISP_1C, DISP_1C],
       (instrs
     (instregex "S(L|R)D$"),
     (instregex "SRAD(I)?$"),

llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

 STATISTIC(SignExtensionsAdded,
           "Number of sign extensions for compare inputs added.");
 STATISTIC(ZeroExtensionsAdded,
           "Number of zero extensions for compare inputs added.");
 STATISTIC(NumLogicOpsOnComparison,
           "Number of logical ops on i1 values calculated in GPR.");
 STATISTIC(OmittedForNonExtendUses,
           "Number of compares not eliminated as they have non-extending uses.");
+STATISTIC(NumP9Setb,
+          "Number of compares lowered to setb.");
 
 // FIXME: Remove this once the bug has been fixed!
 cl::opt<bool> ANDIGlueBug("expose-ppc-andi-glue-bug",
 cl::desc("expose the ANDI glue bug on PPC"), cl::Hidden);
 
 static cl::opt<bool>
     UseBitPermRewriter("ppc-use-bit-perm-rewriter", cl::init(true),
                        cl::desc("use aggressive ppc isel for bit permutations"),

 }
 
 void PPCDAGToDAGISel::transferMemOperands(SDNode *N, SDNode *Result) {
   // Transfer memoperands.
   MachineMemOperand *MemOp = cast<MemSDNode>(N)->getMemOperand();
   CurDAG->setNodeMemRefs(cast<MachineSDNode>(Result), {MemOp});
 }
 
+static bool mayUseP9Setb(SDNode *N, const ISD::CondCode &CC, SelectionDAG *DAG,
+                         bool &NeedSwapOps, bool &IsUnCmp) {
+
+  assert(N->getOpcode() == ISD::SELECT_CC && "Expecting a SELECT_CC here.");
+
+  SDValue LHS = N->getOperand(0);
+  SDValue RHS = N->getOperand(1);
+  SDValue TrueRes = N->getOperand(2);
+  SDValue FalseRes = N->getOperand(3);
+  ConstantSDNode *TrueConst = dyn_cast<ConstantSDNode>(TrueRes);
+  if (!TrueConst)
+    return false;
+
+  assert((N->getSimpleValueType(0) == MVT::i64 ||
+          N->getSimpleValueType(0) == MVT::i32) &&
+         "Expecting either i64 or i32 here.");
+
+  // We are looking for any of:
+  // (select_cc lhs, rhs,  1, (sext (setcc [lr]hs, [lr]hs, cc2)), cc1)
+  // (select_cc lhs, rhs, -1, (zext (setcc [lr]hs, [lr]hs, cc2)), cc1)
+  // (select_cc lhs, rhs,  0, (select_cc [lr]hs, [lr]hs,  1, -1, cc2), seteq)
+  // (select_cc lhs, rhs,  0, (select_cc [lr]hs, [lr]hs, -1,  1, cc2), seteq)
+  int64_t TrueResVal = TrueConst->getSExtValue();
+  if ((TrueResVal < -1 || TrueResVal > 1) ||
+      (TrueResVal == -1 && FalseRes.getOpcode() != ISD::ZERO_EXTEND) ||
+      (TrueResVal == 1 && FalseRes.getOpcode() != ISD::SIGN_EXTEND) ||
+      (TrueResVal == 0 &&
+       (FalseRes.getOpcode() != ISD::SELECT_CC || CC != ISD::SETEQ)))
+    return false;
+
+  bool InnerIsSel = FalseRes.getOpcode() == ISD::SELECT_CC;
+  SDValue SetOrSelCC = InnerIsSel ? FalseRes : FalseRes.getOperand(0);
+  if (SetOrSelCC.getOpcode() != ISD::SETCC &&
+      SetOrSelCC.getOpcode() != ISD::SELECT_CC)
+    return false;
+
+  // Without this setb optimization, the outer SELECT_CC will be manually
+  // selected to SELECT_CC_I4/SELECT_CC_I8 Pseudo, then expand-isel-pseudos pass
+  // transforms pseduo instruction to isel instruction. When there are more than
+  // one use for result like zext/sext, with current optimization we only see
+  // isel is replaced by setb but can't see any significant gain. Since
+  // setb has longer latency than original isel, we should avoid this. Another
+  // point is that setb requires comparison always kept, it can break the
+  // oppotunity to get the comparison away if we have in future.
+  if (!SetOrSelCC.hasOneUse() || (!InnerIsSel && !FalseRes.hasOneUse()))
+    return false;
+
+  SDValue InnerLHS = SetOrSelCC.getOperand(0);
+  SDValue InnerRHS = SetOrSelCC.getOperand(1);
+  ISD::CondCode InnerCC =
+      cast<CondCodeSDNode>(SetOrSelCC.getOperand(InnerIsSel ? 4 : 2))->get();
+  // If the inner comparison is a select_cc, make sure the true/false values are
+  // 1/-1 and canonicalize it if needed.
+  if (InnerIsSel) {
+    ConstantSDNode *SelCCTrueConst =
+        dyn_cast<ConstantSDNode>(SetOrSelCC.getOperand(2));
+    ConstantSDNode *SelCCFalseConst =
+        dyn_cast<ConstantSDNode>(SetOrSelCC.getOperand(3));
+    if (!SelCCTrueConst || !SelCCFalseConst)
+      return false;
+    int64_t SelCCTVal = SelCCTrueConst->getSExtValue();
+    int64_t SelCCFVal = SelCCFalseConst->getSExtValue();
+    // The values must be -1/1 (requiring a swap) or 1/-1.
+    if (SelCCTVal == -1 && SelCCFVal == 1) {
+      std::swap(InnerLHS, InnerRHS);
+    } else if (SelCCTVal != 1 || SelCCFVal != -1)
+      return false;
+  }
+
+  // Canonicalize unsigned case
+  if (InnerCC == ISD::SETULT || InnerCC == ISD::SETUGT) {
+    IsUnCmp = true;
+    InnerCC = (InnerCC == ISD::SETULT) ? ISD::SETLT : ISD::SETGT;
+  }
+
+  bool InnerSwapped = false;
+  if (LHS == InnerRHS && RHS == InnerLHS)
+    InnerSwapped = true;
+  else if (LHS != InnerLHS || RHS != InnerRHS)
+    return false;
+
+  switch (CC) {
+  // (select_cc lhs, rhs,  0, \
+  //     (select_cc [lr]hs, [lr]hs, 1, -1, setlt/setgt), seteq)
+  case ISD::SETEQ:
+    if (!InnerIsSel)
+      return false;
+    if (InnerCC != ISD::SETLT && InnerCC != ISD::SETGT)
+      return false;
+    NeedSwapOps = (InnerCC == ISD::SETGT) ? InnerSwapped : !InnerSwapped;
+    break;
+
+  // (select_cc lhs, rhs, -1, (zext (setcc [lr]hs, [lr]hs, setne)), setu?lt)
+  // (select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setgt)), setu?lt)
+  // (select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setlt)), setu?lt)
+  // (select_cc lhs, rhs, 1, (sext (setcc [lr]hs, [lr]hs, setne)), setu?lt)
+  // (select_cc lhs, rhs, 1, (sext (setcc lhs, rhs, setgt)), setu?lt)
+  // (select_cc lhs, rhs, 1, (sext (setcc rhs, lhs, setlt)), setu?lt)
+  case ISD::SETULT:
+    if (!IsUnCmp && InnerCC != ISD::SETNE)
+      return false;
+    IsUnCmp = true;
+    LLVM_FALLTHROUGH;
+  case ISD::SETLT:
+    if (InnerCC == ISD::SETNE || (InnerCC == ISD::SETGT && !InnerSwapped) ||
+        (InnerCC == ISD::SETLT && InnerSwapped))
+      NeedSwapOps = (TrueResVal == 1);
+    else
+      return false;
+    break;
+
+  // (select_cc lhs, rhs, 1, (sext (setcc [lr]hs, [lr]hs, setne)), setu?gt)
+  // (select_cc lhs, rhs, 1, (sext (setcc lhs, rhs, setlt)), setu?gt)
+  // (select_cc lhs, rhs, 1, (sext (setcc rhs, lhs, setgt)), setu?gt)
+  // (select_cc lhs, rhs, -1, (zext (setcc [lr]hs, [lr]hs, setne)), setu?gt)
+  // (select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setlt)), setu?gt)
+  // (select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setgt)), setu?gt)
+  case ISD::SETUGT:
+    if (!IsUnCmp && InnerCC != ISD::SETNE)
+      return false;
+    IsUnCmp = true;
+    LLVM_FALLTHROUGH;
+  case ISD::SETGT:
+    if (InnerCC == ISD::SETNE || (InnerCC == ISD::SETLT && !InnerSwapped) ||
+        (InnerCC == ISD::SETGT && InnerSwapped))
+      NeedSwapOps = (TrueResVal == -1);
+    else
+      return false;
+    break;
+
+  default:
+    return false;
+  }
+
+  LLVM_DEBUG(dbgs() << "Found a node that can be lowered to a SETB: ");
+  LLVM_DEBUG(N->dump());
+
+  return true;
+}
+
 // Select - Convert the specified operand from a target-independent to a
 // target-specific node if it hasn't already been changed.
 void PPCDAGToDAGISel::Select(SDNode *N) {
   SDLoc dl(N);
   if (N->isMachineOpcode()) {
     N->setNodeId(-1);
     return;   // Already selected.
   }
EVT PtrVT =
         CurDAG->getTargetLoweringInfo().getPointerTy(CurDAG->getDataLayout());
     bool isPPC64 = (PtrVT == MVT::i64);
 
     // If this is a select of i1 operands, we'll pattern match it.
     if (PPCSubTarget->useCRBits() &&
         N->getOperand(0).getValueType() == MVT::i1)
       break;
 
+    if (PPCSubTarget->isISA3_0() && PPCSubTarget->isPPC64()) {
+      bool NeedSwapOps = false;
+      bool IsUnCmp = false;
+      if (mayUseP9Setb(N, CC, CurDAG, NeedSwapOps, IsUnCmp)) {
+        SDValue LHS = N->getOperand(0);
+        SDValue RHS = N->getOperand(1);
+        if (NeedSwapOps)
+          std::swap(LHS, RHS);
+
+        // Make use of SelectCC to generate the comparison to set CR bits, for
+        // equality comparisons having one literal operand, SelectCC probably
+        // doesn't need to materialize the whole literal and just use xoris to
+        // check it first, it leads the following comparison result can't
+        // exactly represent GT/LT relationship. So to avoid this we specify
+        // SETGT/SETUGT here instead of SETEQ.
+        SDValue GenCC =
+            SelectCC(LHS, RHS, IsUnCmp ? ISD::SETUGT : ISD::SETGT, dl);
+        CurDAG->SelectNodeTo(
+            N, N->getSimpleValueType(0) == MVT::i64 ? PPC::SETB8 : PPC::SETB,
+            N->getValueType(0), GenCC);
+        NumP9Setb++;
+        return;
+      }
+    }
+
     // Handle the setcc cases here.  select_cc lhs, 0, 1, 0, cc
     if (!isPPC64)
       if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
         if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N->getOperand(2)))
           if (ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N->getOperand(3)))
             if (N1C->isNullValue() && N3C->isNullValue() &&
                 N2C->getZExtValue() == 1ULL && CC == ISD::SETNE &&
                 // FIXME: Implement this optzn for PPC64.

llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td

 
 let Predicates = [IsISA3_0] in {
 def MADDHD : VAForm_1a<48, (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC),
                        "maddhd $RT, $RA, $RB, $RC", IIC_IntMulHD, []>, isPPC64;
 def MADDHDU : VAForm_1a<49, (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC),
                        "maddhdu $RT, $RA, $RB, $RC", IIC_IntMulHD, []>, isPPC64;
 def MADDLD : VAForm_1a<51, (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC),
                        "maddld $RT, $RA, $RB, $RC", IIC_IntMulHD, []>, isPPC64;
-def SETB : XForm_44<31, 128, (outs g8rc:$RT), (ins crrc:$BFA),
+def SETB : XForm_44<31, 128, (outs gprc:$RT), (ins crrc:$BFA),
                        "setb $RT, $BFA", IIC_IntGeneral>, isPPC64;
+let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
+  def SETB8 : XForm_44<31, 128, (outs g8rc:$RT), (ins crrc:$BFA),
+                       "setb $RT, $BFA", IIC_IntGeneral>, isPPC64;
+}
 def DARN : XForm_45<31, 755, (outs g8rc:$RT), (ins i32imm:$L),
                      "darn $RT, $L", IIC_LdStLD>, isPPC64;
 def ADDPCIS : DXForm<19, 2, (outs g8rc:$RT), (ins i32imm:$D),
                      "addpcis $RT, $D", IIC_BrB, []>, isPPC64;
 def MODSD : XForm_8<31, 777, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
                         "modsd $rT, $rA, $rB", IIC_IntDivW,
                         [(set i64:$rT, (srem i64:$rA, i64:$rB))]>;
 def MODUD : XForm_8<31, 265, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),

llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp

if (Opcode == PPC::LI     || Opcode == PPC::LI8     ||
       Opcode == PPC::LHZ    || Opcode == PPC::LHZX    ||
       Opcode == PPC::LHZ8   || Opcode == PPC::LHZX8   ||
       Opcode == PPC::LHZU   || Opcode == PPC::LHZUX   ||
       Opcode == PPC::LHZU8  || Opcode == PPC::LHZUX8  ||
       Opcode == PPC::EXTSB  || Opcode == PPC::EXTSBo  ||
       Opcode == PPC::EXTSH  || Opcode == PPC::EXTSHo  ||
       Opcode == PPC::EXTSB8 || Opcode == PPC::EXTSH8  ||
       Opcode == PPC::EXTSW  || Opcode == PPC::EXTSWo  ||
+      Opcode == PPC::SETB   || Opcode == PPC::SETB8   ||
       Opcode == PPC::EXTSH8_32_64 || Opcode == PPC::EXTSW_32_64 ||
       Opcode == PPC::EXTSB8_32_64)
     return true;
 
   if (Opcode == PPC::RLDICL && MI.getOperand(3).getImm() >= 33)
     return true;
 
   if ((Opcode == PPC::RLWINM || Opcode == PPC::RLWINMo ||

llvm/trunk/test/CodeGen/PowerPC/ppc64-P9-setb.ll

 ; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
 ; RUN:   -enable-ppc-quad-precision -ppc-asm-full-reg-names < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown \
 ; RUN:   -ppc-asm-full-reg-names < %s | FileCheck %s -check-prefix=CHECK-PWR8    \
 ; RUN:   -implicit-check-not "\<setb\>"
 
 ; Test different patterns with type i64
 
 ; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setne)), setlt
 define i64 @setb1(i64 %a, i64 %b) {
   %t1 = icmp slt i64 %a, %b
   %t2 = icmp ne i64 %a, %b
   %t3 = zext i1 %t2 to i64
   %t4 = select i1 %t1, i64 -1, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setb1
-; CHECK-DAG: xor
-; CHECK-DAG: li
-; CHECK-DAG: cmpd
-; CHECK-DAG: addic
-; CHECK-DAG: subfe
-; CHECK: isel
+; CHECK-LABEL: setb1:
+; CHECK-NOT: xor
+; CHECK-NOT: li
+; CHECK: cmpd {{c?r?(0, )?}}r3, r4
+; CHECK-NEXT: setb r3, cr0
+; CHECK-NOT: addic
+; CHECK-NOT: subfe
+; CHECK-NOT: isel
 ; CHECK: blr
 ; CHECK-PWR8-LABEL: setb1
 ; CHECK-PWR8-DAG: xor
 ; CHECK-PWR8-DAG: li
 ; CHECK-PWR8-DAG: cmpd
 ; CHECK-PWR8-DAG: addic
 ; CHECK-PWR8-DAG: subfe
 ; CHECK-PWR8: isel
 ; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setne)), setgt
 define i64 @setb2(i64 %a, i64 %b) {
   %t1 = icmp sgt i64 %b, %a
   %t2 = icmp ne i64 %a, %b
   %t3 = zext i1 %t2 to i64
   %t4 = select i1 %t1, i64 -1, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setb2
-; CHECK-DAG: xor
-; CHECK-DAG: li
-; CHECK-DAG: cmpd
-; CHECK-DAG: addic
-; CHECK-DAG: subfe
-; CHECK: isel
+; CHECK-LABEL: setb2:
+; CHECK-NOT: xor
+; CHECK-NOT: li
+; CHECK: cmpd {{c?r?(0, )?}}r3, r4
+; CHECK-NEXT: setb r3, cr0
+; CHECK-NOT: addic
+; CHECK-NOT: subfe
+; CHECK-NOT: isel
 ; CHECK: blr
 ; CHECK-PWR8-LABEL: setb2
 ; CHECK-PWR8-DAG: xor
 ; CHECK-PWR8-DAG: li
 ; CHECK-PWR8-DAG: cmpd
 ; CHECK-PWR8-DAG: addic
 ; CHECK-PWR8-DAG: subfe
 ; CHECK-PWR8: isel
 ; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setne)), setlt
 define i64 @setb3(i64 %a, i64 %b) {
   %t1 = icmp slt i64 %a, %b
   %t2 = icmp ne i64 %b, %a
   %t3 = zext i1 %t2 to i64
   %t4 = select i1 %t1, i64 -1, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setb3
-; CHECK-DAG: xor
-; CHECK-DAG: li
-; CHECK-DAG: cmpd
-; CHECK-DAG: addic
-; CHECK-DAG: subfe
-; CHECK: isel
+; CHECK-LABEL: setb3:
+; CHECK-NOT: xor
+; CHECK-NOT: li
+; CHECK: cmpd {{c?r?(0, )?}}r3, r4
+; CHECK-NEXT: setb r3, cr0
+; CHECK-NOT: addic
+; CHECK-NOT: subfe
+; CHECK-NOT: isel
 ; CHECK: blr
 ; CHECK-PWR8-LABEL: setb3
 ; CHECK-PWR8-DAG: xor
 ; CHECK-PWR8-DAG: li
 ; CHECK-PWR8-DAG: cmpd
 ; CHECK-PWR8-DAG: addic
 ; CHECK-PWR8-DAG: subfe
 ; CHECK-PWR8: isel
 ; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setne)), setgt
 define i64 @setb4(i64 %a, i64 %b) {
   %t1 = icmp sgt i64 %b, %a
   %t2 = icmp ne i64 %b, %a
   %t3 = zext i1 %t2 to i64
   %t4 = select i1 %t1, i64 -1, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setb4
-; CHECK-DAG: xor
-; CHECK-DAG: li
-; CHECK-DAG: cmpd
-; CHECK-DAG: addic
-; CHECK-DAG: subfe
-; CHECK: isel
+; CHECK-LABEL: setb4:
+; CHECK-NOT: xor
+; CHECK-NOT: li
+; CHECK: cmpd {{c?r?(0, )?}}r3, r4
+; CHECK-NEXT: setb r3, cr0
+; CHECK-NOT: addic
+; CHECK-NOT: subfe
+; CHECK-NOT: isel
 ; CHECK: blr
 ; CHECK-PWR8-LABEL: setb4
 ; CHECK-PWR8-DAG: xor
 ; CHECK-PWR8-DAG: li
 ; CHECK-PWR8-DAG: cmpd
 ; CHECK-PWR8-DAG: addic
 ; CHECK-PWR8-DAG: subfe
 ; CHECK-PWR8: isel
 ; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setgt)), setlt
 define i64 @setb5(i64 %a, i64 %b) {
   %t1 = icmp slt i64 %a, %b
   %t2 = icmp sgt i64 %a, %b
   %t3 = zext i1 %t2 to i64
   %t4 = select i1 %t1, i64 -1, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setb5
-; CHECK-DAG: sradi
-; CHECK-DAG: rldicl
-; CHECK-DAG: li
-; CHECK-DAG: cmpd
-; CHECK-DAG: subfc
-; CHECK-DAG: adde
-; CHECK-DAG: xori
-; CHECK: isel
+; CHECK-LABEL: setb5:
+; CHECK-NOT: sradi
+; CHECK-NOT: rldicl
+; CHECK-NOT: li
+; CHECK: cmpd {{c?r?(0, )?}}r3, r4
+; CHECK-NEXT: setb r3, cr0
+; CHECK-NOT: subfc
+; CHECK-NOT: adde
+; CHECK-NOT: xori
+; CHECK-NOT: isel
 ; CHECK: blr
 ; CHECK-PWR8-LABEL: setb5
 ; CHECK-PWR8-DAG: sradi
 ; CHECK-PWR8-DAG: rldicl
 ; CHECK-PWR8-DAG: li
 ; CHECK-PWR8-DAG: cmpd
 ; CHECK-PWR8-DAG: subfc
 ; CHECK-PWR8-DAG: adde
 ; CHECK-PWR8-DAG: xori
 ; CHECK-PWR8: isel
 ; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setgt)), setgt
 define i64 @setb6(i64 %a, i64 %b) {
   %t1 = icmp sgt i64 %b, %a
   %t2 = icmp sgt i64 %a, %b
   %t3 = zext i1 %t2 to i64
   %t4 = select i1 %t1, i64 -1, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setb6
-; CHECK-DAG: sradi
-; CHECK-DAG: rldicl
-; CHECK-DAG: li
-; CHECK-DAG: cmpd
-; CHECK-DAG: subfc
-; CHECK-DAG: adde
-; CHECK-DAG: xori
-; CHECK: isel
+; CHECK-LABEL: setb6:
+; CHECK-NOT: sradi
+; CHECK-NOT: rldicl
+; CHECK-NOT: li
+; CHECK: cmpd {{c?r?(0, )?}}r3, r4
+; CHECK-NEXT: setb r3, cr0
+; CHECK-NOT: subfc
+; CHECK-NOT: adde
+; CHECK-NOT: xori
+; CHECK-NOT: isel
 ; CHECK: blr
 ; CHECK-PWR8-LABEL: setb6
 ; CHECK-PWR8-DAG: sradi
 ; CHECK-PWR8-DAG: rldicl
 ; CHECK-PWR8-DAG: li
 ; CHECK-PWR8-DAG: cmpd
 ; CHECK-PWR8-DAG: subfc
 ; CHECK-PWR8-DAG: adde
 ; CHECK-PWR8-DAG: xori
 ; CHECK-PWR8: isel
 ; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setlt)), setlt
 define i64 @setb7(i64 %a, i64 %b) {
   %t1 = icmp slt i64 %a, %b
   %t2 = icmp slt i64 %b, %a
   %t3 = zext i1 %t2 to i64
   %t4 = select i1 %t1, i64 -1, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setb7
-; CHECK-DAG: sradi
-; CHECK-DAG: rldicl
-; CHECK-DAG: li
-; CHECK-DAG: cmpd
-; CHECK-DAG: subfc
-; CHECK-DAG: adde
-; CHECK-DAG: xori
-; CHECK: isel
+; CHECK-LABEL: setb7:
+; CHECK-NOT: sradi
+; CHECK-NOT: rldicl
+; CHECK-NOT: li
+; CHECK: cmpd {{c?r?(0, )?}}r3, r4
+; CHECK-NEXT: setb r3, cr0
+; CHECK-NOT: subfc
+; CHECK-NOT: adde
+; CHECK-NOT: xori
+; CHECK-NOT: isel
 ; CHECK: blr
 ; CHECK-PWR8-LABEL: setb7
 ; CHECK-PWR8-DAG: sradi
 ; CHECK-PWR8-DAG: rldicl
 ; CHECK-PWR8-DAG: li
 ; CHECK-PWR8-DAG: cmpd
 ; CHECK-PWR8-DAG: subfc
 ; CHECK-PWR8-DAG: adde
 ; CHECK-PWR8-DAG: xori
 ; CHECK-PWR8: isel
 ; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setlt)), setgt
 define i64 @setb8(i64 %a, i64 %b) {
   %t1 = icmp sgt i64 %b, %a
   %t2 = icmp slt i64 %b, %a
   %t3 = zext i1 %t2 to i64
   %t4 = select i1 %t1, i64 -1, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setb8
-; CHECK-DAG: sradi
-; CHECK-DAG: rldicl
-; CHECK-DAG: li
-; CHECK-DAG: cmpd
-; CHECK-DAG: subfc
-; CHECK-DAG: adde
-; CHECK-DAG: xori
-; CHECK: isel
+; CHECK-LABEL: setb8:
+; CHECK-NOT: sradi
+; CHECK-NOT: rldicl
+; CHECK-NOT: li
+; CHECK: cmpd {{c?r?(0, )?}}r3, r4
+; CHECK-NEXT: setb r3, cr0
+; CHECK-NOT: subfc
+; CHECK-NOT: adde
+; CHECK-NOT: xori
+; CHECK-NOT: isel
 ; CHECK: blr
 ; CHECK-PWR8-LABEL: setb8
 ; CHECK-PWR8-DAG: sradi
 ; CHECK-PWR8-DAG: rldicl
 ; CHECK-PWR8-DAG: li
 ; CHECK-PWR8-DAG: cmpd
 ; CHECK-PWR8-DAG: subfc
 ; CHECK-PWR8-DAG: adde
 ; CHECK-PWR8-DAG: xori
 ; CHECK-PWR8: isel
 ; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, 1, (sext (setcc lhs, rhs, setne)), setgt
 define i64 @setb9(i64 %a, i64 %b) {
   %t1 = icmp sgt i64 %a, %b
   %t2 = icmp ne i64 %a, %b
   %t3 = sext i1 %t2 to i64
   %t4 = select i1 %t1, i64 1, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setb9
-; CHECK-DAG: xor
-; CHECK-DAG: li
-; CHECK-DAG: cmpd
-; CHECK-DAG: subfic
-; CHECK-DAG: subfe
-; CHECK-DAG: isel
+; CHECK-LABEL: setb9:
+; CHECK-NOT: xor
+; CHECK-NOT: li
+; CHECK: cmpd {{c?r?(0, )?}}r3, r4
+; CHECK-NEXT: setb r3, cr0
+; CHECK-NOT: subfic
+; CHECK-NOT: subfe
+; CHECK-NOT: isel
 ; CHECK: blr
 ; CHECK-PWR8-LABEL: setb9
 ; CHECK-PWR8-DAG: xor
 ; CHECK-PWR8-DAG: li
 ; CHECK-PWR8-DAG: cmpd
 ; CHECK-PWR8-DAG: subfic
 ; CHECK-PWR8-DAG: subfe
 ; CHECK-PWR8: isel
 ; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, 1, (sext (setcc rhs, lhs, setne)), setlt
 define i64 @setb10(i64 %a, i64 %b) {
   %t1 = icmp slt i64 %b, %a
   %t2 = icmp ne i64 %a, %b
   %t3 = sext i1 %t2 to i64
   %t4 = select i1 %t1, i64 1, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setb10
-; CHECK-DAG: xor
-; CHECK-DAG: li
-; CHECK-DAG: cmpd
-; CHECK-DAG: subfic
-; CHECK-DAG: subfe
-; CHECK-DAG: isel
+; CHECK-LABEL: setb10:
+; CHECK-NOT: xor
+; CHECK-NOT: li
+; CHECK: cmpd {{c?r?(0, )?}}r3, r4
+; CHECK-NEXT: setb r3, cr0
+; CHECK-NOT: subfic
+; CHECK-NOT: subfe
+; CHECK-NOT: isel
 ; CHECK: blr
 ; CHECK-PWR8-LABEL: setb10
 ; CHECK-PWR8-DAG: xor
 ; CHECK-PWR8-DAG: li
 ; CHECK-PWR8-DAG: cmpd
 ; CHECK-PWR8-DAG: subfic
 ; CHECK-PWR8-DAG: subfe
 ; CHECK-PWR8: isel
 ; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, 1, (sext (setcc rhs, lhs, setne)), setgt
 define i64 @setb11(i64 %a, i64 %b) {
   %t1 = icmp sgt i64 %a, %b
   %t2 = icmp ne i64 %b, %a
   %t3 = sext i1 %t2 to i64
   %t4 = select i1 %t1, i64 1, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setb11
-; CHECK-DAG: xor
-; CHECK-DAG: li
-; CHECK-DAG: cmpd
-; CHECK-DAG: subfic
-; CHECK-DAG: subfe
-; CHECK-DAG: isel
+; CHECK-LABEL: setb11:
+; CHECK-NOT: xor
+; CHECK-NOT: li
+; CHECK: cmpd {{c?r?(0, )?}}r3, r4
+; CHECK-NEXT: setb r3, cr0
+; CHECK-NOT: subfic
+; CHECK-NOT: subfe
+; CHECK-NOT: isel
 ; CHECK: blr
 ; CHECK-PWR8-LABEL: setb11
 ; CHECK-PWR8-DAG: xor
 ; CHECK-PWR8-DAG: li
 ; CHECK-PWR8-DAG: cmpd
 ; CHECK-PWR8-DAG: subfic
 ; CHECK-PWR8-DAG: subfe
 ; CHECK-PWR8: isel
 ; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, 1, (sext (setcc lhs, rhs, setne)), setlt
 define i64 @setb12(i64 %a, i64 %b) {
   %t1 = icmp slt i64 %b, %a
   %t2 = icmp ne i64 %b, %a
   %t3 = sext i1 %t2 to i64
   %t4 = select i1 %t1, i64 1, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setb12
-; CHECK-DAG: xor
-; CHECK-DAG: li
-; CHECK-DAG: cmpd
-; CHECK-DAG: subfic
-; CHECK-DAG: subfe
-; CHECK-DAG: isel
+; CHECK-LABEL: setb12:
+; CHECK-NOT: xor
+; CHECK-NOT: li
+; CHECK: cmpd {{c?r?(0, )?}}r3, r4
+; CHECK-NEXT: setb r3, cr0
+; CHECK-NOT: subfic
+; CHECK-NOT: subfe
+; CHECK-NOT: isel
 ; CHECK: blr
 ; CHECK-PWR8-LABEL: setb12
 ; CHECK-PWR8-DAG: xor
 ; CHECK-PWR8-DAG: li
 ; CHECK-PWR8-DAG: cmpd
 ; CHECK-PWR8-DAG: subfic
 ; CHECK-PWR8-DAG: subfe
 ; CHECK-PWR8: isel
 ; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, 1, (sext (setcc lhs, rhs, setlt)), setgt
 define i64 @setb13(i64 %a, i64 %b) {
   %t1 = icmp sgt i64 %a, %b
   %t2 = icmp slt i64 %a, %b
   %t3 = sext i1 %t2 to i64
   %t4 = select i1 %t1, i64 1, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setb13
-; CHECK-DAG: sradi
-; CHECK-DAG: rldicl
-; CHECK-DAG: li
-; CHECK-DAG: cmpd
-; CHECK-DAG: subfc
-; CHECK-DAG: adde
-; CHECK-DAG: xori
-; CHECK-DAG: neg
-; CHECK: isel
+; CHECK-LABEL: setb13:
+; CHECK-NOT: sradi
+; CHECK-NOT: rldicl
+; CHECK-NOT: li
+; CHECK: cmpd {{c?r?(0, )?}}r3, r4
+; CHECK-NEXT: setb r3, cr0
+; CHECK-NOT: subfc
+; CHECK-NOT: adde
+; CHECK-NOT: xori
+; CHECK-NOT: neg
+; CHECK-NOT: isel
 ; CHECK: blr
 ; CHECK-PWR8-LABEL: setb13
 ; CHECK-PWR8-DAG: sradi
 ; CHECK-PWR8-DAG: rldicl
 ; CHECK-PWR8-DAG: li
 ; CHECK-PWR8-DAG: cmpd
 ; CHECK-PWR8-DAG: subfc
 ; CHECK-PWR8-DAG: adde
 ; CHECK-PWR8-DAG: xori
 ; CHECK-PWR8-DAG: neg
 ; CHECK-PWR8: isel
 ; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, 1, (sext (setcc rhs, lhs, setlt)), setlt
 define i64 @setb14(i64 %a, i64 %b) {
   %t1 = icmp slt i64 %b, %a
   %t2 = icmp slt i64 %a, %b
   %t3 = sext i1 %t2 to i64
   %t4 = select i1 %t1, i64 1, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setb14
-; CHECK-DAG: sradi
-; CHECK-DAG: rldicl
-; CHECK-DAG: li
-; CHECK-DAG: cmpd
-; CHECK-DAG: subfc
-; CHECK-DAG: adde
-; CHECK-DAG: xori
-; CHECK-DAG: neg
-; CHECK: isel
+; CHECK-LABEL: setb14:
+; CHECK-NOT: sradi
+; CHECK-NOT: rldicl
+; CHECK-NOT: li
+; CHECK: cmpd {{c?r?(0, )?}}r3, r4
+; CHECK-NEXT: setb r3, cr0
+; CHECK-NOT: subfc
+; CHECK-NOT: adde
+; CHECK-NOT: xori
+; CHECK-NOT: neg
+; CHECK-NOT: isel
 ; CHECK: blr
 ; CHECK-PWR8-LABEL: setb14
 ; CHECK-PWR8-DAG: sradi
 ; CHECK-PWR8-DAG: rldicl
 ; CHECK-PWR8-DAG: li
 ; CHECK-PWR8-DAG: cmpd
 ; CHECK-PWR8-DAG: subfc
 ; CHECK-PWR8-DAG: adde
 ; CHECK-PWR8-DAG: xori
 ; CHECK-PWR8-DAG: neg
 ; CHECK-PWR8: isel
 ; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, 1, (sext (setcc rhs, lhs, setgt)), setgt
 define i64 @setb15(i64 %a, i64 %b) {
   %t1 = icmp sgt i64 %a, %b
   %t2 = icmp sgt i64 %b, %a
   %t3 = sext i1 %t2 to i64
   %t4 = select i1 %t1, i64 1, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setb15
-; CHECK-DAG: sradi
-; CHECK-DAG: rldicl
-; CHECK-DAG: li
-; CHECK-DAG: cmpd
-; CHECK-DAG: subfc
-; CHECK-DAG: adde
-; CHECK-DAG: xori
-; CHECK-DAG: neg
-; CHECK: isel
+; CHECK-LABEL: setb15:
+; CHECK-NOT: sradi
+; CHECK-NOT: rldicl
+; CHECK-NOT: li
+; CHECK: cmpd {{c?r?(0, )?}}r3, r4
+; CHECK-NEXT: setb r3, cr0
+; CHECK-NOT: subfc
+; CHECK-NOT: adde
+; CHECK-NOT: xori
+; CHECK-NOT: neg
+; CHECK-NOT: isel
 ; CHECK: blr
 ; CHECK-PWR8-LABEL: setb15
 ; CHECK-PWR8-DAG: sradi
 ; CHECK-PWR8-DAG: rldicl
 ; CHECK-PWR8-DAG: li
 ; CHECK-PWR8-DAG: cmpd
 ; CHECK-PWR8-DAG: subfc
 ; CHECK-PWR8-DAG: adde
 ; CHECK-PWR8-DAG: xori
 ; CHECK-PWR8-DAG: neg
 ; CHECK-PWR8: isel
 ; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, 1, (sext (setcc lhs, rhs, setgt)), setlt
 define i64 @setb16(i64 %a, i64 %b) {
   %t1 = icmp slt i64 %b, %a
   %t2 = icmp sgt i64 %b, %a
   %t3 = sext i1 %t2 to i64
   %t4 = select i1 %t1, i64 1, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setb16
-; CHECK-DAG: sradi
-; CHECK-DAG: rldicl
-; CHECK-DAG: li
-; CHECK-DAG: cmpd
-; CHECK-DAG: subfc
-; CHECK-DAG: adde
-; CHECK-DAG: xori
-; CHECK-DAG: neg
-; CHECK: isel
+; CHECK-LABEL: setb16:
+; CHECK-NOT: sradi
+; CHECK-NOT: rldicl
+; CHECK-NOT: li
+; CHECK: cmpd {{c?r?(0, )?}}r3, r4
+; CHECK-NEXT: setb r3, cr0
+; CHECK-NOT: subfc
+; CHECK-NOT: adde
+; CHECK-NOT: xori
+; CHECK-NOT: neg
+; CHECK-NOT: isel
 ; CHECK: blr
 ; CHECK-PWR8-LABEL: setb16
 ; CHECK-PWR8-DAG: sradi
 ; CHECK-PWR8-DAG: rldicl
 ; CHECK-PWR8-DAG: li
 ; CHECK-PWR8-DAG: cmpd
 ; CHECK-PWR8-DAG: subfc
 ; CHECK-PWR8-DAG: adde
 ; CHECK-PWR8-DAG: xori
 ; CHECK-PWR8-DAG: neg
 ; CHECK-PWR8: isel
 ; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, 0, (select_cc lhs, rhs, 1, -1, setgt), seteq
 define i64 @setb17(i64 %a, i64 %b) {
   %t1 = icmp eq i64 %a, %b
   %t2 = icmp sgt i64 %a, %b
   %t3 = select i1 %t2, i64 1, i64 -1
   %t4 = select i1 %t1, i64 0, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setb17
-; CHECK-DAG: li
-; CHECK-DAG: li
-; CHECK-DAG: cmpd
-; CHECK: isel
-; CHECK: cmpld
-; CHECK: isel
+; CHECK-LABEL: setb17:
+; CHECK-NOT: li
+; CHECK-NOT: cmpld
+; CHECK-NOT: isel
+; CHECK: cmpd {{c?r?(0, )?}}r3, r4
+; CHECK-NEXT: setb r3, cr0
+; CHECK-NOT: isel
 ; CHECK: blr
 ; CHECK-PWR8-LABEL: setb17
 ; CHECK-PWR8: cmpd
 ; CHECK-PWR8: isel
 ; CHECK-PWR8: cmpld
 ; CHECK-PWR8: isel
 ; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, 0, (select_cc rhs, lhs, 1, -1, setgt), seteq
 define i64 @setb18(i64 %a, i64 %b) {
   %t1 = icmp eq i64 %b, %a
   %t2 = icmp sgt i64 %a, %b
   %t3 = select i1 %t2, i64 1, i64 -1
   %t4 = select i1 %t1, i64 0, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setb18
-; CHECK-DAG: li
-; CHECK-DAG: li
-; CHECK-DAG: cmpd
-; CHECK: isel
-; CHECK: cmpld
-; CHECK: isel
+; CHECK-LABEL: setb18:
+; CHECK-NOT: li
+; CHECK-NOT: cmpld
+; CHECK-NOT: isel
+; CHECK: cmpd {{c?r?(0, )?}}r3, r4
+; CHECK-NEXT: setb r3, cr0
+; CHECK-NOT: isel
 ; CHECK: blr
 ; CHECK-PWR8-LABEL: setb18
 ; CHECK-PWR8: cmpd
 ; CHECK-PWR8: isel
 ; CHECK-PWR8: cmpld
 ; CHECK-PWR8: isel
 ; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, 0, (select_cc rhs, lhs, 1, -1, setlt), seteq
 define i64 @setb19(i64 %a, i64 %b) {
   %t1 = icmp eq i64 %a, %b
   %t2 = icmp slt i64 %b, %a
   %t3 = select i1 %t2, i64 1, i64 -1
   %t4 = select i1 %t1, i64 0, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setb19
-; CHECK-DAG: li
-; CHECK-DAG: li
-; CHECK-DAG: cmpd
-; CHECK: isel
-; CHECK: cmpld
-; CHECK: isel
+; CHECK-LABEL: setb19:
+; CHECK-NOT: li
+; CHECK-NOT: cmpld
+; CHECK-NOT: isel
+; CHECK: cmpd {{c?r?(0, )?}}r3, r4
+; CHECK-NEXT: setb r3, cr0
+; CHECK-NOT: isel
 ; CHECK: blr
 ; CHECK-PWR8-LABEL: setb19
 ; CHECK-PWR8: cmpd
 ; CHECK-PWR8: isel
 ; CHECK-PWR8: cmpld
 ; CHECK-PWR8: isel
 ; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, 0, (select_cc lhs, rhs, 1, -1, setlt), seteq
 define i64 @setb20(i64 %a, i64 %b) {
   %t1 = icmp eq i64 %b, %a
   %t2 = icmp slt i64 %b, %a
   %t3 = select i1 %t2, i64 1, i64 -1
   %t4 = select i1 %t1, i64 0, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setb20
-; CHECK-DAG: li
-; CHECK-DAG: li
-; CHECK-DAG: cmpd
-; CHECK: isel
-; CHECK: cmpld
-; CHECK: isel
+; CHECK-LABEL: setb20:
+; CHECK-NOT: li
+; CHECK-NOT: cmpld
+; CHECK-NOT: isel
+; CHECK: cmpd {{c?r?(0, )?}}r3, r4
+; CHECK-NEXT: setb r3, cr0
+; CHECK-NOT: isel
 ; CHECK: blr
 ; CHECK-PWR8-LABEL: setb20
 ; CHECK-PWR8: cmpd
 ; CHECK-PWR8: isel
 ; CHECK-PWR8: cmpld
 ; CHECK-PWR8: isel
 ; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, 0, (select_cc lhs, rhs, -1, 1, setlt), seteq
 define i64 @setb21(i64 %a, i64 %b) {
   %t1 = icmp eq i64 %a, %b
   %t2 = icmp slt i64 %a, %b
   %t3 = select i1 %t2, i64 -1, i64 1
   %t4 = select i1 %t1, i64 0, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setb21
-; CHECK-DAG: li
-; CHECK-DAG: li
-; CHECK-DAG: cmpd
-; CHECK: isel
-; CHECK: cmpld
-; CHECK: isel
+; CHECK-LABEL: setb21:
+; CHECK-NOT: li
+; CHECK-NOT: cmpld
+; CHECK-NOT: isel
+; CHECK: cmpd {{c?r?(0, )?}}r3, r4
+; CHECK-NEXT: setb r3, cr0
+; CHECK-NOT: isel
 ; CHECK: blr
 ; CHECK-PWR8-LABEL: setb21
 ; CHECK-PWR8: cmpd
 ; CHECK-PWR8: isel
 ; CHECK-PWR8: cmpld
 ; CHECK-PWR8: isel
 ; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, 0, (select_cc rhs, lhs, -1, 1, setlt), seteq
 define i64 @setb22(i64 %a, i64 %b) {
   %t1 = icmp eq i64 %b, %a
   %t2 = icmp slt i64 %a, %b
   %t3 = select i1 %t2, i64 -1, i64 1
   %t4 = select i1 %t1, i64 0, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setb22
-; CHECK-DAG: li
-; CHECK-DAG: li
-; CHECK-DAG: cmpd
-; CHECK-DAG: isel
-; CHECK-DAG: cmpld
-; CHECK: isel
+; CHECK-LABEL: setb22:
+; CHECK-NOT: li
+; CHECK-NOT: cmpld
+; CHECK-NOT: isel
+; CHECK: cmpd {{c?r?(0, )?}}r3, r4
+; CHECK-NEXT: setb r3, cr0
+; CHECK-NOT: isel
 ; CHECK: blr
 ; CHECK-PWR8-LABEL: setb22
 ; CHECK-PWR8: cmpd
 ; CHECK-PWR8: isel
 ; CHECK-PWR8: cmpld
 ; CHECK-PWR8: isel
 ; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, 0, (select_cc rhs, lhs, -1, 1, setgt), seteq
 define i64 @setb23(i64 %a, i64 %b) {
   %t1 = icmp eq i64 %a, %b
   %t2 = icmp sgt i64 %b, %a
   %t3 = select i1 %t2, i64 -1, i64 1
   %t4 = select i1 %t1, i64 0, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setb23
-; CHECK-DAG: li
-; CHECK-DAG: li
-; CHECK-DAG: cmpd
-; CHECK: isel
-; CHECK: cmpld
-; CHECK: isel
+; CHECK-LABEL: setb23:
+; CHECK-NOT: li
+; CHECK-NOT: cmpld
+; CHECK-NOT: isel
+; CHECK: cmpd {{c?r?(0, )?}}r3, r4
+; CHECK-NEXT: setb r3, cr0
+; CHECK-NOT: isel
 ; CHECK: blr
 ; CHECK-PWR8-LABEL: setb23
 ; CHECK-PWR8: cmpd
 ; CHECK-PWR8: isel
 ; CHECK-PWR8: cmpld
 ; CHECK-PWR8: isel
 ; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, 0, (select_cc lhs, rhs, -1, 1, setgt), seteq
 define i64 @setb24(i64 %a, i64 %b) {
   %t1 = icmp eq i64 %b, %a
   %t2 = icmp sgt i64 %b, %a
   %t3 = select i1 %t2, i64 -1, i64 1
   %t4 = select i1 %t1, i64 0, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setb24
-; CHECK-DAG: li
-; CHECK-DAG: li
-; CHECK-DAG: cmpd
-; CHECK: isel
-; CHECK: cmpld
-; CHECK: isel
+; CHECK-LABEL: setb24:
+; CHECK-NOT: li
+; CHECK-NOT: cmpld
+; CHECK-NOT: isel
+; CHECK: cmpd {{c?r?(0, )?}}r3, r4
+; CHECK-NEXT: setb r3, cr0
+; CHECK-NOT: isel
 ; CHECK: blr
 ; CHECK-PWR8-LABEL: setb24
 ; CHECK-PWR8: cmpd
 ; CHECK-PWR8: isel
 ; CHECK-PWR8: cmpld
 ; CHECK-PWR8: isel
 ; CHECK-PWR8: blr
 }
 ; end all patterns testing for i64
 
 ; Test with swapping the input parameters
 
 ; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setne)), setlt
 define i64 @setb25(i64 %a, i64 %b) {
   %t1 = icmp slt i64 %b, %a
   %t2 = icmp ne i64 %b, %a
   %t3 = zext i1 %t2 to i64
   %t4 = select i1 %t1, i64 -1, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setb25
-; CHECK-DAG: xor
-; CHECK-DAG: li
-; CHECK-DAG: cmpd
-; CHECK-DAG: addic
-; CHECK-DAG: subfe
-; CHECK: isel
+; CHECK-LABEL: setb25:
+; CHECK-NOT: xor
+; CHECK-NOT: li
+; CHECK-NOT: cmpd
+; CHECK: cmpd {{c?r?(0, )?}}r4, r3
+; CHECK-NEXT: setb r3, cr0
+; CHECK-NOT: addic
+; CHECK-NOT: subfe
+; CHECK-NOT: isel
 ; CHECK: blr
 ; CHECK-PWR8-LABEL: setb25
 ; CHECK-PWR8-DAG: cmpd
 ; CHECK-PWR8-DAG: addic
 ; CHECK-PWR8-DAG: subfe
 ; CHECK-PWR8: isel
 ; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setne)), setgt
 define i64 @setb26(i64 %a, i64 %b) {
   %t1 = icmp sgt i64 %a, %b
   %t2 = icmp ne i64 %b, %a
   %t3 = zext i1 %t2 to i64
   %t4 = select i1 %t1, i64 -1, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setb26
-; CHECK-DAG: xor
-; CHECK-DAG: li
-; CHECK-DAG: cmpd
-; CHECK-DAG: addic
-; CHECK-DAG: subfe
-; CHECK: isel
+; CHECK-LABEL: setb26:
+; CHECK-NOT: xor
+; CHECK-NOT: li
+; CHECK: cmpd {{c?r?(0, )?}}r4, r3
+; CHECK-NEXT: setb r3, cr0
+; CHECK-NOT: addic
+; CHECK-NOT: subfe
+; CHECK-NOT: isel
 ; CHECK: blr
 ; CHECK-PWR8-LABEL: setb26
 ; CHECK-PWR8-DAG: cmpd
 ; CHECK-PWR8-DAG: addic
 ; CHECK-PWR8-DAG: subfe
 ; CHECK-PWR8: isel
 ; CHECK-PWR8: blr
 }
 
 ; Test with different scalar integer type for selected value
 ; i32/i16/i8 rather than i64 above
 
 ; select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setne)), setlt
 define i64 @setb27(i64 %a, i64 %b) {
   %t1 = icmp slt i64 %a, %b
   %t2 = icmp ne i64 %b, %a
   %t3 = zext i1 %t2 to i32
   %t4 = select i1 %t1, i32 -1, i32 %t3
   %t5 = sext i32 %t4 to i64
   ret i64 %t5
-; CHECK-LABEL: setb27
-; CHECK-DAG: xor
-; CHECK-DAG: li
-; CHECK-DAG: cmpd
-; CHECK-DAG: addic
-; CHECK-DAG: subfe
-; CHECK: isel
+; CHECK-LABEL: setb27:
+; CHECK-NOT: xor
+; CHECK-NOT: li
+; CHECK: cmpd {{c?r?(0, )?}}r3, r4
+; CHECK-NEXT: setb r3, cr0
+; CHECK-NOT: addic
+; CHECK-NOT: subfe
+; CHECK-NOT: isel
 ; CHECK: extsw
 ; CHECK: blr
 ; CHECK-PWR8-LABEL: setb27
 ; CHECK-PWR8-DAG: cmpd
 ; CHECK-PWR8-DAG: addic
 ; CHECK-PWR8-DAG: subfe
 ; CHECK-PWR8: isel
 ; CHECK-PWR8: extsw
 ; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setne)), setgt
 define i64 @setb28(i64 %a, i64 %b) {
   %t1 = icmp sgt i64 %b, %a
   %t2 = icmp ne i64 %b, %a
   %t3 = zext i1 %t2 to i16
   %t4 = select i1 %t1, i16 -1, i16 %t3
   %t5 = sext i16 %t4 to i64
   ret i64 %t5
-; CHECK-LABEL: setb28
-; CHECK-DAG: xor
-; CHECK-DAG: li
-; CHECK-DAG: cmpd
-; CHECK-DAG: addic
-; CHECK-DAG: subfe
-; CHECK: isel
+; CHECK-LABEL: setb28:
+; CHECK-NOT: xor
+; CHECK-NOT: li
+; CHECK: cmpd {{c?r?(0, )?}}r3, r4
+; CHECK-NEXT: setb r3, cr0
+; CHECK-NOT: addic
+; CHECK-NOT: subfe
+; CHECK-NOT: isel
 ; CHECK: extsh
 ; CHECK: blr
 ; CHECK-PWR8-LABEL: setb28
 ; CHECK-PWR8-DAG: cmpd
 ; CHECK-PWR8-DAG: addic
 ; CHECK-PWR8-DAG: subfe
 ; CHECK-PWR8: isel
 ; CHECK-PWR8: extsh
 ; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setgt)), setlt
 define i64 @setb29(i64 %a, i64 %b) {
   %t1 = icmp slt i64 %a, %b
   %t2 = icmp sgt i64 %a, %b
   %t3 = zext i1 %t2 to i8
   %t4 = select i1 %t1, i8 -1, i8 %t3
   %t5 = zext i8 %t4 to i64
   ret i64 %t5
-; CHECK-LABEL: setb29
-; CHECK-DAG: sradi
-; CHECK-DAG: rldicl
-; CHECK-DAG: li
-; CHECK-DAG: cmpd
-; CHECK-DAG: subfc
-; CHECK-DAG: adde
-; CHECK-DAG: xori
-; CHECK-DAG: isel
+; CHECK-LABEL: setb29:
+; CHECK-NOT: sradi
+; CHECK-NOT: rldicl
+; CHECK-NOT: li
+; CHECK: cmpd {{c?r?(0, )?}}r3, r4
+; CHECK-NEXT: setb r3, cr0
+; CHECK-NOT: subfc
+; CHECK-NOT: adde
+; CHECK-NOT: xori
+; CHECK-NOT: isel
 ; CHECK: blr
 ; CHECK-PWR8-LABEL: setb29
 ; CHECK-PWR8-DAG: cmpd
 ; CHECK-PWR8-DAG: subfc
 ; CHECK-PWR8-DAG: adde
 ; CHECK-PWR8: isel
 ; CHECK-PWR8: blr
 }
 
 ; Testings to cover different comparison opcodes
 ; Test with integer type i32/i16/i8 for input parameter
 
 ; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setne)), setlt
 define i64 @setbsw1(i32 %a, i32 %b) {
   %t1 = icmp slt i32 %a, %b
   %t2 = icmp ne i32 %a, %b
   %t3 = zext i1 %t2 to i64
   %t4 = select i1 %t1, i64 -1, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setbsw1
-; CHECK-DAG: xor
-; CHECK-DAG: li
-; CHECK-DAG: cmpw
-; CHECK-DAG: cntlzw
-; CHECK-DAG: srwi
-; CHECK-DAG: xori
-; CHECK: isel
+; CHECK-LABEL: setbsw1:
+; CHECK-NOT: xor
+; CHECK-NOT: li
+; CHECK: cmpw {{c?r?(0, )?}}r3, r4
+; CHECK-NEXT: setb r3, cr0
+; CHECK-NOT: cntlzw
+; CHECK-NOT: srwi
+; CHECK-NOT: xori
+; CHECK-NOT: isel
 ; CHECK: blr
 ; CHECK-PWR8-LABEL: setbsw1
 ; CHECK-PWR8-DAG: cntlzw
 ; CHECK-PWR8-DAG: cmpw
 ; CHECK-PWR8-DAG: srwi
 ; CHECK-PWR8-DAG: xori
 ; CHECK-PWR8: isel
 ; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setne)), setgt
 define i64 @setbsw2(i32 %a, i32 %b) {
   %t1 = icmp sgt i32 %b, %a
   %t2 = icmp ne i32 %a, %b
   %t3 = zext i1 %t2 to i64
   %t4 = select i1 %t1, i64 -1, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setbsw2
-; CHECK-DAG: xor
-; CHECK-DAG: li
-; CHECK-DAG: cmpw
-; CHECK-DAG: cntlzw
-; CHECK-DAG: srwi
-; CHECK-DAG: xori
-; CHECK: isel
+; CHECK-LABEL: setbsw2:
+; CHECK-NOT: xor
+; CHECK-NOT: li
+; CHECK: cmpw {{c?r?(0, )?}}r3, r4
+; CHECK-NEXT: setb r3, cr0
+; CHECK-NOT: cntlzw
+; CHECK-NOT: srwi
+; CHECK-NOT: xori
+; CHECK-NOT: isel
 ; CHECK: blr
 ; CHECK-PWR8-LABEL: setbsw2
 ; CHECK-PWR8-DAG: cntlzw
 ; CHECK-PWR8-DAG: cmpw
 ; CHECK-PWR8-DAG: srwi
 ; CHECK-PWR8-DAG: xori
 ; CHECK-PWR8: isel
 ; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, 0, (select_cc rhs, lhs, -1, 1, setgt), seteq
 define i64 @setbsw3(i32 %a, i32 %b) {
   %t1 = icmp eq i32 %a, %b
   %t2 = icmp sgt i32 %b, %a
   %t3 = select i1 %t2, i64 -1, i64 1
   %t4 = select i1 %t1, i64 0, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setbsw3
-; CHECK-DAG: li
-; CHECK-DAG: li
-; CHECK-DAG: cmpw
-; CHECK: isel
-; CHECK: cmplw
-; CHECK: isel
+; CHECK-LABEL: setbsw3:
+; CHECK-NOT: li
+; CHECK: cmpw {{c?r?(0, )?}}r3, r4
+; CHECK-NEXT: setb r3, cr0
+; CHECK-NOT: isel
+; CHECK-NOT: cmplw
+; CHECK-NOT: isel
 ; CHECK: blr
 ; CHECK-PWR8-LABEL: setbsw3
 ; CHECK-PWR8: cmpw
 ; CHECK-PWR8: isel
 ; CHECK-PWR8: cmplw
 ; CHECK-PWR8: isel
 ; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setne)), setlt
 define i64 @setbsh1(i16 signext %a, i16 signext %b) {
   %t1 = icmp slt i16 %a, %b
   %t2 = icmp ne i16 %b, %a
   %t3 = zext i1 %t2 to i64
   %t4 = select i1 %t1, i64 -1, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setbsh1
-; CHECK-DAG: xor
-; CHECK-DAG: li
-; CHECK-DAG: cmpw
-; CHECK-DAG: cntlzw
-; CHECK-DAG: srwi
-; CHECK-DAG: xori
-; CHECK: isel
+; CHECK-LABEL: setbsh1:
+; CHECK-NOT: xor
+; CHECK-NOT: li
+; CHECK: cmpw {{c?r?(0, )?}}r3, r4
+; CHECK-NEXT: setb r3, cr0
+; CHECK-NOT: cntlzw
+; CHECK-NOT: srwi
+; CHECK-NOT: xori
+; CHECK-NOT: isel
 ; CHECK: blr
 ; CHECK-PWR8-LABEL: setbsh1
 ; CHECK-PWR8-DAG: cntlzw
 ; CHECK-PWR8-DAG: cmpw
 ; CHECK-PWR8-DAG: srwi
 ; CHECK-PWR8-DAG: xori
 ; CHECK-PWR8: isel
 ; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setne)), setgt
 define i64 @setbsh2(i16 signext %a, i16 signext %b) {
   %t1 = icmp sgt i16 %b, %a
   %t2 = icmp ne i16 %b, %a
   %t3 = zext i1 %t2 to i64
   %t4 = select i1 %t1, i64 -1, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setbsh2
-; CHECK-DAG: xor
-; CHECK-DAG: li
-; CHECK-DAG: cmpw
-; CHECK-DAG: cntlzw
-; CHECK-DAG: srwi
-; CHECK-DAG: xori
-; CHECK: isel
+; CHECK-LABEL: setbsh2:
+; CHECK-NOT: xor
+; CHECK-NOT: li
+; CHECK: cmpw {{c?r?(0, )?}}r3, r4
+; CHECK-NEXT: setb r3, cr0
+; CHECK-NOT: cntlzw
+; CHECK-NOT: srwi
+; CHECK-NOT: xori
+; CHECK-NOT: isel
 ; CHECK: blr
 ; CHECK-PWR8-LABEL: setbsh2
 ; CHECK-PWR8-DAG: cmpw
 ; CHECK-PWR8-DAG: cntlzw
 ; CHECK-PWR8-DAG: srwi
 ; CHECK-PWR8-DAG: xori
 ; CHECK-PWR8: isel
 ; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setgt)), setlt
 define i64 @setbsc1(i8 %a, i8 %b) {
   %t1 = icmp slt i8 %a, %b
   %t2 = icmp sgt i8 %a, %b
   %t3 = zext i1 %t2 to i64
   %t4 = select i1 %t1, i64 -1, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setbsc1
+; CHECK-LABEL: setbsc1:
 ; CHECK-DAG: extsb [[RA:r[0-9]+]], r3
 ; CHECK-DAG: extsb [[RB:r[0-9]+]], r4
-; CHECK-DAG: li
-; CHECK-DAG: sub
-; CHECK-DAG: cmpw {{c?r?(0, )?}}[[RA]], [[RB]]
-; CHECK-DAG: rldicl
-; CHECK: isel
+; CHECK-NOT: li
+; CHECK-NOT: sub
+; CHECK: cmpw {{c?r?(0, )?}}[[RA]], [[RB]]
+; CHECK-NEXT: setb r3, cr0
+; CHECK-NOT: rldicl
+; CHECK-NOT: isel
 ; CHECK: blr
 ; CHECK-PWR8-LABEL: setbsc1
 ; CHECK-PWR8-DAG: extsb
 ; CHECK-PWR8-DAG: extsb
 ; CHECK-PWR8-DAG: extsw
 ; CHECK-PWR8-DAG: extsw
 ; CHECK-PWR8-DAG: cmpw
 ; CHECK-PWR8-DAG: rldicl
 ; CHECK-PWR8: isel
 ; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setgt)), setgt
 define i64 @setbsc2(i8 %a, i8 %b) {
   %t1 = icmp sgt i8 %b, %a
   %t2 = icmp sgt i8 %a, %b
   %t3 = zext i1 %t2 to i64
   %t4 = select i1 %t1, i64 -1, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setbsc2
+; CHECK-LABEL: setbsc2:
 ; CHECK-DAG: extsb [[RA:r[0-9]+]], r3
 ; CHECK-DAG: extsb [[RB:r[0-9]+]], r4
-; CHECK-DAG: li
-; CHECK-DAG: sub
-; CHECK-DAG: cmpw
-; CHECK-DAG: rldicl
-; CHECK: isel
+; CHECK-NOT: li
+; CHECK-NOT: sub
+; CHECK: cmpw {{c?r?(0, )?}}[[RA]], [[RB]]
+; CHECK-NEXT: setb r3, cr0
+; CHECK-NOT: rldicl
+; CHECK-NOT: isel
 ; CHECK: blr
 ; CHECK-PWR8-LABEL: setbsc2
 ; CHECK-PWR8-DAG: extsb
 ; CHECK-PWR8-DAG: extsb
 ; CHECK-PWR8-DAG: extsw
 ; CHECK-PWR8-DAG: extsw
 ; CHECK-PWR8-DAG: cmpw
 ; CHECK-PWR8-DAG: rldicl
 ; CHECK-PWR8: isel
 ; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setlt)), setlt
 define i64 @setbsc3(i4 %a, i4 %b) {
   %t1 = icmp slt i4 %a, %b
   %t2 = icmp slt i4 %b, %a
   %t3 = zext i1 %t2 to i64
   %t4 = select i1 %t1, i64 -1, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setbsc3
+; CHECK-LABEL: setbsc3:
 ; CHECK-DAG: slwi [[RA:r[0-9]+]], r3, 28
 ; CHECK-DAG: slwi [[RB:r[0-9]+]], r4, 28
-; CHECK-DAG: li
+; CHECK-NOT: li
 ; CHECK-DAG: srawi [[RA1:r[0-9]+]], [[RA]], 28
 ; CHECK-DAG: srawi [[RB1:r[0-9]+]], [[RB]], 28
-; CHECK-DAG: sub
-; CHECK-DAG: cmpw
-; CHECK-DAG: rldicl
-; CHECK: isel
+; CHECK-NOT: sub
+; CHECK: cmpw {{c?r?(0, )?}}[[RA1]], [[RB1]]
+; CHECK-NEXT: setb r3, cr0
+; CHECK-NOT: rldicl
+; CHECK-NOT: isel
 ; CHECK: blr
 ; CHECK-PWR8-LABEL: setbsc3
 ; CHECK-PWR8-DAG: slwi
 ; CHECK-PWR8-DAG: slwi
 ; CHECK-PWR8-DAG: srawi
 ; CHECK-PWR8-DAG: srawi
 ; CHECK-PWR8-DAG: extsw
 ; CHECK-PWR8-DAG: extsw
 ; CHECK-PWR8-DAG: cmpw
 ; CHECK-PWR8-DAG: rldicl
 ; CHECK-PWR8: isel
 ; CHECK-PWR8: blr
 }
 
 ; Test with unsigned integer type i64/i32/i16/i8 for input parameter
 
 ; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setult)), setugt
 define i64 @setbud1(i64 %a, i64 %b) {
   %t1 = icmp ugt i64 %b, %a
   %t2 = icmp ult i64 %b, %a
   %t3 = zext i1 %t2 to i64
   %t4 = select i1 %t1, i64 -1, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setbud1
-; CHECK-DAG: li
-; CHECK-DAG: cmpld
-; CHECK-DAG: subfc
-; CHECK-DAG: subfe
-; CHECK-DAG: neg
-; CHECK: isel
+; CHECK-LABEL: setbud1:
+; CHECK-NOT: li
+; CHECK: cmpld {{c?r?(0, )?}}r3, r4
+; CHECK-NEXT: setb r3, cr0
+; CHECK-NOT: subfc
+; CHECK-NOT: subfe
+; CHECK-NOT: neg
+; CHECK-NOT: isel
 ; CHECK: blr
 ; CHECK-PWR8-LABEL: setbud1
 ; CHECK-PWR8-DAG: subfc
 ; CHECK-PWR8-DAG: subfe
 ; CHECK-PWR8-DAG: cmpld
 ; CHECK-PWR8-DAG: neg
 ; CHECK-PWR8: isel
 ; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, 1, (sext (setcc lhs, rhs, setne)), setugt
 define i64 @setbud2(i64 %a, i64 %b) {
   %t1 = icmp ugt i64 %a, %b
   %t2 = icmp ne i64 %a, %b
   %t3 = sext i1 %t2 to i64
   %t4 = select i1 %t1, i64 1, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setbud2
-; CHECK-DAG: xor
-; CHECK-DAG: li
-; CHECK: cmpld
-; CHECK-DAG: subfic
-; CHECK-DAG: subfe
-; CHECK: isel
+; CHECK-LABEL: setbud2:
+; CHECK-NOT: xor
+; CHECK-NOT: li
+; CHECK: cmpld {{c?r?(0, )?}}r3, r4
+; CHECK-NEXT: setb r3, cr0
+; CHECK-NOT: subfic
+; CHECK-NOT: subfe
+; CHECK-NOT: isel
 ; CHECK: blr
 ; CHECK-PWR8-LABEL: setbud2
 ; CHECK-PWR8-DAG: cmpld
 ; CHECK-PWR8-DAG: subfic
 ; CHECK-PWR8-DAG: subfe
 ; CHECK-PWR8: isel
 ; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, 0, (select_cc lhs, rhs, -1, 1, setugt), seteq
 define i64 @setbud3(i64 %a, i64 %b) {
   %t1 = icmp eq i64 %b, %a
   %t2 = icmp ugt i64 %b, %a
   %t3 = select i1 %t2, i64 -1, i64 1
   %t4 = select i1 %t1, i64 0, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setbud3
-; CHECK-DAG: li
-; CHECK: cmpld
-; CHECK-DAG: li
-; CHECK: isel
-; CHECK: isel
+; CHECK-LABEL: setbud3:
+; CHECK-NOT: li
+; CHECK: cmpld {{c?r?(0, )?}}r3, r4
+; CHECK-NEXT: setb r3, cr0
+; CHECK-NOT: li
+; CHECK-NOT: isel
 ; CHECK: blr
 ; CHECK-PWR8-LABEL: setbud3
 ; CHECK-PWR8-DAG: cmpld
 ; CHECK-PWR8-DAG: li
 ; CHECK-PWR8-DAG: li
 ; CHECK-PWR8: isel
 ; CHECK-PWR8: isel
 ; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, 1, (sext (setcc rhs, lhs, setne)), setult
 define i64 @setbuw1(i32 %a, i32 %b) {
   %t1 = icmp ult i32 %b, %a
   %t2 = icmp ne i32 %a, %b
   %t3 = sext i1 %t2 to i64
   %t4 = select i1 %t1, i64 1, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setbuw1
-; CHECK-DAG: xor
-; CHECK-DAG: li
-; CHECK-DAG: cmplw
-; CHECK-DAG: cntlzw
-; CHECK-DAG: srwi
-; CHECK-DAG: xori
-; CHECK-DAG: neg
-; CHECK: isel
+; CHECK-LABEL: setbuw1:
+; CHECK-NOT: xor
+; CHECK-NOT: li
+; CHECK: cmplw {{c?r?(0, )?}}r3, r4
+; CHECK-NEXT: setb r3, cr0
+; CHECK-NOT: cntlzw
+; CHECK-NOT: srwi
+; CHECK-NOT: xori
+; CHECK-NOT: neg
+; CHECK-NOT: isel
 ; CHECK: blr
 ; CHECK-PWR8-LABEL: setbuw1
 ; CHECK-PWR8-DAG: cntlzw
 ; CHECK-PWR8-DAG: cmplw
 ; CHECK-PWR8-DAG: srwi
 ; CHECK-PWR8-DAG: xori
 ; CHECK-PWR8-DAG: neg
 ; CHECK-PWR8: isel
 ; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, 1, (sext (setcc rhs, lhs, setne)), setugt
 define i64 @setbuw2(i32 %a, i32 %b) {
   %t1 = icmp ugt i32 %a, %b
   %t2 = icmp ne i32 %b, %a
   %t3 = sext i1 %t2 to i64
   %t4 = select i1 %t1, i64 1, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setbuw2
-; CHECK-DAG: xor
-; CHECK-DAG: li
-; CHECK-DAG: cmplw
-; CHECK-DAG: cntlzw
-; CHECK-DAG: srwi
-; CHECK-DAG: xori
-; CHECK-DAG: neg
-; CHECK: isel
+; CHECK-LABEL: setbuw2:
+; CHECK-NOT: xor
+; CHECK-NOT: li
+; CHECK: cmplw {{c?r?(0, )?}}r3, r4
+; CHECK-NEXT: setb r3, cr0
+; CHECK-NOT: cntlzw
+; CHECK-NOT: srwi
+; CHECK-NOT: xori
+; CHECK-NOT: neg
+; CHECK-NOT: isel
 ; CHECK: blr
 ; CHECK-PWR8-LABEL: setbuw2
 ; CHECK-PWR8-DAG: cntlzw
 ; CHECK-PWR8-DAG: cmplw
 ; CHECK-PWR8-DAG: srwi
 ; CHECK-PWR8-DAG: xori
 ; CHECK-PWR8-DAG: neg
 ; CHECK-PWR8: isel
 ; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, 1, (sext (setcc lhs, rhs, setne)), setult
 define i64 @setbuh(i16 %a, i16 %b) {
   %t1 = icmp ult i16 %b, %a
   %t2 = icmp ne i16 %b, %a
   %t3 = sext i1 %t2 to i64
   %t4 = select i1 %t1, i64 1, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setbuh
+; CHECK-LABEL: setbuh:
 ; CHECK-DAG: rlwinm [[RA:r[0-9]+]], r3, 0, 16, 31
 ; CHECK-DAG: rlwinm [[RB:r[0-9]+]], r4, 0, 16, 31
-; CHECK-DAG: li
-; CHECK-DAG: xor
-; CHECK-DAG: cmplw
-; CHECK-DAG: cntlzw
-; CHECK-DAG: srwi
-; CHECK-DAG: xori
-; CHECK-DAG: neg
-; CHECK: isel
+; CHECK-NOT: li
+; CHECK-NOT: xor
+; CHECK: cmplw {{c?r?(0, )?}}[[RA]], [[RB]]
+; CHECK-NEXT: setb r3, cr0
+; CHECK-NOT: cntlzw
+; CHECK-NOT: srwi
+; CHECK-NOT: xori
+; CHECK-NOT: neg
+; CHECK-NOT: isel
 ; CHECK: blr
 ; CHECK-PWR8-LABEL: setbuh
 ; CHECK-PWR8: rlwinm
 ; CHECK-PWR8: rlwinm
 ; CHECK-PWR8-DAG: cmplw
 ; CHECK-PWR8-DAG: cntlzw
 ; CHECK-PWR8: srwi
 ; CHECK-PWR8: xori
 ; CHECK-PWR8: neg
 ; CHECK-PWR8: isel
 ; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, 1, (sext (setcc lhs, rhs, setult)), setugt
 define i64 @setbuc(i8 %a, i8 %b) {
   %t1 = icmp ugt i8 %a, %b
   %t2 = icmp ult i8 %a, %b
   %t3 = sext i1 %t2 to i64
   %t4 = select i1 %t1, i64 1, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setbuc
+; CHECK-LABEL: setbuc:
 ; CHECK-DAG: rlwinm [[RA:r[0-9]+]], r3, 0, 24, 31
 ; CHECK-DAG: rlwinm [[RB:r[0-9]+]], r4, 0, 24, 31
-; CHECK-DAG: li
-; CHECK-DAG: clrldi
-; CHECK-DAG: clrldi
-; CHECK-DAG: cmplw
-; CHECK-DAG: sub
-; CHECK-DAG: sradi
-; CHECK: isel
+; CHECK-NOT: li
+; CHECK-NOT: clrldi
+; CHECK: cmplw {{c?r?(0, )?}}[[RA]], [[RB]]
+; CHECK-NEXT: setb r3, cr0
+; CHECK-NOT: sub
+; CHECK-NOT: sradi
+; CHECK-NOT: isel
 ; CHECK: blr
 ; CHECK-PWR8-LABEL: setbuc
 ; CHECK-PWR8: rlwinm
 ; CHECK-PWR8: rlwinm
 ; CHECK-PWR8-DAG: clrldi
 ; CHECK-PWR8-DAG: clrldi
 ; CHECK-PWR8-DAG: cmplw
 ; CHECK-PWR8: sradi
 ; CHECK-PWR8: isel
 ; CHECK-PWR8: blr
 }
 
 ; Test with float/double/float128 for input parameter
 
 ; select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setlt)), setlt
 define i64 @setbf1(float %a, float %b) {
   %t1 = fcmp fast olt float %a, %b
   %t2 = fcmp fast olt float %b, %a
   %t3 = zext i1 %t2 to i64
   %t4 = select i1 %t1, i64 -1, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setbf1
-; CHECK: fcmpu
-; CHECK-DAG: li
-; CHECK-DAG: li
-; CHECK-DAG: fcmpu
-; CHECK: isel
-; CHECK: li
-; CHECK: isel
+; CHECK-LABEL: setbf1:
+; CHECK-NOT: li
+; CHECK: fcmpu cr0, f1, f2
+; CHECK-NEXT: setb r3, cr0
+; CHECK-NOT: isel
+; CHECK-NOT: li
 ; CHECK: blr
 ; CHECK-PWR8-LABEL: setbf1
 ; CHECK-PWR8: isel
 ; CHECK-PWR8: isel
 ; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setlt)), setgt
 define i64 @setbf2(float %a, float %b) {
   %t1 = fcmp fast ogt float %b, %a
   %t2 = fcmp fast olt float %b, %a
   %t3 = zext i1 %t2 to i64
   %t4 = select i1 %t1, i64 -1, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setbf2
-; CHECK-DAG: li
-; CHECK-DAG: li
-; CHECK-DAG: fcmpu
-; CHECK-DAG: isel
-; CHECK-DAG: li
-; CHECK: isel
+; CHECK-LABEL: setbf2:
+; CHECK-NOT: li
+; CHECK: fcmpu cr0, f1, f2
+; CHECK-NEXT: setb r3, cr0
+; CHECK-NOT: isel
+; CHECK-NOT: li
 ; CHECK: blr
 ; CHECK-PWR8-LABEL: setbf2
 ; CHECK-PWR8: isel
 ; CHECK-PWR8: isel
 ; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, 0, (select_cc lhs, rhs, -1, 1, setgt), seteq
 define i64 @setbdf1(double %a, double %b) {
   %t1 = fcmp fast oeq double %b, %a
   %t2 = fcmp fast ogt double %b, %a
   %t3 = select i1 %t2, i64 -1, i64 1
   %t4 = select i1 %t1, i64 0, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setbdf1
-; CHECK-DAG: xscmpudp
-; CHECK-DAG: li
-; CHECK-DAG: li
-; CHECK: isel
-; CHECK: isel
+; CHECK-LABEL: setbdf1:
+; CHECK: xscmpudp cr0, f1, f2
+; CHECK-NEXT: setb r3, cr0
+; CHECK-NOT: li
+; CHECK-NOT: isel
 ; CHECK: blr
 ; CHECK-PWR8-LABEL: setbdf1
 ; CHECK-PWR8: isel
 ; CHECK-PWR8: isel
 ; CHECK-PWR8: blr
 }
 
 ; select_cc lhs, rhs, 1, (sext (setcc lhs, rhs, setgt)), setlt
 define i64 @setbdf2(double %a, double %b) {
   %t1 = fcmp fast olt double %b, %a
   %t2 = fcmp fast ogt double %b, %a
   %t3 = sext i1 %t2 to i64
   %t4 = select i1 %t1, i64 1, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setbdf2
-; CHECK-DAG: fcmpu
-; CHECK-DAG: li
-; CHECK-DAG: li
-; CHECK-DAG: xscmpudp
-; CHECK-DAG: isel
-; CHECK-DAG: li
-; CHECK: isel
+; CHECK-LABEL: setbdf2:
+; CHECK-NOT: fcmpu
+; CHECK-NOT: li
+; CHECK: xscmpudp cr0, f1, f2
+; CHECK-NEXT: setb r3, cr0
+; CHECK-NOT: li
+; CHECK-NOT: isel
 ; CHECK: blr
 ; CHECK-PWR8-LABEL: setbdf2
 ; CHECK-PWR8: isel
 ; CHECK-PWR8: isel
 ; CHECK-PWR8: blr
 }
 
 define i64 @setbf128(fp128 %a, fp128 %b) {
   %t1 = fcmp fast ogt fp128 %a, %b
   %t2 = fcmp fast olt fp128 %a, %b
   %t3 = sext i1 %t2 to i64
   %t4 = select i1 %t1, i64 1, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setbf128
-; CHECK-DAG: li
-; CHECK-DAG: li
-; CHECK-DAG: xscmpuqp
-; CHECK-DAG: isel
-; CHECK-DAG: li
-; CHECK: isel
+; CHECK-LABEL: setbf128:
+; CHECK-NOT: li
+; CHECK: xscmpuqp cr0, v2, v3
+; CHECK-NEXT: setb r3, cr0
+; CHECK-NOT: isel
+; CHECK-NOT: li
 ; CHECK: blr
 ; CHECK-PWR8-LABEL: setbf128
 ; CHECK-PWR8: isel
 ; CHECK-PWR8: blr
 }
 
 ; Some cases we can't leverage setb
 
 define i64 @setbn1(i64 %a, i64 %b) {
   %t1 = icmp slt i64 %a, %b
   %t2 = icmp eq i64 %a, %b
   %t3 = zext i1 %t2 to i64
   %t4 = select i1 %t1, i64 -1, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setbn1
+; CHECK-LABEL: setbn1:
 ; CHECK-NOT: {{\<setb\>}}
 ; CHECK: isel
 ; CHECK: blr
 }
 
 define i64 @setbn2(double %a, double %b) {
   %t1 = fcmp olt double %a, %b
   %t2 = fcmp one double %a, %b
   %t3 = zext i1 %t2 to i64
   %t4 = select i1 %t1, i64 -1, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setbn2
+; CHECK-LABEL: setbn2:
 ; CHECK-NOT: {{\<setb\>}}
 ; CHECK: isel
 ; CHECK: blr
 }
 
 define i64 @setbn3(float %a, float %b) {
   %t1 = fcmp ult float %a, %b
   %t2 = fcmp une float %a, %b
   %t3 = zext i1 %t2 to i64
   %t4 = select i1 %t1, i64 -1, i64 %t3
   ret i64 %t4
-; CHECK-LABEL: setbn3
+; CHECK-LABEL: setbn3:
 ; CHECK-NOT: {{\<setb\>}}
 ; CHECK: isel
 ; CHECK: blr
 }