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[MachineCSE][GlobalISel] Making sure MachineCSE works mid-GlobalISel (again)
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Authored by rtereshin on Oct 11 2018, 10:09 AM.

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Summary

Change of approach, it looks like it's much better idea to deal with the
vregs that have LLTs and reg classes both properly, than trying to
avoid creating those across all GlobalISel passes and all targets.

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rL LLVM

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rtereshin created this revision.Oct 11 2018, 10:09 AM

Thanks for working on this. LGTM.

This revision is now accepted and ready to land.Oct 15 2018, 3:20 PM
rtereshin added inline comments.Oct 15 2018, 3:21 PM
lib/CodeGen/MachineCSE.cpp
258 ↗(On Diff #169233)

MachineRegisterInfo::isConstantPhysReg expects the reserved registers to be frozen.
The problem doesn't trigger post-ISel as most (if not all) targets freeze reserved registers
right after ISel. Here I have inlined by hand the MachineRegisterInfo:: isCallerPreservedOrConstPhysReg
and protected half of the condition. There is no test covering this as the only way to insert
a new pass (MachineCSE) from a command line I know of is llcs -run-pass option, which only
works with MIR, but MIRParser freezes reserved registers upon MachineFunctions creation,
making it impossible to reproduce the state that exposes the issue.

lib/CodeGen/MachineRegisterInfo.cpp
93 ↗(On Diff #169233)

Apparently, for now this is only used by MachineCSE.
The changes are NFC for any pipeline but one that
contains MachineCSE mid-GlobalISel.

This revision was automatically updated to reflect the committed changes.