[llvm-exegesis][NFC] Make SnippetGenerator a pure virtual interface.

[gchatelet]

Summary

The purpose of this change is too have many different Snippet Generators for Latency. This allows for testing several snippets for the same instruction. The end goal is: many simple generators that describe what they're doing and how to interpret the resulting measure.

[gchatelet]

As discussed let's drop this change and return many CodeTemplate instead of a single one, moving the informations into CodeTemplate.

tools/llvm-exegesis/lib/Latency.h

 #include "BenchmarkRunner.h"
 #include "MCInstrDescView.h"
 #include "SnippetGenerator.h"
 
 namespace exegesis {
 
 class LatencySnippetGenerator : public SnippetGenerator {
 public:
-  LatencySnippetGenerator(const LLVMState &State) : SnippetGenerator(State) {}
+  LatencySnippetGenerator(const LLVMState &State) : State(State) {}
   ~LatencySnippetGenerator() override;
 
   llvm::Expected<CodeTemplate>
   generateCodeTemplate(const Instruction &Instr) const override;
 
 private:
+  const LLVMState &State;
+
   llvm::Expected<CodeTemplate>
   generateTwoInstructionPrototype(const Instruction &Instr) const;
 };
 
 class LatencyBenchmarkRunner : public BenchmarkRunner {
 public:
   LatencyBenchmarkRunner(const LLVMState &State)
       : BenchmarkRunner(State, InstructionBenchmark::Latency) {}

tools/llvm-exegesis/lib/SnippetGenerator.h

 #include "llvm/MC/MCInst.h"
 #include "llvm/Support/Error.h"
 #include <cstdlib>
 #include <memory>
 #include <vector>
 
 namespace exegesis {
 
-// A class representing failures that happened during Benchmark, they are used
-// to report informations to the user.
-class SnippetGeneratorFailure : public llvm::StringError {
-public:
-  SnippetGeneratorFailure(const llvm::Twine &S);
-};
-
-// Common code for all benchmark modes.
-class SnippetGenerator {
-public:
-  explicit SnippetGenerator(const LLVMState &State);
-
-  virtual ~SnippetGenerator();
-
-  // Calls generateCodeTemplate and expands it into one or more BenchmarkCode.
-  llvm::Expected<std::vector<BenchmarkCode>>
-  generateConfigurations(const Instruction &Instr) const;
-
-  // Given a snippet, computes which registers the setup code needs to define.
-  std::vector<RegisterValue> computeRegisterInitialValues(
-      const std::vector<InstructionTemplate> &Snippet) const;
+    const RegisterAliasingTrackerCache &RATC,
+    const std::vector<InstructionTemplate> &Instructions);
 
-protected:
-  const LLVMState &State;
+// Expands a CodeTemplate into one or more BenchmarkCode.
+std::vector<BenchmarkCode>
+generateConfigurations(const RegisterAliasingTrackerCache &RATC,
+                       CodeTemplate &CT);
 
-  // Generates a single code template that has a self-dependency.
-  llvm::Expected<CodeTemplate>
-  generateSelfAliasingCodeTemplate(const Instruction &Instr) const;
-  // Generates a single code template without assignment constraints.
-  llvm::Expected<CodeTemplate>
-  generateUnconstrainedCodeTemplate(const Instruction &Instr,
-                                    llvm::StringRef Msg) const;
+generateSelfAliasingCodeTemplate(const Instruction &Instr);
+
+                                  llvm::StringRef Msg);
+
+// A class representing failures that happened during Benchmark, they are
+// used to report informations to the user.
+class SnippetGeneratorFailure : public llvm::StringError {
+public:
+  SnippetGeneratorFailure(const llvm::Twine &S);
+};
+
+// Interface for generating code templates.
+class SnippetGenerator {
+public:
+  virtual ~SnippetGenerator();
 
-private:
-  // API to be implemented by subclasses.
   virtual llvm::Expected<CodeTemplate>
   generateCodeTemplate(const Instruction &Instr) const = 0;
 };
 
 // A global Random Number Generator to randomize configurations.
 // FIXME: Move random number generation into an object and make it seedable for
 // unit tests.
 std::mt19937 &randomGenerator();

tools/llvm-exegesis/lib/SnippetGenerator.cpp

 #include "llvm/ADT/StringRef.h"
 #include "llvm/ADT/Twine.h"
 #include "llvm/Support/FileSystem.h"
 #include "llvm/Support/FormatVariadic.h"
 #include "llvm/Support/Program.h"
 
 namespace exegesis {
 
-SnippetGeneratorFailure::SnippetGeneratorFailure(const llvm::Twine &S)
-    : llvm::StringError(S, llvm::inconvertibleErrorCode()) {}
-
-SnippetGenerator::SnippetGenerator(const LLVMState &State) : State(State) {}
-
-SnippetGenerator::~SnippetGenerator() = default;
-
-llvm::Expected<std::vector<BenchmarkCode>>
-SnippetGenerator::generateConfigurations(const Instruction &Instr) const {
-  if (auto E = generateCodeTemplate(Instr)) {
-    CodeTemplate &CT = E.get();
-    const auto &RATC = State.getRATC();
-    const llvm::BitVector &ForbiddenRegs =
-        CT.ScratchSpacePointerInReg
-            ? RATC.getRegister(CT.ScratchSpacePointerInReg).aliasedBits()
-            : RATC.emptyRegisters();
-    std::vector<BenchmarkCode> Output;
-    // TODO: Generate as many BenchmarkCode as needed.
-    {
-      BenchmarkCode BC;
-      BC.Info = CT.Info;
-      for (InstructionTemplate &IT : CT.Instructions) {
-        randomizeUnsetVariables(ForbiddenRegs, IT);
-        BC.Instructions.push_back(IT.build());
-      }
-      if (CT.ScratchSpacePointerInReg)
-        BC.LiveIns.push_back(CT.ScratchSpacePointerInReg);
-      BC.RegisterInitialValues = computeRegisterInitialValues(CT.Instructions);
-      Output.push_back(std::move(BC));
-    }
-    return Output;
-  } else
-    return E.takeError();
-}
-
-std::vector<RegisterValue> SnippetGenerator::computeRegisterInitialValues(
-    const std::vector<InstructionTemplate> &Instructions) const {
+std::vector<RegisterValue> computeRegisterInitialValues(
+    const RegisterAliasingTrackerCache &RATC,
+    const std::vector<InstructionTemplate> &Instructions) {
   // Collect all register uses and create an assignment for each of them.
   // Ignore memory operands which are handled separately.
   // Loop invariant: DefinedRegs[i] is true iif it has been set at least once
   // before the current instruction.
-  llvm::BitVector DefinedRegs = State.getRATC().emptyRegisters();
+  llvm::BitVector DefinedRegs = RATC.emptyRegisters();
   std::vector<RegisterValue> RIV;
   for (const InstructionTemplate &IT : Instructions) {
     // Returns the register that this Operand sets or uses, or 0 if this is not
     // a register.
     const auto GetOpReg = [&IT](const Operand &Op) -> unsigned {
       if (Op.isMemory())
         return 0;
       if (Op.isImplicitReg())
for (const Operand &Op : IT.Instr.Operands) {
         if (Reg > 0)
           DefinedRegs.set(Reg);
       }
     }
   }
   return RIV;
 }
 
-llvm::Expected<CodeTemplate> SnippetGenerator::generateSelfAliasingCodeTemplate(
-    const Instruction &Instr) const {
+std::vector<BenchmarkCode>
+generateConfigurations(const RegisterAliasingTrackerCache &RATC,
+                       CodeTemplate &CT) {
+  const llvm::BitVector &ForbiddenRegs =
+      CT.ScratchSpacePointerInReg
+          ? RATC.getRegister(CT.ScratchSpacePointerInReg).aliasedBits()
+          : RATC.emptyRegisters();
+  std::vector<BenchmarkCode> Output;
+  // TODO: Generate as many BenchmarkCode as needed.
+  {
+    BenchmarkCode BC;
+    BC.Info = CT.Info;
+    for (InstructionTemplate &IT : CT.Instructions) {
+      randomizeUnsetVariables(ForbiddenRegs, IT);
+      BC.Instructions.push_back(IT.build());
+    }
+    if (CT.ScratchSpacePointerInReg)
+      BC.LiveIns.push_back(CT.ScratchSpacePointerInReg);
+    BC.RegisterInitialValues =
+        computeRegisterInitialValues(RATC, CT.Instructions);
+    Output.push_back(std::move(BC));
+  }
+  return Output;
+}
+
+llvm::Expected<CodeTemplate>
+generateSelfAliasingCodeTemplate(const Instruction &Instr) {
   const AliasingConfigurations SelfAliasing(Instr, Instr);
   if (SelfAliasing.empty()) {
     return llvm::make_error<SnippetGeneratorFailure>("empty self aliasing");
   }
   CodeTemplate CT;
   InstructionTemplate IT(Instr);
   if (SelfAliasing.hasImplicitAliasing()) {
     CT.Info = "implicit Self cycles, picking random values.";
   } else {
     CT.Info = "explicit self cycles, selecting one aliasing Conf.";
     // This is a self aliasing instruction so defs and uses are from the same
     // instance, hence twice IT in the following call.
     setRandomAliasing(SelfAliasing, IT, IT);
   }
   CT.Instructions.push_back(std::move(IT));
   return std::move(CT);
 }
 
 llvm::Expected<CodeTemplate>
-SnippetGenerator::generateUnconstrainedCodeTemplate(const Instruction &Instr,
-                                                    llvm::StringRef Msg) const {
+generateUnconstrainedCodeTemplate(const Instruction &Instr,
+                                  llvm::StringRef Msg) {
   CodeTemplate CT;
   CT.Info = llvm::formatv("{0}, repeating an unconstrained assignment", Msg);
   CT.Instructions.emplace_back(Instr);
   return std::move(CT);
 }
 
+SnippetGeneratorFailure::SnippetGeneratorFailure(const llvm::Twine &S)
+    : llvm::StringError(S, llvm::inconvertibleErrorCode()) {}
+
+SnippetGenerator::~SnippetGenerator() = default;
+
 std::mt19937 &randomGenerator() {
   static std::random_device RandomDevice;
   static std::mt19937 RandomGenerator(RandomDevice());
   return RandomGenerator;
 }
 
 static size_t randomIndex(size_t Size) {
   assert(Size > 0);

tools/llvm-exegesis/lib/Uops.h

 
 #include "BenchmarkRunner.h"
 #include "SnippetGenerator.h"
 
 namespace exegesis {
 
 class UopsSnippetGenerator : public SnippetGenerator {
 public:
-  UopsSnippetGenerator(const LLVMState &State) : SnippetGenerator(State) {}
+  UopsSnippetGenerator(const LLVMState &State) : State(State) {}
   ~UopsSnippetGenerator() override;
 
   llvm::Expected<CodeTemplate>
   generateCodeTemplate(const Instruction &Instr) const override;
 
   static constexpr const size_t kMinNumDifferentAddresses = 6;
 
 private:
+  const LLVMState &State;
   // Instantiates memory operands within a snippet.
   // To make computations as parallel as possible, we generate independant
   // memory locations for instructions that load and store. If there are less
   // than kMinNumDifferentAddresses in the original snippet, we duplicate
   // instructions until there are this number of instructions.
   // For example, assuming kMinNumDifferentAddresses=5 and
   // getMaxMemoryAccessSize()=64, if the original snippet is:
   //   mov eax, [memory]

tools/llvm-exegesis/lib/X86/Target.cpp

 #include "X86Subtarget.h"
 #include "llvm/MC/MCInstBuilder.h"
 
 namespace exegesis {
 
 namespace {
 
 // Common code for X86 Uops and Latency runners.
-template <typename Impl> class X86SnippetGenerator : public Impl {
-  using Impl::Impl;
+template <typename Policy>
+class X86SnippetGenerator : public SnippetGenerator, private Policy {
+public:
+  X86SnippetGenerator(const LLVMState &State)
+      : Delegate(Policy::Create(State)) {}
 
   llvm::Expected<CodeTemplate>
   generateCodeTemplate(const Instruction &Instr) const override {
     // Test whether we can generate a snippet for this instruction.
     const auto OpcodeName = Instr.Name;
     if (OpcodeName.startswith("POPF") || OpcodeName.startswith("PUSHF") ||
-        OpcodeName.startswith("ADJCALLSTACK")) {
+        OpcodeName.startswith("ADJCALLSTACK"))
       return llvm::make_error<BenchmarkFailure>(
           "Unsupported opcode: Push/Pop/AdjCallStack");
-    }
 
     // Handle X87.
     const unsigned FPInstClass =
         Instr.Description->TSFlags & llvm::X86II::FPTypeMask;
     switch (FPInstClass) {
     case llvm::X86II::NotFP:
       break;
     case llvm::X86II::ZeroArgFP:
       return llvm::make_error<BenchmarkFailure>("Unsupported x87 ZeroArgFP");
     case llvm::X86II::OneArgFP:
       return llvm::make_error<BenchmarkFailure>("Unsupported x87 OneArgFP");
     case llvm::X86II::OneArgFPRW:
     case llvm::X86II::TwoArgFP: {
       // These are instructions like
       //   - `ST(0) = fsqrt(ST(0))` (OneArgFPRW)
       //   - `ST(0) = ST(0) + ST(i)` (TwoArgFP)
       // They are intrinsically serial and do not modify the state of the stack.
       // We generate the same code for latency and uops.
-      return this->generateSelfAliasingCodeTemplate(Instr);
+      return generateSelfAliasingCodeTemplate(Instr);
     }
     case llvm::X86II::CompareFP:
-      return Impl::handleCompareFP(Instr);
+      return Policy::handleCompareFP(Instr);
     case llvm::X86II::CondMovFP:
-      return Impl::handleCondMovFP(Instr);
+      return Policy::handleCondMovFP(Instr);
     case llvm::X86II::SpecialFP:
       return llvm::make_error<BenchmarkFailure>("Unsupported x87 SpecialFP");
     default:
       llvm_unreachable("Unknown FP Type!");
     }
 
     // Fallback to generic implementation.
-    return Impl::Base::generateCodeTemplate(Instr);
+    return Delegate->generateCodeTemplate(Instr);
   }
+
+private:
+  std::unique_ptr<SnippetGenerator> Delegate;
 };
 
-class X86LatencyImpl : public LatencySnippetGenerator {
+class X86LatencyPolicy {
 protected:
-  using Base = LatencySnippetGenerator;
-  using Base::Base;
+  static SnippetGenerator *Create(const LLVMState &State) {
+    return new LatencySnippetGenerator(State);
+  }
   llvm::Expected<CodeTemplate> handleCompareFP(const Instruction &Instr) const {
     return llvm::make_error<SnippetGeneratorFailure>(
         "Unsupported x87 CompareFP");
   }
   llvm::Expected<CodeTemplate> handleCondMovFP(const Instruction &Instr) const {
     return llvm::make_error<SnippetGeneratorFailure>(
         "Unsupported x87 CondMovFP");
   }
 };
 
-class X86UopsImpl : public UopsSnippetGenerator {
+class X86UopsPolicy {
 protected:
-  using Base = UopsSnippetGenerator;
-  using Base::Base;
+  static SnippetGenerator *Create(const LLVMState &State) {
+    return new UopsSnippetGenerator(State);
+  }
   // We can compute uops for any FP instruction that does not grow or shrink the
   // stack (either do not touch the stack or push as much as they pop).
   llvm::Expected<CodeTemplate> handleCompareFP(const Instruction &Instr) const {
     return generateUnconstrainedCodeTemplate(
         Instr, "instruction does not grow/shrink the FP stack");
   }
   llvm::Expected<CodeTemplate> handleCondMovFP(const Instruction &Instr) const {
     return generateUnconstrainedCodeTemplate(
std::vector<llvm::MCInst> setRegTo(const llvm::MCSubtargetInfo &STI,
     }
     if (Reg == llvm::X86::EFLAGS)
       return CI.popFlagAndFinalize();
     return {}; // Not yet implemented.
   }
 
   std::unique_ptr<SnippetGenerator>
   createLatencySnippetGenerator(const LLVMState &State) const override {
-    return llvm::make_unique<X86SnippetGenerator<X86LatencyImpl>>(State);
+    return llvm::make_unique<X86SnippetGenerator<X86LatencyPolicy>>(State);
   }
 
   std::unique_ptr<SnippetGenerator>
   createUopsSnippetGenerator(const LLVMState &State) const override {
-    return llvm::make_unique<X86SnippetGenerator<X86UopsImpl>>(State);
+    return llvm::make_unique<X86SnippetGenerator<X86UopsPolicy>>(State);
   }
 
   bool matchesArch(llvm::Triple::ArchType Arch) const override {
     return Arch == llvm::Triple::x86_64 || Arch == llvm::Triple::x86;
   }
 };
 
 } // namespace

tools/llvm-exegesis/llvm-exegesis.cpp

generateSnippets(const LLVMState &State, unsigned Opcode) {
   if (InstrDesc.isCall() || InstrDesc.isReturn())
     return llvm::make_error<BenchmarkFailure>(
         "Unsupported opcode: isCall/isReturn");
 
   const std::unique_ptr<SnippetGenerator> Generator =
       State.getExegesisTarget().createSnippetGenerator(BenchmarkMode, State);
   if (!Generator)
     llvm::report_fatal_error("cannot create snippet generator");
-  return Generator->generateConfigurations(Instr);
+  if (auto E = Generator->generateCodeTemplate(Instr))
+    return generateConfigurations(State.getRATC(), E.get());
+  else
+    return E.takeError();
 }
 
 namespace {
 
 // An MCStreamer that reads a BenchmarkCode definition from a file.
 // The BenchmarkCode definition is just an asm file, with additional comments to
 // specify which registers should be defined or are live on entry.
 class BenchmarkCodeStreamer : public llvm::MCStreamer,

unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp

TEST_F(UopsSnippetGeneratorTest, MemoryUse_Movsb) {
   const Instruction Instr(State, Opcode);
   auto Error = Generator.generateCodeTemplate(Instr).takeError();
   EXPECT_TRUE((bool)Error);
   llvm::consumeError(std::move(Error));
 }
 
 class FakeSnippetGenerator : public SnippetGenerator {
 public:
-  FakeSnippetGenerator(const LLVMState &State) : SnippetGenerator(State) {}
+  FakeSnippetGenerator(const LLVMState &State) : State(State) {}
 
   Instruction createInstruction(unsigned Opcode) {
     return Instruction(State, Opcode);
   }
 
 private:
+  const LLVMState &State;
+
   llvm::Expected<CodeTemplate>
   generateCodeTemplate(const Instruction &Instr) const override {
     return llvm::make_error<llvm::StringError>("not implemented",
                                                llvm::inconvertibleErrorCode());
   }
 };
 
 using FakeSnippetGeneratorTest = SnippetGeneratorTest<FakeSnippetGenerator>;
TEST_F(FakeSnippetGeneratorTest, ComputeRegisterInitialValuesAdd16ri) {
   // explicit use 1       : reg RegClass=GR16 | TIED_TO:0
   // explicit use 2       : imm
   // implicit def         : EFLAGS
   InstructionTemplate IT(Generator.createInstruction(llvm::X86::ADD16ri));
   IT.getValueFor(IT.Instr.Variables[0]) =
       llvm::MCOperand::createReg(llvm::X86::AX);
   std::vector<InstructionTemplate> Snippet;
   Snippet.push_back(std::move(IT));
-  const auto RIV = Generator.computeRegisterInitialValues(Snippet);
+  const auto RIV = computeRegisterInitialValues(State.getRATC(), Snippet);
   EXPECT_THAT(RIV, ElementsAre(IsRegisterValue(llvm::X86::AX, llvm::APInt())));
 }
 
 TEST_F(FakeSnippetGeneratorTest, ComputeRegisterInitialValuesAdd64rr) {
   // ADD64rr:
   //  mov64ri rax, 42
   //  add64rr rax, rax, rbx
   // -> only rbx needs defining.
std::vector<InstructionTemplate> Snippet;
     InstructionTemplate Add(Generator.createInstruction(llvm::X86::ADD64rr));
     Add.getValueFor(Add.Instr.Variables[0]) =
         llvm::MCOperand::createReg(llvm::X86::RAX);
     Add.getValueFor(Add.Instr.Variables[1]) =
         llvm::MCOperand::createReg(llvm::X86::RBX);
     Snippet.push_back(std::move(Add));
   }
 
-  const auto RIV = Generator.computeRegisterInitialValues(Snippet);
+  const auto RIV = computeRegisterInitialValues(State.getRATC(), Snippet);
   EXPECT_THAT(RIV, ElementsAre(IsRegisterValue(llvm::X86::RBX, llvm::APInt())));
 }
 
 } // namespace
 } // namespace exegesis