[llvm-exegesis] Fix invalid return type and add a Dump function.

[courbet]

tools/llvm-exegesis/lib/MCInstrDescView.h

122

dump

[gchatelet]

• Fix function case.

tools/llvm-exegesis/lib/MCInstrDescView.h

 // registers and the registers reachable from them (aliasing registers).
 // - Info: a shortcut for MCInstrDesc::operands()[Index].
 // - TiedToIndex: the index of the Operand holding the value or -1.
 // - ImplicitReg: a pointer to the register value when Operand is Implicit,
 // nullptr otherwise.
 // - VariableIndex: the index of the Variable holding the value for this Operand
 // or -1 if this operand is implicit.
 struct Operand {
-  bool getIndex() const;
   bool isExplicit() const;
   bool isImplicit() const;
   bool isImplicitReg() const;
   bool isDef() const;
   bool isUse() const;
   bool isReg() const;
   bool isTied() const;
   bool isVariable() const;
   bool isMemory() const;
   bool isImmediate() const;
-  int getTiedToIndex() const;
-  int getVariableIndex() const;
+  unsigned getIndex() const;
+  unsigned getTiedToIndex() const;
+  unsigned getVariableIndex() const;
   unsigned getImplicitReg() const;
   const RegisterAliasingTracker &getRegisterAliasing() const;
   const llvm::MCOperandInfo &getExplicitOperandInfo() const;
 
   // Please use the accessors above and not the following fields.
   unsigned Index = 0;
   bool IsDef = false;
   const RegisterAliasingTracker *Tracker = nullptr; // Set for Register Op.
struct Instruction {
   bool hasTiedRegisters() const;
 
   // Whether this instruction is self aliasing through some registers.
   // Repeating this instruction may execute sequentially by picking aliasing
   // Use and Def registers. It may also execute in parallel by picking non
   // aliasing Use and Def registers.
   bool hasAliasingRegisters() const;
 
+  // Convenient function to help with debugging.
+  void dump(const llvm::MCRegisterInfo &RegInfo,
+            llvm::raw_ostream &Stream) const;
+
   const llvm::MCInstrDesc *Description; // Never nullptr.
   llvm::SmallVector<Operand, 8> Operands;
   llvm::SmallVector<Variable, 4> Variables;
   llvm::BitVector ImplDefRegs; // The set of aliased implicit def registers.
   llvm::BitVector ImplUseRegs; // The set of aliased implicit use registers.
   llvm::BitVector AllDefRegs;  // The set of all aliased def registers.
   llvm::BitVector AllUseRegs;  // The set of all aliased use registers.
 };

tools/llvm-exegesis/lib/MCInstrDescView.cpp

 
 unsigned Variable::getPrimaryOperandIndex() const {
   assert(!TiedOperands.empty());
   return TiedOperands[0];
 }
 
 bool Variable::hasTiedOperands() const { return TiedOperands.size() > 1; }
 
-bool Operand::getIndex() const { return Index; }
+unsigned Operand::getIndex() const {
+  assert(Index >= 0 && "Index must be set");
+  return Index;
+}
 
 bool Operand::isExplicit() const { return Info; }
 
 bool Operand::isImplicit() const { return !Info; }
 
 bool Operand::isImplicitReg() const { return ImplicitReg; }
 
 bool Operand::isDef() const { return IsDef; }
return isExplicit() &&
          getExplicitOperandInfo().OperandType == llvm::MCOI::OPERAND_MEMORY;
 }
 
 bool Operand::isImmediate() const {
   return isExplicit() &&
          getExplicitOperandInfo().OperandType == llvm::MCOI::OPERAND_IMMEDIATE;
 }
 
-int Operand::getTiedToIndex() const {
-  assert(isTied());
+unsigned Operand::getTiedToIndex() const {
+  assert(isTied() && "Operand must be tied to get the tied index");
+  assert(TiedToIndex >= 0 && "TiedToIndex must be set");
   return TiedToIndex;
 }
 
-int Operand::getVariableIndex() const {
-  assert(isVariable());
+unsigned Operand::getVariableIndex() const {
+  assert(isVariable() && "Operand must be variable to get the Variable index");
+  assert(VariableIndex >= 0 && "VariableIndex must be set");
   return VariableIndex;
 }
 
 unsigned Operand::getImplicitReg() const {
   assert(ImplicitReg);
   return *ImplicitReg;
 }
 
bool Instruction::hasTiedRegisters() const {
   return llvm::any_of(
       Variables, [](const Variable &Var) { return Var.hasTiedOperands(); });
 }
 
 bool Instruction::hasAliasingRegisters() const {
   return AllDefRegs.anyCommon(AllUseRegs);
 }
 
+void Instruction::dump(const llvm::MCRegisterInfo &RegInfo,
+                       llvm::raw_ostream &Stream) const {
+  for (const auto &Op : Operands) {
+    Stream << "- Op" << Op.getIndex();
+    if (Op.isExplicit())
+      Stream << " Explicit";
+    if (Op.isImplicit())
+      Stream << " Implicit";
+    if (Op.isUse())
+      Stream << " Use";
+    if (Op.isDef())
+      Stream << " Def";
+    if (Op.isImmediate())
+      Stream << " Immediate";
+    if (Op.isMemory())
+      Stream << " Memory";
+    if (Op.isReg()) {
+      if (Op.isImplicitReg())
+        Stream << " Reg(" << RegInfo.getName(Op.getImplicitReg()) << ")";
+      else
+        Stream << " RegClass("
+               << RegInfo.getRegClassName(
+                      &RegInfo.getRegClass(Op.Info->RegClass))
+               << ")";
+    }
+    if (Op.isTied())
+      Stream << " TiedToOp" << Op.getTiedToIndex();
+    Stream << "\n";
+  }
+  for (const auto &Var : Variables) {
+    Stream << "- Var" << Var.getIndex();
+    for (auto OperandIndex : Var.TiedOperands)
+      Stream << " Op" << OperandIndex;
+    Stream << "\n";
+  }
+  if (hasMemoryOperands())
+    Stream << "- hasMemoryOperands\n";
+  if (hasAliasingImplicitRegisters())
+    Stream << "- hasAliasingImplicitRegisters (execution is always serial)\n";
+  if (hasTiedRegisters())
+    Stream << "- hasTiedRegisters (execution is always serial)\n";
+  if (hasAliasingRegisters())
+    Stream << "- hasAliasingRegisters\n";
+}
+
 bool RegisterOperandAssignment::
 operator==(const RegisterOperandAssignment &Other) const {
   return std::tie(Op, Reg) == std::tie(Other.Op, Other.Reg);
 }
 
 bool AliasingRegisterOperands::
 operator==(const AliasingRegisterOperands &Other) const {
   return std::tie(Defs, Uses) == std::tie(Other.Defs, Other.Uses);