AMDGPU/GlobalISel: Add support for G_INTTOPTR

[tstellar]

Summary

This is a no-op.

[arsenm]

LGTM

llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

if (!isPreISelGenericOpcode(I.getOpcode())) {
     return true;
   }
 
   switch (I.getOpcode()) {
   default:
     return selectImpl(I, CoverageInfo);
   case TargetOpcode::G_ADD:
     return selectG_ADD(I);
+  case TargetOpcode::G_INTTOPTR:
   case TargetOpcode::G_BITCAST:
     return selectCOPY(I);
   case TargetOpcode::G_CONSTANT:
   case TargetOpcode::G_FCONSTANT:
     return selectG_CONSTANT(I);
   case TargetOpcode::G_GEP:
     return selectG_GEP(I);
   case TargetOpcode::G_IMPLICIT_DEF:

llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

for (LLT PtrTy : AddrSpaces) {
     LLT IdxTy = LLT::scalar(PtrTy.getSizeInBits());
     setAction({G_GEP, PtrTy}, Legal);
     setAction({G_GEP, 1, IdxTy}, Legal);
   }
 
   setAction({G_ICMP, S1}, Legal);
   setAction({G_ICMP, 1, S32}, Legal);
 
+  getActionDefinitionsBuilder(G_INTTOPTR)
+    .legalIf([](const LegalityQuery &Query) {
+      return true;
+    });
 
   getActionDefinitionsBuilder({G_LOAD, G_STORE})
     .legalIf([=, &ST](const LegalityQuery &Query) {
         const LLT &Ty0 = Query.Types[0];
 
         // TODO: Decompose private loads into 4-byte components.
         // TODO: Illegal flat loads on SI
         switch (Ty0.getSizeInBits()) {

llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

case AMDGPU::G_MERGE_VALUES: {
     unsigned SrcSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
 
     OpdsMapping[0] = AMDGPU::getValueMapping(Bank, DstSize);
     // Op1 and Dst should use the same register bank.
     for (unsigned i = 1, e = MI.getNumOperands(); i != e; ++i)
       OpdsMapping[i] = AMDGPU::getValueMapping(Bank, SrcSize);
     break;
   }
+  case AMDGPU::G_INTTOPTR:
   case AMDGPU::G_BITCAST: {
     unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
     unsigned BankID = getRegBankID(MI.getOperand(1).getReg(), MRI, *TRI);
     OpdsMapping[0] = OpdsMapping[1] = AMDGPU::getValueMapping(BankID, Size);
     break;
   }
   case AMDGPU::G_TRUNC: {
     unsigned Dst = MI.getOperand(0).getReg();

llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-inttoptr.mir

+# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN
+
+--- |
+  define amdgpu_kernel void @inttoptr(i32 addrspace(4)* %const0, i32 addrspace(0)* %flat0) {ret void}
+...
+---
+
+name:            inttoptr
+legalized:       true
+regBankSelected: true
+
+# GCN-LABEL: name: inttoptr
+# GCN: [[S64:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
+# GCN: [[V64:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+# FIXME: This extra copy is unnecessary, but is it the instruction selector's
+# job to clean this up?
+# GCN: [[S64_COPY:%[0-9]+]]:sreg_64 = COPY [[S64]]
+# GCN: [[VAL:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM [[S64_COPY]], 0, 0
+# GCN: [[V_VAL:%[0-9]+]]:vgpr_32 = COPY [[VAL]]
+# GCN: FLAT_STORE_DWORD [[V64]], [[V_VAL]]
+#
+
+body: |
+  bb.0:
+    liveins: $sgpr0_sgpr1, $vgpr0_vgpr1
+    %0:sgpr(s64) = COPY $sgpr0_sgpr1
+    %1:vgpr(s64) = COPY $vgpr0_vgpr1
+    %2:sgpr(p4) = G_INTTOPTR %0
+    %3:sgpr(s32) = G_LOAD %2 :: (load 4 from %ir.const0)
+    %4:vgpr(p0) = G_INTTOPTR %1
+    %5:vgpr(s32) = COPY %3
+    G_STORE %5, %4 :: (store 4 into %ir.flat0)
+...
+---

llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-inttoptr.mir

+# RUN: llc -march=amdgcn -run-pass=legalizer %s -o - | FileCheck %s
+
+---
+name: test_inttoptr
+body: |
+  bb.0:
+    liveins: $sgpr0_sgpr1, $sgpr2, $vgpr0_vgpr1, $vgpr2
+
+    ; CHECK-LABEL: name: test_inttoptr
+    ; CHECK: [[S64:%[0-9]+]]:_(s64) = COPY $sgpr0_sgpr1
+    ; CHECK: [[S32:%[0-9]+]]:_(s32) = COPY $sgpr2
+    ; CHECK: [[V64:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
+    ; CHECK: [[V32:%[0-9]+]]:_(s32) = COPY $vgpr2
+    ; CHECK: (p0) = G_INTTOPTR [[V64]]
+    ; CHECK: (p1) = G_INTTOPTR [[V64]]
+    ; CHECK: (p3) = G_INTTOPTR [[V32]]
+    ; CHECK: (p4) = G_INTTOPTR [[S64]]
+    ; CHECK: (p5) = G_INTTOPTR [[S32]]
+    %0:_(s64) = COPY $sgpr0_sgpr1
+    %1:_(s32) = COPY $sgpr2
+    %2:_(s64) = COPY $vgpr0_vgpr1
+    %3:_(s32) = COPY $vgpr2
+    %4:_(p0) = G_INTTOPTR %2
+    %5:_(p1) = G_INTTOPTR %2
+    %6:_(p3) = G_INTTOPTR %3
+    %7:_(p4) = G_INTTOPTR %0
+    %8:_(p5) = G_INTTOPTR %1
+    S_ENDPGM implicit %4, implicit %5, implicit %6, implicit %7, implicit %8
+...

llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-inttoptr.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=amdgcn -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
+# RUN: llc -march=amdgcn -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
+
+---
+name: inttoptr_s
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0_sgpr1
+    ; CHECK-LABEL: name: inttoptr_s
+    ; CHECK: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
+    ; CHECK: [[INTTOPTR:%[0-9]+]]:sgpr(p4) = G_INTTOPTR [[COPY]](s64)
+    %0:_(s64) = COPY $sgpr0_sgpr1
+    %1:_(p4) = G_INTTOPTR %0
+...
+
+---
+name: inttoptr_v
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0_vgpr1
+    ; CHECK-LABEL: name: inttoptr_v
+    ; CHECK: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
+    ; CHECK: [[INTTOPTR:%[0-9]+]]:vgpr(p0) = G_INTTOPTR [[COPY]](s64)
+    %0:_(s64) = COPY $vgpr0_vgpr1
+    %1:_(p0) = G_INTTOPTR %0
+...