This is an archive of the discontinued LLVM Phabricator instance.

[AMDGPU] Assert in getOpSize() there are no sub-dword subregs
ClosedPublic

Authored by rampitec on Oct 1 2018, 10:41 PM.

Download Raw Diff

Details

Reviewers

Commits

rG1821513e2f9c: [AMDGPU] Assert in getOpSize() there are no sub-dword subregs
rL343648: [AMDGPU] Assert in getOpSize() there are no sub-dword subregs

Diff Detail

Event Timeline

rampitec created this revision.Oct 1 2018, 10:41 PM

Herald added subscribers: t-tye, tpr, dstuttard and 5 others. · View Herald TranscriptOct 1 2018, 10:41 PM

LGTM

This revision is now accepted and ready to land.Oct 2 2018, 4:57 PM

Closed by commit rL343648: [AMDGPU] Assert in getOpSize() there are no sub-dword subregs (authored by rampitec). · Explain WhyOct 2 2018, 5:02 PM

This revision was automatically updated to reflect the committed changes.

Revision Contents

Path

Size

lib/

Target/

AMDGPU/

SIInstrInfo.h

7 lines

Diff 167883

lib/Target/AMDGPU/SIInstrInfo.h

Show First 20 Lines • Show All 726 Lines • ▼ Show 20 Lines	unsigned getOpSize(uint16_t Opcode, unsigned OpNo) const {
return RI.getRegSizeInBits(*RI.getRegClass(OpInfo.RegClass)) / 8;		return RI.getRegSizeInBits(*RI.getRegClass(OpInfo.RegClass)) / 8;
}		}

/// This form should usually be preferred since it handles operands		/// This form should usually be preferred since it handles operands
/// with unknown register classes.		/// with unknown register classes.
unsigned getOpSize(const MachineInstr &MI, unsigned OpNo) const {		unsigned getOpSize(const MachineInstr &MI, unsigned OpNo) const {
const MachineOperand &MO = MI.getOperand(OpNo);		const MachineOperand &MO = MI.getOperand(OpNo);
if (MO.isReg()) {		if (MO.isReg()) {
if (unsigned SubReg = MO.getSubReg())		if (unsigned SubReg = MO.getSubReg()) {
		assert(RI.getRegSizeInBits(*RI.getSubClassWithSubReg(
		MI.getParent()->getParent()->getRegInfo().
		getRegClass(MO.getReg()), SubReg)) >= 32 &&
		"Sub-dword subregs are not supported");
return RI.getSubRegIndexLaneMask(SubReg).getNumLanes() * 4;		return RI.getSubRegIndexLaneMask(SubReg).getNumLanes() * 4;
}		}
		}
return RI.getRegSizeInBits(*getOpRegClass(MI, OpNo)) / 8;		return RI.getRegSizeInBits(*getOpRegClass(MI, OpNo)) / 8;
}		}

/// \returns true if it is legal for the operand at index \p OpNo		/// \returns true if it is legal for the operand at index \p OpNo
/// to read a VGPR.		/// to read a VGPR.
bool canReadVGPR(const MachineInstr &MI, unsigned OpNo) const;		bool canReadVGPR(const MachineInstr &MI, unsigned OpNo) const;

/// Legalize the \p OpIndex operand of this instruction by inserting		/// Legalize the \p OpIndex operand of this instruction by inserting
▲ Show 20 Lines • Show All 231 Lines • Show Last 20 Lines