[AMDGPU] Assert in getOpSize() there are no sub-dword subregs

[arsenm]

LGTM

llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.h

unsigned getOpSize(uint16_t Opcode, unsigned OpNo) const {
     return RI.getRegSizeInBits(*RI.getRegClass(OpInfo.RegClass)) / 8;
   }
 
   /// This form should usually be preferred since it handles operands
   /// with unknown register classes.
   unsigned getOpSize(const MachineInstr &MI, unsigned OpNo) const {
     const MachineOperand &MO = MI.getOperand(OpNo);
     if (MO.isReg()) {
-      if (unsigned SubReg = MO.getSubReg())
+      if (unsigned SubReg = MO.getSubReg()) {
+        assert(RI.getRegSizeInBits(*RI.getSubClassWithSubReg(
+                                   MI.getParent()->getParent()->getRegInfo().
+                                     getRegClass(MO.getReg()), SubReg)) >= 32 &&
+               "Sub-dword subregs are not supported");
         return RI.getSubRegIndexLaneMask(SubReg).getNumLanes() * 4;
       }
+    }
     return RI.getRegSizeInBits(*getOpRegClass(MI, OpNo)) / 8;
   }
 
   /// \returns true if it is legal for the operand at index \p OpNo
   /// to read a VGPR.
   bool canReadVGPR(const MachineInstr &MI, unsigned OpNo) const;
 
   /// Legalize the \p OpIndex operand of this instruction by inserting