DAGCombiner: StoreMerging: Fix bad index calculating when adjusting mismatching vector types

[MatzeB]

Summary

This fixes a wrong index calculation when merging mismatching
vector types. This simplifies the code to just use the existing
extract_{subvector|element} and a bitcast instead of bitcasting the vector
before the extract_xxx first and creating a new extract_xxx with adjusted
index after.

rdar://44584718

[niravd]

LGTM.

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

if (IsConstantSrc) {
         // type MemVT. If the underlying value is not the correct
         // type, but it is an extraction of an appropriate vector we
         // can recast Val to be of the correct type. This may require
         // converting between EXTRACT_VECTOR_ELT and
         // EXTRACT_SUBVECTOR.
         if ((MemVT != Val.getValueType()) &&
             (Val.getOpcode() == ISD::EXTRACT_VECTOR_ELT ||
              Val.getOpcode() == ISD::EXTRACT_SUBVECTOR)) {
-          SDValue Vec = Val.getOperand(0);
           EVT MemVTScalarTy = MemVT.getScalarType();
-          SDValue Idx = Val.getOperand(1);
           // We may need to add a bitcast here to get types to line up.
-          if (MemVTScalarTy != Vec.getValueType()) {
-            unsigned Elts = Vec.getValueType().getSizeInBits() /
-                            MemVTScalarTy.getSizeInBits();
-            if (Val.getValueType().isVector() && MemVT.isVector()) {
-              unsigned IdxC = cast<ConstantSDNode>(Idx)->getZExtValue();
-              unsigned NewIdx =
-                  ((uint64_t)IdxC * MemVT.getVectorNumElements()) / Elts;
-              Idx = DAG.getConstant(NewIdx, SDLoc(Val), Idx.getValueType());
-            }
-            EVT NewVecTy =
-                EVT::getVectorVT(*DAG.getContext(), MemVTScalarTy, Elts);
-            Vec = DAG.getBitcast(NewVecTy, Vec);
-          }
-          auto OpC = (MemVT.isVector()) ? ISD::EXTRACT_SUBVECTOR
+          if (MemVTScalarTy != Val.getValueType().getScalarType()) {
+            Val = DAG.getBitcast(MemVT, Val);
+          } else {
+            unsigned OpC = MemVT.isVector() ? ISD::EXTRACT_SUBVECTOR
                                             : ISD::EXTRACT_VECTOR_ELT;
+            SDValue Vec = Val.getOperand(0);
+            SDValue Idx = Val.getOperand(1);
             Val = DAG.getNode(OpC, SDLoc(Val), MemVT, Vec, Idx);
           }
+        }
         Ops.push_back(Val);
       }
 
       // Build the extracted vector elements back into a vector.
       StoredVal = DAG.getNode(MemVT.isVector() ? ISD::CONCAT_VECTORS
                                                : ISD::BUILD_VECTOR,
                               DL, StoreTy, Ops);
     }

test/CodeGen/AArch64/sdag-store-merging-bug.ll

+; RUN: llc -o - %s -mtriple aarch64-- -mattr +slow-misaligned-128store -stop-after=isel | FileCheck %s
+; Checks for a bug where selection dag store merging would construct wrong
+; indices when extracting values from vectors, resulting in an invalid
+; lane duplication in this case.
+; The only way I could trigger stores with mismatching types getting merged was
+; via the aarch64 slow-misaligned-128store code splitting stores earlier.
+
+; CHECK-LABEL: name: func
+; CHECK: LDRQui
+; CHECK-NOT: INSERT_SUBREG
+; CHECK-NOT: DUP
+; CHECK: STRQui
+define void @func(<2 x double>* %sptr, <2 x double>* %dptr) {
+  %load = load <2 x double>, <2 x double>* %sptr, align 8
+  ; aarch64 feature slow-misaligned-128store splits the following store.
+  ; store merging immediately merges it back together (but used to get the
+  ; merging wrong), this is the only way I was able to reproduce the bug...
+  store <2 x double> %load, <2 x double>* %dptr, align 4
+  ret void
+}