AMDGPU: Add Selection patterns to support add of one bit.

[cfang]

Summary

We generate s_xor to lower add of i1s in general cases, and s_not to lower add with a one-bit imm of -1 (true).

[rampitec]

LGTM

[arsenm]

Also needs to support/test sub. I’m also concerned it’s not this simple with i1 to use a scalar operation. This needs some tests stressing SIFixSGPRCopies, and with control flow

llvm/trunk/lib/Target/AMDGPU/SIInstructions.td

 >;
 
 def : GCNPat <
   (i1 (xor i1:$src0, i1:$src1)),
   (S_XOR_B64 $src0, $src1)
 >;
 
 def : GCNPat <
+  (i1 (add i1:$src0, i1:$src1)),
+  (S_XOR_B64 $src0, $src1)
+>;
+
+let AddedComplexity = 1 in {
+def : GCNPat <
+  (i1 (add i1:$src0, (i1 -1))),
+  (S_NOT_B64 $src0)
+>;
+}
+
+def : GCNPat <
   (f16 (sint_to_fp i1:$src)),
   (V_CVT_F16_F32_e32 (V_CNDMASK_B32_e64 (i32 0), (i32 CONST.FP32_NEG_ONE), $src))
 >;
 
 def : GCNPat <
   (f16 (uint_to_fp i1:$src)),
   (V_CVT_F16_F32_e32 (V_CNDMASK_B32_e64 (i32 0), (i32 CONST.FP32_ONE), $src))
 >;

llvm/trunk/test/CodeGen/AMDGPU/add_i1.ll

+; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
+
+
+; GCN-LABEL: {{^}}add_var_var_i1:
+; GCN: s_xor_b64
+define amdgpu_kernel void @add_var_var_i1(i1 addrspace(1)* %out, i1 addrspace(1)* %in0, i1 addrspace(1)* %in1) {
+  %a = load volatile i1, i1 addrspace(1)* %in0
+  %b = load volatile i1, i1 addrspace(1)* %in1
+  %add = add i1 %a, %b
+  store i1 %add, i1 addrspace(1)* %out
+  ret void
+}
+
+; GCN-LABEL: {{^}}add_var_imm_i1:
+; GCN: s_not_b64
+define amdgpu_kernel void @add_var_imm_i1(i1 addrspace(1)* %out, i1 addrspace(1)* %in) {
+  %a = load volatile i1, i1 addrspace(1)* %in
+  %add = add i1 %a, 1
+  store i1 %add, i1 addrspace(1)* %out
+  ret void
+}