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AMDGPU: Add Selection patterns to support add of one bit.
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Authored by cfang on Sep 25 2018, 1:26 PM.

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Summary

We generate s_xor to lower add of i1s in general cases, and s_not to lower add with a one-bit imm of -1 (true).

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rL LLVM

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cfang created this revision.Sep 25 2018, 1:26 PM
This revision is now accepted and ready to land.Sep 25 2018, 1:47 PM
This revision was automatically updated to reflect the committed changes.

Also needs to support/test sub. I’m also concerned it’s not this simple with i1 to use a scalar operation. This needs some tests stressing SIFixSGPRCopies, and with control flow