[Tablegen/RFC] Introduce Mask to limit generation of inferred register classes

[kariddi]

Summary

Hello,

this patch adds a mechanism to control the inferring of new register classes.

The main issue this is trying to solve is that when we have overlapping register classes and register tuples like in this example:

def SRegs : MyClass<16, [i16], (sequence "S%u", 0, 15)>;
def SRegslow : MyClass<16, [i16], (trunc SRegs, 5)>;
def SRegshigh : MyClass<16, [i16], (shl SRegs, 5)>;
def Stup3 : RegisterTuples<[ssub0, ssub1, ssub3], [

 (shl SRegs, 0),
 (shl SRegs, 1),
 (shl SRegs, 2)
]>;

def SRegs3 : MyClass<32, [untyped], (add Stup3)>;

Then tablegen tries to generate all the possible register classes definitions to answer to getMatchingSuperRegClass().
This includes classes like:
SRegs3_with_ssub1_in_SRegslow_and_SRegs3_with_ssub2_in_SRegshigh
or
SRegs3_with_ssub0_in_SRegslow_and_SRegs3_with_ssub2_in_SRegshigh

The more tuples you have and the more overlapping constraints you have the worse this can become.

This approach tries to give knob to use to stop tablegen to infer classes for certain register classes.
This knob consist in a mask (tentatively called a ClassMask) that partitions the register file in sections. If the masks of two register classes are disjoint we do not generate inferred classes out of them.

If we rewrote the above definitions for SReglow and SReghigh like this

def SRegslow : MyClass<16, [i16], (trunc SRegs, 5)>
{

let ClassMask = 1;

}
def SRegshigh : MyClass<16, [i16], (shl SRegs, 5)>
{

let ClassMask = 2;

}

Then the two masks for the two classes would be disjoint (0x1 and 0x2) and tablegen wouldn't generate inferred classes for the combinations of those two classes.

I have to admit that I'm not an expert in the generation of the register representations, so I'm not 100% sure this is the best approach, but this is a step in the direction of limiting the generation of inferred classes for this case.

This patch is also a kind of RFC in figuring out if there is a better solution for this issue when you have register tuples and you try to add constrained register classes.
I wonder if anybody else encountered a similar problem with their targets

[bjope]

I don't know the history behind the inferred classes, I thought they were generated because they might be needed :-)

To use this "knob" I guess I need to know which classes that are used by different instructions in my target, and which register classes that I might get copied between etc. And by using that knowledge I might know that the register coalescer and regalloc etc doesn't need constrain to certain inferred classes. And then I can use the knob to get rid of classes that I believe never is used. Is that a correct interpretation?

To understand a little bit more about what you are trying to achieve it would be nice with some more information about the problem with having those inferred classes.
Are they for example invalid or overlapping in some way (do you get several classes that contain exactly the same registers)?
Or do you hit some maximum limit regarding number of register classes?
Or are you afraid that it costs compile time to have many classes?
Or are you just annoyed that your generated <target>GenRegisterInfo.inc file is hard to read?

[arsenm]

The concept makes sense to me, but I don't see what the meaning of the values is / how you are supposed to compute them for the mask. Is it supposed to be one bit per regunit in the generated registers of the class?

[arsenm]

include/llvm/Target/Target.td

286

Typo paritioned

include/llvm/Target/Target.td

   // constrained classes first. The value has to be in the range [0,63].
   int AllocationPriority = 0;
 
+  // Defines a mask for limiting the construction of inferred register classes.
+  // The idea is that we don't want to infer classes of register tuples
+  // that span two classes with disjoint ClassMasks.
+  // For example if we have these classes:
+  //   def SRegs : MyClass<16, [i16], (sequence "S%u", 0, 15)>;
+  //   def STup2 : RegisterTuples<[ssub0, ssub1],
+  //                         [(shl SRegs, 0),
+  //                          (shl SRegs, 1)]>;
+  //   def SRegs2 : MyClass<32, [i32], (add Stup2)>;
+  //   def SRegslow : MyClass<16, [i16], (trunc SRegs, 5)>
+  //   def SRegshigh : MyClass<16, [i16], (shl SRegs, 5)>
+  // The main register file SReg is paritioned through additional constraints
+  // classes available with theSRegslow/high classes.
+  // We also have and also a tuple of registers SRegs2.
+  // Tablegen would normally create all the combinations of register classes
+  // for the query to getMatchingSuperRegClass() like:
+  //   SRegs2_with_ssub0_in_SRegslow_and_SRegs2_with_ssub1_in_SRegshighRegClass
+  // ... and so on.
+  // All these inferred register classes grow exponentially with the number
+  // of overlapping tuples that potentially cross the boundary of the low/high
+  // constraint classes.
+  // By defining the constraint classes as:
+  //   def SRegslow : MyClass<16, [i16], (trunc SRegs, 5)> {
+  //     let ClassMask = 1;
+  //   }
+  //   def SRegshigh : MyClass<16, [i16], (shl SRegs, 5)> {
+  //     let ClassMask = 2;
+  //   }
+  // where the masks are disjoint Tablegen will make sure to not infer any
+  // class of tuples crossing the boundary between the low and high constraint
+  // file.
+  bits<32> ClassMask = -1;
+
   // The diagnostic type to present when referencing this operand in a match
   // failure error message. If this is empty, the default Match_InvalidOperand
   // diagnostic type will be used. If this is "<name>", a Match_<name> enum

test/TableGen/ClassMask1.td

+// RUN: llvm-tblgen -gen-register-info -I %p/../../include %s -o - 2>&1 | FileCheck %s
+// Checks that classes disjoint through "ClassMask" do not generate extra inferred classes
+include "llvm/Target/Target.td"
+
+class MyReg<string n, list<Register> subregs = []>
+  : Register<n> {
+  let Namespace = "Test";
+  let SubRegs = subregs;
+  let CoveredBySubRegs = 1;
+}
+class MyClass<int size, list<ValueType> types, dag registers>
+  : RegisterClass<"Test", types, size, registers> {
+  let Size = size;
+}
+
+// Register Example:
+// D0_D1 -- D0 (sub0) -- S0 (ssub0)
+//       \            \- S1 (ssub1)
+//        \ D1 (sub1) -- S2 (ssub2)
+//                    \- S3 (ssub3)
+
+def sub0 : SubRegIndex<32>;
+def sub1 : SubRegIndex<32, 32>;
+def sub2 : SubRegIndex<32, 64>;
+
+def ssub0 : SubRegIndex<16>;
+def ssub1 : SubRegIndex<16, 16>;
+def ssub2 : ComposedSubRegIndex<sub1, ssub0>;
+def ssub3 : ComposedSubRegIndex<sub1, ssub1>;
+def ssub4 : ComposedSubRegIndex<sub2, ssub0>;
+
+def S0 : MyReg<"s0">;
+def S1 : MyReg<"s1">;
+def S2 : MyReg<"s2">;
+def S3 : MyReg<"s3">;
+def S4 : MyReg<"s4">;
+def S5 : MyReg<"s5">;
+def S6 : MyReg<"s6">;
+def S7 : MyReg<"s7">;
+def S8 : MyReg<"s8">;
+def S9 : MyReg<"s9">;
+def S10 : MyReg<"s10">;
+def S11 : MyReg<"s11">;
+def S12 : MyReg<"s12">;
+def S13 : MyReg<"s13">;
+def S14 : MyReg<"s14">;
+def S15 : MyReg<"s15">;
+def SRegs : MyClass<16, [i16], (sequence "S%u", 0, 15)>;
+def SRegslow : MyClass<16, [i16], (trunc SRegs, 5)>
+{
+  let ClassMask = 1;
+}
+def SRegshigh : MyClass<16, [i16], (shl SRegs, 5)>
+{
+  let ClassMask = 2;
+}
+def Stup2 : RegisterTuples<[ssub0, ssub1], [
+                            (shl SRegs, 0),
+                            (shl SRegs, 1)
+                           ]>;
+
+def SRegs2 : MyClass<32, [i32], (add Stup2)>;
+
+def TestTarget : Target;
+
+// CHECK-LABEL: // Register classes
+// CHECK: enum {
+// CHECK-NEXT:  SRegsRegClassID = 0,
+// CHECK-NEXT:  SRegshighRegClassID = 1,
+// CHECK-NEXT:  SRegslowRegClassID = 2,
+// CHECK-NEXT:  SRegs2RegClassID = 3,
+// CHECK-NEXT:  SRegs2_with_ssub1_in_SRegshighRegClassID = 4,
+// CHECK-NEXT:  SRegs2_with_ssub0_in_SRegshighRegClassID = 5,
+// CHECK-NEXT:  SRegs2_with_ssub0_in_SRegslowRegClassID = 6,
+// CHECK-NEXT:  SRegs2_with_ssub1_in_SRegslowRegClassID = 7,
+// CHECK-EMPTY:
+// CHECK-NEXT:  };

test/TableGen/ClassMask2.td

+// RUN: llvm-tblgen -gen-register-info -I %p/../../include %s -o - | FileCheck %s
+// Checks that ClassMask works in the expected way when classes with overlapping
+// class masks overlap.
+include "llvm/Target/Target.td"
+
+class MyReg<string n, list<Register> subregs = []>
+  : Register<n> {
+  let Namespace = "Test";
+  let SubRegs = subregs;
+  let CoveredBySubRegs = 1;
+}
+class MyClass<int size, list<ValueType> types, dag registers>
+  : RegisterClass<"Test", types, size, registers> {
+  let Size = size;
+}
+
+// Register Example:
+// D0_D1 -- D0 (sub0) -- S0 (ssub0)
+//       \            \- S1 (ssub1)
+//        \ D1 (sub1) -- S2 (ssub2)
+//                    \- S3 (ssub3)
+
+def sub0 : SubRegIndex<32>;
+def sub1 : SubRegIndex<32, 32>;
+def sub2 : SubRegIndex<32, 64>;
+
+def ssub0 : SubRegIndex<16>;
+def ssub1 : SubRegIndex<16, 16>;
+def ssub2 : ComposedSubRegIndex<sub1, ssub0>;
+def ssub3 : ComposedSubRegIndex<sub1, ssub1>;
+def ssub4 : ComposedSubRegIndex<sub2, ssub0>;
+
+def S0 : MyReg<"s0">;
+def S1 : MyReg<"s1">;
+def S2 : MyReg<"s2">;
+def S3 : MyReg<"s3">;
+def S4 : MyReg<"s4">;
+def S5 : MyReg<"s5">;
+def S6 : MyReg<"s6">;
+def S7 : MyReg<"s7">;
+def S8 : MyReg<"s8">;
+def S9 : MyReg<"s9">;
+def S10 : MyReg<"s10">;
+def S11 : MyReg<"s11">;
+def S12 : MyReg<"s12">;
+def S13 : MyReg<"s13">;
+def S14 : MyReg<"s14">;
+def S15 : MyReg<"s15">;
+def SRegs : MyClass<16, [i16], (sequence "S%u", 0, 15)>;
+def SRegslow : MyClass<16, [i16], (trunc SRegs, 5)>
+{
+  let ClassMask = 3;
+}
+def SRegslowhigh : MyClass<16, [i16], (trunc (shl SRegs, 3), 4)>
+{
+  let ClassMask = 6;
+}
+def SRegshigh : MyClass<16, [i16], (shl SRegs, 5)>
+{
+  let ClassMask = 12;
+}
+def Stup2 : RegisterTuples<[ssub0, ssub1], [
+                            (shl SRegs, 0),
+                            (shl SRegs, 1)
+                           ]>;
+
+def SRegs2 : MyClass<32, [i32], (add Stup2)>;
+
+def TestTarget : Target;
+
+// CHECK-LABEL: // Register classes
+// CHECK: enum {
+// CHECK-NEXT:  SRegsRegClassID = 0,
+// CHECK-NEXT:  SRegshighRegClassID = 1,
+// CHECK-NEXT:  SRegslowRegClassID = 2,
+// CHECK-NEXT:  SRegslowhighRegClassID = 3,
+// CHECK-NEXT:  SRegshigh_and_SRegslowhighRegClassID = 4,
+// CHECK-NEXT:  SRegslow_and_SRegslowhighRegClassID = 5,
+// CHECK-NEXT:  SRegs2RegClassID = 6,
+// CHECK-NEXT:  SRegs2_with_ssub1_in_SRegshighRegClassID = 7,
+// CHECK-NEXT:  SRegs2_with_ssub0_in_SRegshighRegClassID = 8,
+// CHECK-NEXT:  SRegs2_with_ssub0_in_SRegslowRegClassID = 9,
+// CHECK-NEXT:  SRegs2_with_ssub0_in_SRegslowhighRegClassID = 10,
+// CHECK-NEXT:  SRegs2_with_ssub1_in_SRegslowRegClassID = 11,
+// CHECK-NEXT:  SRegs2_with_ssub1_in_SRegslowhighRegClassID = 12,
+// CHECK-NEXT:  SRegs2_with_ssub0_in_SRegslow_and_SRegs2_with_ssub1_in_SRegslowhighRegClassID = 13,
+// CHECK-NEXT:  SRegs2_with_ssub0_in_SRegslowhigh_and_SRegs2_with_ssub1_in_SRegshighRegClassID = 14,
+// CHECK-NEXT:  SRegs2_with_ssub0_in_SRegslowhigh_and_SRegs2_with_ssub1_in_SRegslowhighRegClassID = 15,
+// CHECK-NEXT:  SRegs2_with_ssub0_in_SRegshigh_and_SRegslowhighRegClassID = 16,
+// CHECK-NEXT:  SRegs2_with_ssub0_in_SRegslow_and_SRegslowhighRegClassID = 17,
+// CHECK-NEXT:  SRegs2_with_ssub1_in_SRegshigh_and_SRegslowhighRegClassID = 18,
+// CHECK-NEXT:  SRegs2_with_ssub1_in_SRegslow_and_SRegslowhighRegClassID = 19,
+// CHECK-NEXT:  SRegs2_with_ssub0_in_SRegshigh_and_SRegs2_with_ssub1_in_SRegslowhighRegClassID = 20,
+// CHECK-NEXT:  SRegs2_with_ssub0_in_SRegslowhigh_and_SRegs2_with_ssub1_in_SRegslowRegClassID = 21,
+// CHECK-EMPTY:
+// CHECK-NEXT:  };

test/TableGen/ClassMask3.td

+// RUN: llvm-tblgen -gen-register-info -I %p/../../include %s -o - | FileCheck %s
+// Checks that ClassMask don't interfere with classes that are completely disjoint.
+include "llvm/Target/Target.td"
+
+class MyReg<string n, list<Register> subregs = []>
+  : Register<n> {
+  let Namespace = "Test";
+  let SubRegs = subregs;
+  let CoveredBySubRegs = 1;
+}
+class MyClass<int size, list<ValueType> types, dag registers>
+  : RegisterClass<"Test", types, size, registers> {
+  let Size = size;
+}
+
+// Register Example:
+// D0_D1 -- D0 (sub0) -- S0 (ssub0)
+//       \            \- S1 (ssub1)
+//        \ D1 (sub1) -- S2 (ssub2)
+//                    \- S3 (ssub3)
+
+def sub0 : SubRegIndex<32>;
+def sub1 : SubRegIndex<32, 32>;
+def sub2 : SubRegIndex<32, 64>;
+
+def ssub0 : SubRegIndex<16>;
+def ssub1 : SubRegIndex<16, 16>;
+def ssub2 : ComposedSubRegIndex<sub1, ssub0>;
+def ssub3 : ComposedSubRegIndex<sub1, ssub1>;
+def ssub4 : ComposedSubRegIndex<sub2, ssub0>;
+
+def S0 : MyReg<"s0">;
+def S1 : MyReg<"s1">;
+def S2 : MyReg<"s2">;
+def S3 : MyReg<"s3">;
+def S4 : MyReg<"s4">;
+def S5 : MyReg<"s5">;
+def S6 : MyReg<"s6">;
+def S7 : MyReg<"s7">;
+def S8 : MyReg<"s8">;
+def S9 : MyReg<"s9">;
+def S10 : MyReg<"s10">;
+def S11 : MyReg<"s11">;
+def S12 : MyReg<"s12">;
+def S13 : MyReg<"s13">;
+def S14 : MyReg<"s14">;
+def S15 : MyReg<"s15">;
+def SRegs : MyClass<16, [i16], (sequence "S%u", 0, 15)>;
+def SRegslow : MyClass<16, [i16], (trunc SRegs, 5)>
+{
+  let ClassMask = 3;
+}
+def SRegshigh : MyClass<16, [i16], (shl SRegs, 8)>
+{
+  let ClassMask = 12;
+}
+def Stup2 : RegisterTuples<[ssub0, ssub1], [
+                            (shl SRegs, 0),
+                            (shl SRegs, 1)
+                           ]>;
+
+def SRegs2 : MyClass<32, [i32], (add Stup2)>;
+
+def TestTarget : Target;
+
+// CHECK-LABEL: // Register classes
+// CHECK: enum {
+// CHECK-NEXT:  SRegsRegClassID = 0,
+// CHECK-NEXT:  SRegshighRegClassID = 1,
+// CHECK-NEXT:  SRegslowRegClassID = 2,
+// CHECK-NEXT:  SRegs2RegClassID = 3,
+// CHECK-NEXT:  SRegs2_with_ssub1_in_SRegshighRegClassID = 4,
+// CHECK-NEXT:  SRegs2_with_ssub0_in_SRegshighRegClassID = 5,
+// CHECK-NEXT:  SRegs2_with_ssub0_in_SRegslowRegClassID = 6,
+// CHECK-NEXT:  SRegs2_with_ssub1_in_SRegslowRegClassID = 7,
+// CHECK-EMPTY:
+// CHECK-NEXT:  };

test/TableGen/ClassMask4.td

+// RUN: llvm-tblgen -gen-register-info -I %p/../../include %s -o - | FileCheck %s
+// Checks that a class with ClassMask = 0 doesn't participate in creating
+// inferred classes.
+include "llvm/Target/Target.td"
+
+class MyReg<string n, list<Register> subregs = []>
+  : Register<n> {
+  let Namespace = "Test";
+  let SubRegs = subregs;
+  let CoveredBySubRegs = 1;
+}
+class MyClass<int size, list<ValueType> types, dag registers>
+  : RegisterClass<"Test", types, size, registers> {
+  let Size = size;
+}
+
+// Register Example:
+// D0_D1 -- D0 (sub0) -- S0 (ssub0)
+//       \            \- S1 (ssub1)
+//        \ D1 (sub1) -- S2 (ssub2)
+//                    \- S3 (ssub3)
+
+def sub0 : SubRegIndex<32>;
+def sub1 : SubRegIndex<32, 32>;
+def sub2 : SubRegIndex<32, 64>;
+
+def ssub0 : SubRegIndex<16>;
+def ssub1 : SubRegIndex<16, 16>;
+def ssub2 : ComposedSubRegIndex<sub1, ssub0>;
+def ssub3 : ComposedSubRegIndex<sub1, ssub1>;
+def ssub4 : ComposedSubRegIndex<sub2, ssub0>;
+
+def S0 : MyReg<"s0">;
+def S1 : MyReg<"s1">;
+def S2 : MyReg<"s2">;
+def S3 : MyReg<"s3">;
+def S4 : MyReg<"s4">;
+def S5 : MyReg<"s5">;
+def S6 : MyReg<"s6">;
+def S7 : MyReg<"s7">;
+def S8 : MyReg<"s8">;
+def S9 : MyReg<"s9">;
+def S10 : MyReg<"s10">;
+def S11 : MyReg<"s11">;
+def S12 : MyReg<"s12">;
+def S13 : MyReg<"s13">;
+def S14 : MyReg<"s14">;
+def S15 : MyReg<"s15">;
+def SRegs : MyClass<16, [i16], (sequence "S%u", 0, 15)>;
+def SRegslow : MyClass<16, [i16], (trunc SRegs, 5)>
+{
+  let ClassMask = 3;
+}
+def SRegslowhigh : MyClass<16, [i16], (trunc (shl SRegs, 2), 8)>
+{
+  let ClassMask = 0;
+}
+def SRegshigh : MyClass<16, [i16], (shl SRegs, 5)>
+{
+  let ClassMask = 12;
+}
+def Stup3 : RegisterTuples<[ssub0, ssub1, ssub2], [
+                            (shl SRegs, 0),
+                            (shl SRegs, 1),
+                            (shl SRegs, 2)
+                           ]>;
+
+def SRegs3 : MyClass<48, [untyped], (add Stup3)>;
+
+def TestTarget : Target;
+
+// CHECK-LABEL: // Register classes
+// CHECK: enum {
+// CHECK-NEXT:  SRegsRegClassID = 0,
+// CHECK-NEXT:  SRegshighRegClassID = 1,
+// CHECK-NEXT:  SRegslowhighRegClassID = 2,
+// CHECK-NEXT:  SRegslowRegClassID = 3,
+// CHECK-NEXT:  SRegs3RegClassID = 4,
+// CHECK-NEXT:  SRegs3_with_ssub2_in_SRegshighRegClassID = 5,
+// CHECK-NEXT:  SRegs3_with_ssub1_in_SRegshighRegClassID = 6,
+// CHECK-NEXT:  SRegs3_with_ssub0_in_SRegshighRegClassID = 7,
+// CHECK-NEXT:  SRegs3_with_ssub0_in_SRegslowRegClassID = 8,
+// CHECK-NEXT:  SRegs3_with_ssub1_in_SRegslowRegClassID = 9,
+// CHECK-NEXT:  SRegs3_with_ssub2_in_SRegslowRegClassID = 10,
+// CHECK-EMPTY:
+// CHECK-NEXT:  };

utils/TableGen/CodeGenRegisters.h

     bool Allocatable;
     StringRef AltOrderSelect;
     uint8_t AllocationPriority;
+    unsigned ClassMask;
     /// Contains the combination of the lane masks of all subregisters.
     LaneBitmask LaneMask;
     /// True if there are at least 2 subregisters which do not interfere.

       RegSizeInfoByHwMode RSI;
 
       Key(const CodeGenRegister::Vec *M, const RegSizeInfoByHwMode &I)
           : Members(M), RSI(I) {}
 
       Key(const CodeGenRegisterClass &RC)
           : Members(&RC.getMembers()), RSI(RC.RSI) {}
 
       // Lexicographical order of (Members, RegSizeInfoByHwMode).
       bool operator<(const Key&) const;
     };
 
     // Create a non-user defined register class.
-    CodeGenRegisterClass(CodeGenRegBank&, StringRef Name, Key Props);
+    CodeGenRegisterClass(CodeGenRegBank &, StringRef Name, unsigned ClassMask,
+                         Key Props);
 
     // Called by CodeGenRegBank::CodeGenRegBank().
     static void computeSubClasses(CodeGenRegBank&);

     // Create a synthetic sub-class if it is missing.
     CodeGenRegisterClass *getOrCreateSubClass(const CodeGenRegisterClass *RC,
                                               const CodeGenRegister::Vec *Membs,
-                                              StringRef Name);
+                                              StringRef Name,
+                                              unsigned ClassMask);
 
     // Infer missing register classes.
     void computeInferredRegisterClasses();

utils/TableGen/CodeGenRegisters.cpp

   if (AllocationPriority < 0 || AllocationPriority > 63)
     PrintFatalError(R->getLoc(), "AllocationPriority out of range [0,63]");
   this->AllocationPriority = AllocationPriority;
+  BitsInit *BI = R->getValueAsBitsInit("ClassMask");
+  uint64_t Value = 0;
+  for (unsigned b = 0, be = BI->getNumBits(); b != be; ++b) {
+    if (BitInit *B = dyn_cast<BitInit>(BI->getBit(b)))
+      Value |= (uint64_t)B->getValue() << b;
+  }
+  this->ClassMask = static_cast<unsigned>(Value);
 }
 
 // Create an inferred register class that was missing from the .td files.
 // Most properties will be inherited from the closest super-class after the
 // class structure has been computed.
 CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank,
-                                           StringRef Name, Key Props)
-  : Members(*Props.Members),
-    TheDef(nullptr),
-    Name(Name),
-    TopoSigs(RegBank.getNumTopoSigs()),
-    EnumValue(-1),
-    RSI(Props.RSI),
-    CopyCost(0),
-    Allocatable(true),
-    AllocationPriority(0) {
+                                           StringRef Name, unsigned ClassMask,
+                                           Key Props)
+    : Members(*Props.Members), TheDef(nullptr), Name(Name),
+      TopoSigs(RegBank.getNumTopoSigs()), EnumValue(-1), RSI(Props.RSI),
+      CopyCost(0), Allocatable(true), AllocationPriority(0),
+      ClassMask(ClassMask) {
   Artificial = true;
   for (const auto R : Members) {
     TopoSigs.set(R->getTopoSig());

   Allocatable = Super.Allocatable;
   AltOrderSelect = Super.AltOrderSelect;
   AllocationPriority = Super.AllocationPriority;
-
   // Copy all allocation orders, filter out foreign registers from the larger
   // super-class.
   Orders.resize(Super.Orders.size());

 }
 
 // Create a synthetic sub-class if it is missing.
-CodeGenRegisterClass*
+CodeGenRegisterClass *
 CodeGenRegBank::getOrCreateSubClass(const CodeGenRegisterClass *RC,
                                     const CodeGenRegister::Vec *Members,
-                                    StringRef Name) {
+                                    StringRef Name, unsigned ClassMask) {
+  assert(ClassMask && "Trying to create an artificial class with 0 ClassMask");
   // Synthetic sub-class has the same size and alignment as RC.
   CodeGenRegisterClass::Key K(Members, RC->RSI);
   RCKeyMap::const_iterator FoundI = Key2RC.find(K);

     return FoundI->second;
 
   // Sub-class doesn't exist, create a new one.
-  RegClasses.emplace_back(*this, Name, K);
+  RegClasses.emplace_back(*this, Name, ClassMask, K);
   addToMaps(&RegClasses.back());
   return &RegClasses.back();
 }

     CodeGenRegisterClass *RC2 = &*I;
     if (RC1 == RC2)
       continue;
-
+    const unsigned CompositeMask = RC1->ClassMask & RC2->ClassMask;
+    // Create a subclass only if the masks of the classes are compatible
+    if (!CompositeMask)
+      continue;
     // Compute the set intersection of RC1 and RC2.
     const CodeGenRegister::Vec &Memb1 = RC1->getMembers();
     const CodeGenRegister::Vec &Memb2 = RC2->getMembers();

     std::set_intersection(
         Memb1.begin(), Memb1.end(), Memb2.begin(), Memb2.end(),
         std::inserter(Intersection, Intersection.begin()), deref<llvm::less>());
-
     // Skip disjoint class pairs.
     if (Intersection.empty())
       continue;

       std::swap(RC1, RC2);
 
     getOrCreateSubClass(RC1, &Intersection,
-                        RC1->getName() + "_and_" + RC2->getName());
+                        RC1->getName() + "_and_" + RC2->getName(),
+                        CompositeMask);
   }
 }
 

       continue;
     }
     // This is a real subset.  See if we have a matching class.
-    CodeGenRegisterClass *SubRC =
-      getOrCreateSubClass(RC, &I->second,
-                          RC->getName() + "_with_" + I->first->getName());
+    CodeGenRegisterClass *SubRC = getOrCreateSubClass(
+        RC, &I->second, RC->getName() + "_with_" + I->first->getName(),
+        RC->ClassMask);
     RC->setSubClassWithSubReg(&SubIdx, SubRC);
   }
 }

 // has a maximal result for any SubIdx and any X >= FirstSubRegRC.
 //
 
-void CodeGenRegBank::inferMatchingSuperRegClass(CodeGenRegisterClass *RC,
-                                                std::list<CodeGenRegisterClass>::iterator FirstSubRegRC) {
+void CodeGenRegBank::inferMatchingSuperRegClass(
+    CodeGenRegisterClass *RC,
+    std::list<CodeGenRegisterClass>::iterator FirstSubRegRC) {
   SmallVector<std::pair<const CodeGenRegister*,
                         const CodeGenRegister*>, 16> SSPairs;
   BitVector TopoSigs(getNumTopoSigs());

       // Topological shortcut: SubRC members have the wrong shape.
       if (!TopoSigs.anyCommon(SubRC.getTopoSigs()))
         continue;
+      // If RC and SubRC are disjoint then skip
+      if (!(RC->ClassMask & SubRC.ClassMask))
+        continue;
       // Compute the subset of RC that maps into SubRC.
       CodeGenRegister::Vec SubSetVec;
       for (unsigned i = 0, e = SSPairs.size(); i != e; ++i)

 
       // Only a subset of RC maps into SubRC. Make sure it is represented by a
       // class.
-      getOrCreateSubClass(RC, &SubSetVec, RC->getName() + "_with_" +
-                                          SubIdx.getName() + "_in_" +
-                                          SubRC.getName());
+      getOrCreateSubClass(RC, &SubSetVec,
+                          RC->getName() + "_with_" + SubIdx.getName() + "_in_" +
+                              SubRC.getName(),
+                          RC->ClassMask & SubRC.ClassMask);
     }
   }
 }