[WebAssembly] Simplified selecting asmmatcher stack instructions.

[aardappel]

Summary

By using the existing isCodeGenOnly bit in the tablegen defs, as
suggested by tlively in https://reviews.llvm.org/D51662

Tested: llvm-lit -v find test -name WebAssembly

[tlively]

Perfect!

llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrControl.td

 // TODO: SelectionDAG's lowering insists on using a pointer as the index for
 // jump tables, so in practice we don't ever use BR_TABLE_I64 in wasm32 mode
 // currently.
 // Set TSFlags{0} to 1 to indicate that the variable_ops are immediates.
 // Set TSFlags{1} to 1 to indicate that the immediates represent labels.
 // FIXME: this can't inherit from I<> since there is no way to inherit from a
 // multiclass and still have the let statements.
 let isTerminator = 1, hasCtrlDep = 1, isBarrier = 1 in {
+let isCodeGenOnly = 1 in
 def BR_TABLE_I32 : NI<(outs), (ins I32:$index, variable_ops),
                       [(WebAssemblybr_table I32:$index)], 0,
                       "br_table \t$index", 0x0e> {
   let TSFlags{0} = 1;
   let TSFlags{1} = 1;
 }
 def BR_TABLE_I32_S : NI<(outs), (ins variable_ops),
                         [], 1,
                         "br_table", 0x0e> {
   let TSFlags{0} = 1;
   let TSFlags{1} = 1;
 }
+let isCodeGenOnly = 1 in
 def BR_TABLE_I64 : NI<(outs), (ins I64:$index, variable_ops),
                       [(WebAssemblybr_table I64:$index)], 0,
                       "br_table \t$index"> {
   let TSFlags{0} = 1;
   let TSFlags{1} = 1;
 }
 def BR_TABLE_I64_S : NI<(outs), (ins variable_ops),
                         [], 1,

llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrFormats.td

 // stack), and get_locals and set_locals are explicit. The register instructions
 // are converted to their corresponding stack instructions before lowering to
 // MC.
 // Every instruction should want to be based on this multi-class to guarantee
 // there is always an equivalent pair of instructions.
 multiclass I<dag oops_r, dag iops_r, dag oops_s, dag iops_s,
              list<dag> pattern_r, string asmstr_r = "", string asmstr_s = "",
              bits<32> inst = -1> {
+  let isCodeGenOnly = 1 in
   def "" : NI<oops_r, iops_r, pattern_r, 0, asmstr_r, inst>;
   def _S : NI<oops_s, iops_s, [], 1, asmstr_s, inst>;
 }
 
 // For instructions that have no register ops, so both sets are the same.
 multiclass NRI<dag oops, dag iops, list<dag> pattern, string asmstr = "",
                bits<32> inst = -1> {
   defm "": I<oops, iops, oops, iops, pattern, asmstr, asmstr, inst>;

llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp

for (const auto &Pair : SubtargetFeatures)
     LLVM_DEBUG(Pair.second.dump());
 #endif // NDEBUG
   assert(SubtargetFeatures.size() <= 64 && "Too many subtarget features!");
 
   bool HasMnemonicFirst = AsmParser->getValueAsBit("HasMnemonicFirst");
   bool ReportMultipleNearMisses =
       AsmParser->getValueAsBit("ReportMultipleNearMisses");
 
-  bool IsWebAssemblyTarget = Target.getName() == "WebAssembly";
-
   // Parse the instructions; we need to do this first so that we can gather the
   // singleton register classes.
   SmallPtrSet<Record*, 16> SingletonRegisters;
   unsigned VariantCount = Target.getAsmParserVariantCount();
   for (unsigned VC = 0; VC != VariantCount; ++VC) {
     Record *AsmVariant = Target.getAsmParserVariant(VC);
     StringRef CommentDelimiter =
         AsmVariant->getValueAsString("CommentDelimiter");
for (const CodeGenInstruction *CGI : Target.getInstructionsByEnumValue()) {
       if (CGI->TheDef->getValueAsBit("isCodeGenOnly"))
         continue;
 
       // Ignore instructions for different instructions
       StringRef V = CGI->TheDef->getValueAsString("AsmVariantName");
       if (!V.empty() && V != Variant.Name)
         continue;
 
-      // [WebAssembly] Ignore non-stack instructions.
-      if (IsWebAssemblyTarget) {
-        auto Bit = CGI->TheDef->getValue("StackBased")->getValue()->
-                     getCastTo(BitRecTy::get());
-        if (!Bit || !reinterpret_cast<const BitInit *>(Bit)->getValue())
-          continue;
-      }
-
       auto II = llvm::make_unique<MatchableInfo>(*CGI);
 
       II->initialize(*this, SingletonRegisters, Variant, HasMnemonicFirst);
 
       // Ignore instructions which shouldn't be matched and diagnose invalid
       // instruction definitions with an error.
       if (!II->validate(CommentDelimiter, false))
         continue;