[ARM] Disallow icmp with negative imm and overflow

[samparker]

Summary

We allow overflowing instructions if they're decreasing and only used by an unsigned compare. Add the extra condition that the icmp cannot be using a negative immediate.

[SjoerdMeijer]

LGTM

llvm/trunk/lib/Target/ARM/ARMCodeGenPrepare.cpp

if (Opc == Instruction::Add || Opc == Instruction::Sub) {
     // We don't care if the add or sub could wrap if the value is decreasing
     // and is only being used by an unsigned compare.
     if (!I->hasOneUse() ||
         !isa<ICmpInst>(*I->user_begin()) ||
         !isa<ConstantInt>(I->getOperand(1)))
       return false;
 
     auto *CI = cast<ICmpInst>(*I->user_begin());
+    
+    // Don't support an icmp that deals with sign bits, including negative
+    // immediates
     if (CI->isSigned())
       return false;
 
+    if (auto *Const = dyn_cast<ConstantInt>(CI->getOperand(0)))
+      if (Const->isNegative())
+        return false;
+
+    if (auto *Const = dyn_cast<ConstantInt>(CI->getOperand(1)))
+      if (Const->isNegative())
+        return false;
+
     bool NegImm = cast<ConstantInt>(I->getOperand(1))->isNegative();
     bool IsDecreasing = ((Opc == Instruction::Sub) && !NegImm) ||
                         ((Opc == Instruction::Add) && NegImm);
     if (!IsDecreasing)
       return false;
 
     LLVM_DEBUG(dbgs() << "ARM CGP: Allowing safe overflow for " << *I << "\n");
     return true;

llvm/trunk/test/CodeGen/ARM/arm-cgp-icmps.ll

 ; CHECK-COMMON: movw [[MINUS_ONE:r[0-9]+]], #32767
 define i32 @icmp_i15(i15 zeroext %arg0, i15 zeroext %arg1) {
   %xor = xor i15 %arg0, -1
   %cmp = icmp eq i15 %xor, %arg1
   %res = select i1 %cmp, i32 21, i32 42
   ret i32 %res
 }
 
+; CHECK-COMMON-LABEL: icmp_minus_imm
+; CHECK-NODSP: subs [[SUB:r[0-9]+]],
+; CHECK-NODSP: uxtb [[UXT:r[0-9]+]],
+; CHECK-NODSP: cmp [[UXT]], #251
+
+; CHECK-DSP: subs [[SUB:r[0-9]+]],
+; CHECK-DSP: uxtb [[UXT:r[0-9]+]],
+; CHECK-DSP: cmp [[UXT]], #251
+
+; CHECK-DSP-IMM: ldrb [[A:r[0-9]+]],
+; CHECK-DSP-IMM: movs  [[MINUS_7:r[0-9]+]], #249
+; CHECK-DSP-IMM: uadd8 [[RES:r[0-9]+]], [[A]], [[MINUS_7]]
+; CHECK-DSP-IMM: cmp [[RES]], #251
+define i32 @icmp_minus_imm(i8* %a) {
+entry:
+  %0 = load i8, i8* %a, align 1
+  %add.i = add i8 %0, -7
+  %cmp = icmp ugt i8 %add.i, -5
+  %conv1 = zext i1 %cmp to i32
+  ret i32 %conv1
+}
+