[RISCV] Fix crash in decoding instruction with unknown floating point rounding mode

[apazos]

Summary

Instead of crashing in printFRMArg, decode and warn about invalid instruction.

This bug was uncovered by a LLVM MC Disassembler Protocol Buffer Fuzzer for the RISC-V assembly language.

[asb]

Looks good to me, thanks. Just one tiny comment inline.

As this is a disassembler-only test and only makes sense as a disassembler test it might be worth putting in test/MC/Disassembler/RISCV, and perhaps choosing a more descriptive name. e.g. invalid-fp-founding-mode.txt.

lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

120

Can't this line be deleted as the case is fully covered.

[apazos]

Updated test case location and name.

lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

 //===-- RISCVDisassembler.cpp - Disassembler for RISCV --------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements the RISCVDisassembler class.
 //
 //===----------------------------------------------------------------------===//
 
+#include "MCTargetDesc/RISCVBaseInfo.h"
 #include "MCTargetDesc/RISCVMCTargetDesc.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCDisassembler/MCDisassembler.h"
 #include "llvm/MC/MCFixedLenDisassembler.h"
 #include "llvm/MC/MCInst.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/Support/Endian.h"
static DecodeStatus decodeCLUIImmOperand(MCInst &Inst, uint64_t Imm,
   assert(isUInt<6>(Imm) && "Invalid immediate");
   if (Imm > 31) {
     Imm = (SignExtend64<6>(Imm) & 0xfffff);
   }
   Inst.addOperand(MCOperand::createImm(Imm));
   return MCDisassembler::Success;
 }
 
+static DecodeStatus decodeFRMArg(MCInst &Inst, uint64_t Imm,
+                                 int64_t Address,
+                                 const void *Decoder) {
+  assert(isUInt<3>(Imm) && "Invalid immediate");
+  if (!llvm::RISCVFPRndMode::isValidRoundingMode(Imm))
+    return MCDisassembler::Fail;
+
+  Inst.addOperand(MCOperand::createImm(Imm));
+  return MCDisassembler::Success;
+}
+
 #include "RISCVGenDisassemblerTables.inc"
 
 DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
                                                ArrayRef<uint8_t> Bytes,
                                                uint64_t Address,
                                                raw_ostream &OS,
                                                raw_ostream &CS) const {
   // TODO: This will need modification when supporting instruction set

lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

return StringSwitch<RoundingMode>(Str)
       .Case("rne", RISCVFPRndMode::RNE)
       .Case("rtz", RISCVFPRndMode::RTZ)
       .Case("rdn", RISCVFPRndMode::RDN)
       .Case("rup", RISCVFPRndMode::RUP)
       .Case("rmm", RISCVFPRndMode::RMM)
       .Case("dyn", RISCVFPRndMode::DYN)
       .Default(RISCVFPRndMode::Invalid);
 }
+
+inline static bool isValidRoundingMode(unsigned Mode) {
+  switch (Mode) {
+  default:
+    return false;
+  case RISCVFPRndMode::RNE:
+  case RISCVFPRndMode::RTZ:
+  case RISCVFPRndMode::RDN:
+  case RISCVFPRndMode::RUP:
+  case RISCVFPRndMode::RMM:
+  case RISCVFPRndMode::DYN:
+    return true;
+  }
+  return false;
+}
+
 } // namespace RISCVFPRndMode
 } // namespace llvm
 
 #endif

lib/Target/RISCV/RISCVInstrInfoF.td

def FRMArg : AsmOperandClass {
   let Name = "FRMArg";
   let RenderMethod = "addFRMArgOperands";
   let DiagnosticType = "InvalidFRMArg";
 }
 
 def frmarg : Operand<XLenVT> {
   let ParserMatchClass = FRMArg;
   let PrintMethod = "printFRMArg";
-  let DecoderMethod = "decodeUImmOperand<3>";
+  let DecoderMethod = "decodeFRMArg";
 }
 
 //===----------------------------------------------------------------------===//
 // Instruction class templates
 //===----------------------------------------------------------------------===//
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
 class FPFMAS_rrr_frm<RISCVOpcode opcode, string opcodestr>

test/MC/RISCV/fuzzer-invalid.txt

+# RUN: not llvm-mc -disassemble -triple=riscv32 -mattr=+f,+d < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -disassemble -triple=riscv64 -mattr=+f,+d < %s 2>&1 | FileCheck %s
+#
+# Test generated by a LLVM MC Disassembler Protocol Buffer Fuzzer
+# for the RISC-V assembly language.
+
+# This decodes as fadd.s  ft0, ft0, ft0 with unknown floating point rounding mode
+[0x53 0x50 0x00 0x00]
+# CHECK: warning: invalid instruction encoding