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[SelectionDAG] enhance vector demanded elements to look at a vector select condition operand
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Authored by spatel on Sep 5 2018, 11:23 AM.

Details

Summary

This is the DAG equivalent of D51433.
If we know we're not using all vector lanes, use that knowledge to potentially simplify a vselect condition.

The reduction/horizontal tests show that we are eliminating AVX1 operations on the upper half of 256-bit vectors because we don't need those anyway (double-check to make sure I'm reading those diffs correctly).
I'm not sure what the pr34592 test is showing. That's run with -O0; is SimplifyDemandedVectorElts supposed to be running there?

The removal of the temporary DemandedLHS/DemandedRHS variables is NFC, so we could make that a pre-commit IIUC.

Diff Detail

Event Timeline

spatel created this revision.Sep 5 2018, 11:23 AM
RKSimon added inline comments.Sep 5 2018, 12:53 PM
lib/CodeGen/SelectionDAG/TargetLowering.cpp
1539

Can we use UnusedZero to alter the LHS/RHS DemandedElts ?

spatel added inline comments.Sep 5 2018, 1:42 PM
lib/CodeGen/SelectionDAG/TargetLowering.cpp
1539

If UnusedZero (if we do use it, I'll change the name of course) has set bits, that would mean that we're choosing RHS elements in this select, right?

UnusedUndef is probably the more interesting part, and that's what the TODO comment is alluding to. I'm not sure what we decided on this: if an element of the condition is undef, does that mean the result is undef? In that case, I think we could do something like this below here:
KnownUndef = UndefCond | (UndefLHS & UndefRHS);

I did try that change, but there were no existing test diffs, so I thought it was better left for a follow-up.

RKSimon added inline comments.Sep 6 2018, 2:44 AM
lib/CodeGen/SelectionDAG/TargetLowering.cpp
1539

If UnusedZero (if we do use it, I'll change the name of course) has set bits, that would mean that we're choosing RHS elements in this select, right?

Yes, Known zero select values demand RHS and ignore LHS - remember that the unknown/zero masks are only guaranteed to be correct for demanded elements.

KnownUndef = UndefCond | (UndefLHS & UndefRHS);

I think the only case we can UndefCond is if UndefLHS & UndefRHS are both known to be true, something like:

KnownUndef = (SelectLHS & UndefLHS) | (SelectRHS & UndefRHS);
KnownUndef |= UndefCond & (UndefLHS & UndefRHS);

Another thing will be to add a SimplifyDemandedVectorElts call to DAGCombiner::visitVSELECT (PR37989)

spatel updated this revision to Diff 164216.Sep 6 2018, 7:47 AM

Patch updated:
No functional change from the last rev, but updated the TODO comment based on finding the answer to the select-condition-is-undef question. For reference, this is how we handle it in IR-level constant folding:

if (isa<UndefValue>(Cond)) {
  if (isa<UndefValue>(V1)) return V1;
  return V2;
}
RKSimon accepted this revision.Sep 8 2018, 7:58 AM

LGTM

This revision is now accepted and ready to land.Sep 8 2018, 7:58 AM
This revision was automatically updated to reflect the committed changes.