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Differential D51541

AMDGPU: Restrict extract_vector_elt combine to loads
ClosedPublic

Authored by arsenm on Aug 31 2018, 7:24 AM.

Details

Reviewers
rampitec
Summary

The intention is to enable the extract_vector_elt load combine,
and doing this for other operations interferes with more
useful optimizations on vectors.




Handle any type of load since in principle we should do the

same combine for the various load intrinsics.
Diff Detail
Event Timeline
arsenm created this revision.Aug 31 2018, 7:24 AM
Herald added subscribers: t-tye, tpr, dstuttard and 5 others.  ·  View Herald TranscriptAug 31 2018, 7:24 AM
rampitec accepted this revision.Aug 31 2018, 8:21 AM
LGTM
This revision is now accepted and ready to land.Aug 31 2018, 8:21 AM
arsenm closed this revision.Aug 31 2018, 8:42 AM
r341219
Revision Contents
PathSize
lib/
Target/
AMDGPU/
3 lines
test/
CodeGen/
AMDGPU/
38 lines
260 lines
260 lines
4 lines
Diff 163530
lib/Target/AMDGPU/SIISelLowering.cpp
  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 7,935 Lines • ▼ Show 20 LinesSDValue SITargetLowering::performExtractVectorEltCombine(




  unsigned VecSize = VecVT.getSizeInBits();
  unsigned VecSize = VecVT.getSizeInBits();

  unsigned EltSize = EltVT.getSizeInBits();
  unsigned EltSize = EltVT.getSizeInBits();




  // Try to turn sub-dword accesses of vectors into accesses of the same 32-bit
  // Try to turn sub-dword accesses of vectors into accesses of the same 32-bit

  // elements. This exposes more load reduction opportunities by replacing
  // elements. This exposes more load reduction opportunities by replacing

  // multiple small extract_vector_elements with a single 32-bit extract.
  // multiple small extract_vector_elements with a single 32-bit extract.

  auto *Idx = dyn_cast<ConstantSDNode>(N->getOperand(1));
  auto *Idx = dyn_cast<ConstantSDNode>(N->getOperand(1));

  if (EltSize <= 16 &&
  if (isa<MemSDNode>(Vec) &&

      EltSize <= 16 &&

      EltVT.isByteSized() &&
      EltVT.isByteSized() &&

      VecSize > 32 &&
      VecSize > 32 &&

      VecSize % 32 == 0 &&
      VecSize % 32 == 0 &&

      Idx) {
      Idx) {

    EVT NewVT = getEquivalentMemType(*DAG.getContext(), VecVT);
    EVT NewVT = getEquivalentMemType(*DAG.getContext(), VecVT);




    unsigned BitIndex = Idx->getZExtValue() * EltSize;
    unsigned BitIndex = Idx->getZExtValue() * EltSize;

    unsigned EltIdx = BitIndex / 32;
    unsigned EltIdx = BitIndex / 32;

▲ Show 20 Lines • Show All 1,292 Lines • Show Last 20 Lines
test/CodeGen/AMDGPU/fexp.ll
Show First 20 Lines • Show All 218 Lines • ▼ Show 20 Lines
;   %result = call <3 x half> @llvm.exp.v3f16(<3 x half> %arg0)
;   %result = call <3 x half> @llvm.exp.v3f16(<3 x half> %arg0)

;   ret <3 x half> %result
;   ret <3 x half> %result

; }
; }




define <4 x half> @v_exp_v4f16(<4 x half> %arg0) {
define <4 x half> @v_exp_v4f16(<4 x half> %arg0) {

; SI-LABEL: v_exp_v4f16:
; SI-LABEL: v_exp_v4f16:

; SI:       ; %bb.0:
; SI:       ; %bb.0:

; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; SI-NEXT:    v_cvt_f16_f32_e32 v0, v0

; SI-NEXT:    v_cvt_f16_f32_e32 v1, v1

; SI-NEXT:    v_cvt_f16_f32_e32 v2, v2

; SI-NEXT:    v_cvt_f16_f32_e32 v3, v3

; SI-NEXT:    v_mov_b32_e32 v4, 0x3fb8aa3b

; SI-NEXT:    v_cvt_f32_f16_e32 v0, v0

; SI-NEXT:    v_cvt_f32_f16_e32 v1, v1

; SI-NEXT:    v_cvt_f32_f16_e32 v2, v2

; SI-NEXT:    v_cvt_f32_f16_e32 v3, v3

; SI-NEXT:    v_mul_f32_e32 v3, v3, v4

; SI-NEXT:    v_mul_f32_e32 v2, v2, v4

; SI-NEXT:    v_mul_f32_e32 v1, v1, v4

; SI-NEXT:    v_mul_f32_e32 v0, v0, v4

; SI-NEXT:    v_exp_f32_e32 v3, v3

; SI-NEXT:    v_exp_f32_e32 v2, v2

; SI-NEXT:    v_exp_f32_e32 v1, v1

; SI-NEXT:    v_exp_f32_e32 v0, v0

; SI-NEXT:    v_cvt_f16_f32_e32 v3, v3
; SI-NEXT:    v_cvt_f16_f32_e32 v3, v3

; SI-NEXT:    v_cvt_f16_f32_e32 v2, v2
; SI-NEXT:    v_cvt_f16_f32_e32 v2, v2

; SI-NEXT:    v_cvt_f16_f32_e32 v1, v1
; SI-NEXT:    v_cvt_f16_f32_e32 v1, v1

; SI-NEXT:    v_cvt_f16_f32_e32 v0, v0
; SI-NEXT:    v_cvt_f16_f32_e32 v0, v0

; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT:    v_mov_b32_e32 v4, 0x3fb8aa3b

; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v1

; SI-NEXT:    v_or_b32_e32 v3, v2, v3

; SI-NEXT:    v_or_b32_e32 v1, v0, v1

; SI-NEXT:    v_cvt_f32_f16_e32 v0, v1

; SI-NEXT:    v_cvt_f32_f16_e32 v2, v3

; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v1

; SI-NEXT:    v_lshrrev_b32_e32 v3, 16, v3

; SI-NEXT:    v_cvt_f32_f16_e32 v1, v1

; SI-NEXT:    v_cvt_f32_f16_e32 v3, v3
; SI-NEXT:    v_cvt_f32_f16_e32 v3, v3

; SI-NEXT:    v_cvt_f32_f16_e32 v2, v2

; SI-NEXT:    v_cvt_f32_f16_e32 v1, v1

; SI-NEXT:    v_cvt_f32_f16_e32 v0, v0

; SI-NEXT:    v_mul_f32_e32 v0, v0, v4

; SI-NEXT:    v_mul_f32_e32 v1, v1, v4

; SI-NEXT:    v_mul_f32_e32 v2, v2, v4

; SI-NEXT:    v_mul_f32_e32 v3, v3, v4

; SI-NEXT:    v_exp_f32_e32 v0, v0

; SI-NEXT:    v_exp_f32_e32 v1, v1

; SI-NEXT:    v_exp_f32_e32 v2, v2

; SI-NEXT:    v_exp_f32_e32 v3, v3

; SI-NEXT:    s_setpc_b64 s[30:31]
; SI-NEXT:    s_setpc_b64 s[30:31]

;
;

; VI-LABEL: v_exp_v4f16:
; VI-LABEL: v_exp_v4f16:

; VI:       ; %bb.0:
; VI:       ; %bb.0:

; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; VI-NEXT:    v_mov_b32_e32 v2, 0x3dc5
; VI-NEXT:    v_mov_b32_e32 v2, 0x3dc5

; VI-NEXT:    v_mul_f16_e32 v3, v1, v2
; VI-NEXT:    v_mul_f16_e32 v3, v1, v2

; VI-NEXT:    v_mul_f16_e32 v4, v0, v2
; VI-NEXT:    v_mul_f16_e32 v4, v0, v2

▲ Show 20 Lines • Show All 42 Lines • Show Last 20 Lines
test/CodeGen/AMDGPU/fmax_legacy.f16.ll
Show First 20 Lines • Show All 284 Lines • ▼ Show 20 Lines
; VI-NNAN-NEXT:    v_max_f16_e32 v0, v0, v2
; VI-NNAN-NEXT:    v_max_f16_e32 v0, v0, v2

; VI-NNAN-NEXT:    v_or_b32_e32 v0, v0, v5
; VI-NNAN-NEXT:    v_or_b32_e32 v0, v0, v5

; VI-NNAN-NEXT:    v_or_b32_e32 v1, v1, v4
; VI-NNAN-NEXT:    v_or_b32_e32 v1, v1, v4

; VI-NNAN-NEXT:    s_setpc_b64 s[30:31]
; VI-NNAN-NEXT:    s_setpc_b64 s[30:31]

;
;

; SI-SAFE-LABEL: test_fmax_legacy_ugt_v4f16:
; SI-SAFE-LABEL: test_fmax_legacy_ugt_v4f16:

; SI-SAFE:       ; %bb.0:
; SI-SAFE:       ; %bb.0:

; SI-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v0, v0

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v4, v4

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v1, v1

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v5, v5

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v2, v2

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v6, v6

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v3, v3
; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v3, v3

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v7, v7
; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v7, v7

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v0, v0

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v4, v4

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v1, v1

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v5, v5

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v2, v2

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v6, v6

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v3, v3

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v7, v7

; SI-SAFE-NEXT:    v_max_legacy_f32_e32 v3, v7, v3

; SI-SAFE-NEXT:    v_max_legacy_f32_e32 v2, v6, v2

; SI-SAFE-NEXT:    v_max_legacy_f32_e32 v1, v5, v1

; SI-SAFE-NEXT:    v_max_legacy_f32_e32 v0, v4, v0

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v3, v3

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v2, v2
; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v2, v2

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v6, v6

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v1, v1
; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v1, v1

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v5, v5

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v0, v0
; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v0, v0

; SI-SAFE-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v4, v4

; SI-SAFE-NEXT:    v_lshlrev_b32_e32 v1, 16, v1

; SI-SAFE-NEXT:    v_or_b32_e32 v3, v2, v3

; SI-SAFE-NEXT:    v_or_b32_e32 v1, v0, v1

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v0, v1

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v2, v3

; SI-SAFE-NEXT:    v_lshrrev_b32_e32 v1, 16, v1

; SI-SAFE-NEXT:    v_lshrrev_b32_e32 v3, 16, v3

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v1, v1

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v3, v3
; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v3, v3

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v7, v7

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v2, v2

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v6, v6

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v1, v1

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v5, v5

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v0, v0

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v4, v4

; SI-SAFE-NEXT:    v_max_legacy_f32_e32 v0, v4, v0

; SI-SAFE-NEXT:    v_max_legacy_f32_e32 v1, v5, v1

; SI-SAFE-NEXT:    v_max_legacy_f32_e32 v2, v6, v2

; SI-SAFE-NEXT:    v_max_legacy_f32_e32 v3, v7, v3

; SI-SAFE-NEXT:    s_setpc_b64 s[30:31]
; SI-SAFE-NEXT:    s_setpc_b64 s[30:31]

;
;

; SI-NNAN-LABEL: test_fmax_legacy_ugt_v4f16:
; SI-NNAN-LABEL: test_fmax_legacy_ugt_v4f16:

; SI-NNAN:       ; %bb.0:
; SI-NNAN:       ; %bb.0:

; SI-NNAN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NNAN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v4, v4

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v0, v0

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v5, v5

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v1, v1

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v6, v6

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v2, v2

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v7, v7
; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v7, v7

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v3, v3
; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v3, v3

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v4, v4
; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v6, v6

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v0, v0

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v5, v5

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v1, v1

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v6, v6

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v2, v2

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v7, v7

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v3, v3

; SI-NNAN-NEXT:    v_max_f32_e32 v3, v3, v7

; SI-NNAN-NEXT:    v_max_f32_e32 v2, v2, v6

; SI-NNAN-NEXT:    v_max_f32_e32 v1, v1, v5

; SI-NNAN-NEXT:    v_max_f32_e32 v0, v0, v4

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v3, v3

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v2, v2
; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v2, v2

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v5, v5

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v1, v1
; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v1, v1

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v4, v4

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v0, v0
; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v0, v0

; SI-NNAN-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v7, v7

; SI-NNAN-NEXT:    v_lshlrev_b32_e32 v1, 16, v1

; SI-NNAN-NEXT:    v_or_b32_e32 v3, v2, v3

; SI-NNAN-NEXT:    v_or_b32_e32 v1, v0, v1

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v0, v1

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v2, v3

; SI-NNAN-NEXT:    v_lshrrev_b32_e32 v1, 16, v1

; SI-NNAN-NEXT:    v_lshrrev_b32_e32 v3, 16, v3

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v1, v1

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v3, v3
; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v3, v3

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v6, v6

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v2, v2

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v5, v5

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v1, v1

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v4, v4

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v0, v0

; SI-NNAN-NEXT:    v_max_f32_e32 v0, v0, v4

; SI-NNAN-NEXT:    v_max_f32_e32 v1, v1, v5

; SI-NNAN-NEXT:    v_max_f32_e32 v2, v2, v6

; SI-NNAN-NEXT:    v_max_f32_e32 v3, v3, v7

; SI-NNAN-NEXT:    s_setpc_b64 s[30:31]
; SI-NNAN-NEXT:    s_setpc_b64 s[30:31]

  %cmp = fcmp ugt <4 x half> %a, %b
  %cmp = fcmp ugt <4 x half> %a, %b

  %val = select <4 x i1> %cmp, <4 x half> %a, <4 x half> %b
  %val = select <4 x i1> %cmp, <4 x half> %a, <4 x half> %b

  ret <4 x half> %val
  ret <4 x half> %val

}
}




define <8 x half> @test_fmax_legacy_ugt_v8f16(<8 x half> %a, <8 x half> %b) #0 {
define <8 x half> @test_fmax_legacy_ugt_v8f16(<8 x half> %a, <8 x half> %b) #0 {

; GFX9-SAFE-LABEL: test_fmax_legacy_ugt_v8f16:
; GFX9-SAFE-LABEL: test_fmax_legacy_ugt_v8f16:

▲ Show 20 Lines • Show All 95 Lines • ▼ Show 20 Lines
; VI-NNAN-NEXT:    v_or_b32_e32 v1, v1, v10
; VI-NNAN-NEXT:    v_or_b32_e32 v1, v1, v10

; VI-NNAN-NEXT:    v_or_b32_e32 v2, v2, v9
; VI-NNAN-NEXT:    v_or_b32_e32 v2, v2, v9

; VI-NNAN-NEXT:    v_or_b32_e32 v3, v3, v8
; VI-NNAN-NEXT:    v_or_b32_e32 v3, v3, v8

; VI-NNAN-NEXT:    s_setpc_b64 s[30:31]
; VI-NNAN-NEXT:    s_setpc_b64 s[30:31]

;
;

; SI-SAFE-LABEL: test_fmax_legacy_ugt_v8f16:
; SI-SAFE-LABEL: test_fmax_legacy_ugt_v8f16:

; SI-SAFE:       ; %bb.0:
; SI-SAFE:       ; %bb.0:

; SI-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v0, v0

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v8, v8

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v1, v1

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v9, v9

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v2, v2

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v10, v10

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v3, v3

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v11, v11

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v4, v4

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v12, v12

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v5, v5

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v13, v13

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v6, v6

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v14, v14

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v7, v7
; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v7, v7

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v15, v15
; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v15, v15

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v0, v0

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v8, v8

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v1, v1

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v9, v9

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v2, v2

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v10, v10

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v3, v3

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v11, v11

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v4, v4

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v12, v12

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v5, v5

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v13, v13

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v6, v6

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v14, v14

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v7, v7

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v15, v15

; SI-SAFE-NEXT:    v_max_legacy_f32_e32 v7, v15, v7

; SI-SAFE-NEXT:    v_max_legacy_f32_e32 v6, v14, v6

; SI-SAFE-NEXT:    v_max_legacy_f32_e32 v5, v13, v5

; SI-SAFE-NEXT:    v_max_legacy_f32_e32 v4, v12, v4

; SI-SAFE-NEXT:    v_max_legacy_f32_e32 v3, v11, v3

; SI-SAFE-NEXT:    v_max_legacy_f32_e32 v2, v10, v2

; SI-SAFE-NEXT:    v_max_legacy_f32_e32 v1, v9, v1

; SI-SAFE-NEXT:    v_max_legacy_f32_e32 v0, v8, v0

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v7, v7

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v6, v6
; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v6, v6

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v14, v14

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v5, v5
; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v5, v5

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v13, v13

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v4, v4
; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v4, v4

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v12, v12

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v3, v3
; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v3, v3

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v11, v11

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v2, v2
; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v2, v2

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v10, v10

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v1, v1
; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v1, v1

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v9, v9

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v0, v0
; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v0, v0

; SI-SAFE-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v8, v8

; SI-SAFE-NEXT:    v_lshlrev_b32_e32 v5, 16, v5

; SI-SAFE-NEXT:    v_lshlrev_b32_e32 v3, 16, v3

; SI-SAFE-NEXT:    v_lshlrev_b32_e32 v1, 16, v1

; SI-SAFE-NEXT:    v_or_b32_e32 v7, v6, v7

; SI-SAFE-NEXT:    v_or_b32_e32 v5, v4, v5

; SI-SAFE-NEXT:    v_or_b32_e32 v3, v2, v3

; SI-SAFE-NEXT:    v_or_b32_e32 v1, v0, v1

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v0, v1

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v2, v3

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v4, v5

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v6, v7

; SI-SAFE-NEXT:    v_lshrrev_b32_e32 v1, 16, v1

; SI-SAFE-NEXT:    v_lshrrev_b32_e32 v3, 16, v3

; SI-SAFE-NEXT:    v_lshrrev_b32_e32 v5, 16, v5

; SI-SAFE-NEXT:    v_lshrrev_b32_e32 v7, 16, v7

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v1, v1

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v3, v3

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v5, v5

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v7, v7
; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v7, v7

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v15, v15

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v6, v6

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v14, v14

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v5, v5

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v13, v13

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v4, v4

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v12, v12

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v3, v3

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v11, v11

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v2, v2

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v10, v10

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v1, v1

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v9, v9

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v0, v0

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v8, v8

; SI-SAFE-NEXT:    v_max_legacy_f32_e32 v0, v8, v0

; SI-SAFE-NEXT:    v_max_legacy_f32_e32 v1, v9, v1

; SI-SAFE-NEXT:    v_max_legacy_f32_e32 v2, v10, v2

; SI-SAFE-NEXT:    v_max_legacy_f32_e32 v3, v11, v3

; SI-SAFE-NEXT:    v_max_legacy_f32_e32 v4, v12, v4

; SI-SAFE-NEXT:    v_max_legacy_f32_e32 v5, v13, v5

; SI-SAFE-NEXT:    v_max_legacy_f32_e32 v6, v14, v6

; SI-SAFE-NEXT:    v_max_legacy_f32_e32 v7, v15, v7

; SI-SAFE-NEXT:    s_setpc_b64 s[30:31]
; SI-SAFE-NEXT:    s_setpc_b64 s[30:31]

;
;

; SI-NNAN-LABEL: test_fmax_legacy_ugt_v8f16:
; SI-NNAN-LABEL: test_fmax_legacy_ugt_v8f16:

; SI-NNAN:       ; %bb.0:
; SI-NNAN:       ; %bb.0:

; SI-NNAN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NNAN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v8, v8

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v0, v0

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v9, v9

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v1, v1

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v10, v10

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v2, v2

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v11, v11

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v3, v3

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v12, v12

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v4, v4

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v13, v13

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v5, v5

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v14, v14

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v6, v6

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v15, v15
; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v15, v15

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v7, v7
; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v7, v7

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v8, v8
; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v14, v14

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v0, v0

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v9, v9

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v1, v1

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v10, v10

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v2, v2

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v11, v11

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v3, v3

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v12, v12

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v4, v4

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v13, v13

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v5, v5

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v14, v14

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v6, v6

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v15, v15

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v7, v7

; SI-NNAN-NEXT:    v_max_f32_e32 v7, v7, v15

; SI-NNAN-NEXT:    v_max_f32_e32 v6, v6, v14

; SI-NNAN-NEXT:    v_max_f32_e32 v5, v5, v13

; SI-NNAN-NEXT:    v_max_f32_e32 v4, v4, v12

; SI-NNAN-NEXT:    v_max_f32_e32 v3, v3, v11

; SI-NNAN-NEXT:    v_max_f32_e32 v2, v2, v10

; SI-NNAN-NEXT:    v_max_f32_e32 v1, v1, v9

; SI-NNAN-NEXT:    v_max_f32_e32 v0, v0, v8

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v7, v7

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v6, v6
; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v6, v6

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v13, v13

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v5, v5
; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v5, v5

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v12, v12

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v4, v4
; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v4, v4

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v11, v11

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v3, v3
; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v3, v3

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v10, v10

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v2, v2
; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v2, v2

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v9, v9

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v1, v1
; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v1, v1

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v8, v8

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v0, v0
; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v0, v0

; SI-NNAN-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v15, v15

; SI-NNAN-NEXT:    v_lshlrev_b32_e32 v5, 16, v5

; SI-NNAN-NEXT:    v_lshlrev_b32_e32 v3, 16, v3

; SI-NNAN-NEXT:    v_lshlrev_b32_e32 v1, 16, v1

; SI-NNAN-NEXT:    v_or_b32_e32 v7, v6, v7

; SI-NNAN-NEXT:    v_or_b32_e32 v5, v4, v5

; SI-NNAN-NEXT:    v_or_b32_e32 v3, v2, v3

; SI-NNAN-NEXT:    v_or_b32_e32 v1, v0, v1

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v0, v1

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v2, v3

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v4, v5

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v6, v7

; SI-NNAN-NEXT:    v_lshrrev_b32_e32 v1, 16, v1

; SI-NNAN-NEXT:    v_lshrrev_b32_e32 v3, 16, v3

; SI-NNAN-NEXT:    v_lshrrev_b32_e32 v5, 16, v5

; SI-NNAN-NEXT:    v_lshrrev_b32_e32 v7, 16, v7

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v1, v1

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v3, v3

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v5, v5

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v7, v7
; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v7, v7

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v14, v14

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v6, v6

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v13, v13

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v5, v5

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v12, v12

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v4, v4

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v11, v11

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v3, v3

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v10, v10

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v2, v2

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v9, v9

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v1, v1

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v8, v8

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v0, v0

; SI-NNAN-NEXT:    v_max_f32_e32 v0, v0, v8

; SI-NNAN-NEXT:    v_max_f32_e32 v1, v1, v9

; SI-NNAN-NEXT:    v_max_f32_e32 v2, v2, v10

; SI-NNAN-NEXT:    v_max_f32_e32 v3, v3, v11

; SI-NNAN-NEXT:    v_max_f32_e32 v4, v4, v12

; SI-NNAN-NEXT:    v_max_f32_e32 v5, v5, v13

; SI-NNAN-NEXT:    v_max_f32_e32 v6, v6, v14

; SI-NNAN-NEXT:    v_max_f32_e32 v7, v7, v15

; SI-NNAN-NEXT:    s_setpc_b64 s[30:31]
; SI-NNAN-NEXT:    s_setpc_b64 s[30:31]

  %cmp = fcmp ugt <8 x half> %a, %b
  %cmp = fcmp ugt <8 x half> %a, %b

  %val = select <8 x i1> %cmp, <8 x half> %a, <8 x half> %b
  %val = select <8 x i1> %cmp, <8 x half> %a, <8 x half> %b

  ret <8 x half> %val
  ret <8 x half> %val

}
}




attributes #0 = { nounwind }
attributes #0 = { nounwind }

test/CodeGen/AMDGPU/fmin_legacy.f16.ll
Show First 20 Lines • Show All 285 Lines • ▼ Show 20 Lines
; VI-NNAN-NEXT:    v_min_f16_e32 v0, v0, v2
; VI-NNAN-NEXT:    v_min_f16_e32 v0, v0, v2

; VI-NNAN-NEXT:    v_or_b32_e32 v0, v0, v5
; VI-NNAN-NEXT:    v_or_b32_e32 v0, v0, v5

; VI-NNAN-NEXT:    v_or_b32_e32 v1, v1, v4
; VI-NNAN-NEXT:    v_or_b32_e32 v1, v1, v4

; VI-NNAN-NEXT:    s_setpc_b64 s[30:31]
; VI-NNAN-NEXT:    s_setpc_b64 s[30:31]

;
;

; SI-SAFE-LABEL: test_fmin_legacy_ule_v4f16:
; SI-SAFE-LABEL: test_fmin_legacy_ule_v4f16:

; SI-SAFE:       ; %bb.0:
; SI-SAFE:       ; %bb.0:

; SI-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v0, v0

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v4, v4

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v1, v1

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v5, v5

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v2, v2

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v6, v6

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v3, v3
; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v3, v3

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v7, v7
; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v7, v7

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v0, v0

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v4, v4

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v1, v1

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v5, v5

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v2, v2

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v6, v6

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v3, v3

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v7, v7

; SI-SAFE-NEXT:    v_min_legacy_f32_e32 v3, v7, v3

; SI-SAFE-NEXT:    v_min_legacy_f32_e32 v2, v6, v2

; SI-SAFE-NEXT:    v_min_legacy_f32_e32 v1, v5, v1

; SI-SAFE-NEXT:    v_min_legacy_f32_e32 v0, v4, v0

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v3, v3

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v2, v2
; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v2, v2

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v6, v6

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v1, v1
; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v1, v1

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v5, v5

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v0, v0
; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v0, v0

; SI-SAFE-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v4, v4

; SI-SAFE-NEXT:    v_lshlrev_b32_e32 v1, 16, v1

; SI-SAFE-NEXT:    v_or_b32_e32 v3, v2, v3

; SI-SAFE-NEXT:    v_or_b32_e32 v1, v0, v1

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v0, v1

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v2, v3

; SI-SAFE-NEXT:    v_lshrrev_b32_e32 v1, 16, v1

; SI-SAFE-NEXT:    v_lshrrev_b32_e32 v3, 16, v3

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v1, v1

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v3, v3
; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v3, v3

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v7, v7

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v2, v2

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v6, v6

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v1, v1

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v5, v5

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v0, v0

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v4, v4

; SI-SAFE-NEXT:    v_min_legacy_f32_e32 v0, v4, v0

; SI-SAFE-NEXT:    v_min_legacy_f32_e32 v1, v5, v1

; SI-SAFE-NEXT:    v_min_legacy_f32_e32 v2, v6, v2

; SI-SAFE-NEXT:    v_min_legacy_f32_e32 v3, v7, v3

; SI-SAFE-NEXT:    s_setpc_b64 s[30:31]
; SI-SAFE-NEXT:    s_setpc_b64 s[30:31]

;
;

; SI-NNAN-LABEL: test_fmin_legacy_ule_v4f16:
; SI-NNAN-LABEL: test_fmin_legacy_ule_v4f16:

; SI-NNAN:       ; %bb.0:
; SI-NNAN:       ; %bb.0:

; SI-NNAN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NNAN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v4, v4

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v0, v0

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v5, v5

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v1, v1

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v6, v6

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v2, v2

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v7, v7
; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v7, v7

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v3, v3
; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v3, v3

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v4, v4
; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v6, v6

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v0, v0

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v5, v5

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v1, v1

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v6, v6

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v2, v2

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v7, v7

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v3, v3

; SI-NNAN-NEXT:    v_min_f32_e32 v3, v3, v7

; SI-NNAN-NEXT:    v_min_f32_e32 v2, v2, v6

; SI-NNAN-NEXT:    v_min_f32_e32 v1, v1, v5

; SI-NNAN-NEXT:    v_min_f32_e32 v0, v0, v4

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v3, v3

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v2, v2
; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v2, v2

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v5, v5

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v1, v1
; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v1, v1

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v4, v4

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v0, v0
; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v0, v0

; SI-NNAN-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v7, v7

; SI-NNAN-NEXT:    v_lshlrev_b32_e32 v1, 16, v1

; SI-NNAN-NEXT:    v_or_b32_e32 v3, v2, v3

; SI-NNAN-NEXT:    v_or_b32_e32 v1, v0, v1

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v0, v1

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v2, v3

; SI-NNAN-NEXT:    v_lshrrev_b32_e32 v1, 16, v1

; SI-NNAN-NEXT:    v_lshrrev_b32_e32 v3, 16, v3

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v1, v1

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v3, v3
; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v3, v3

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v6, v6

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v2, v2

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v5, v5

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v1, v1

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v4, v4

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v0, v0

; SI-NNAN-NEXT:    v_min_f32_e32 v0, v0, v4

; SI-NNAN-NEXT:    v_min_f32_e32 v1, v1, v5

; SI-NNAN-NEXT:    v_min_f32_e32 v2, v2, v6

; SI-NNAN-NEXT:    v_min_f32_e32 v3, v3, v7

; SI-NNAN-NEXT:    s_setpc_b64 s[30:31]
; SI-NNAN-NEXT:    s_setpc_b64 s[30:31]

  %cmp = fcmp ule <4 x half> %a, %b
  %cmp = fcmp ule <4 x half> %a, %b

  %val = select <4 x i1> %cmp, <4 x half> %a, <4 x half> %b
  %val = select <4 x i1> %cmp, <4 x half> %a, <4 x half> %b

  ret <4 x half> %val
  ret <4 x half> %val

}
}




define <8 x half> @test_fmin_legacy_ule_v8f16(<8 x half> %a, <8 x half> %b) #0 {
define <8 x half> @test_fmin_legacy_ule_v8f16(<8 x half> %a, <8 x half> %b) #0 {

; GFX9-SAFE-LABEL: test_fmin_legacy_ule_v8f16:
; GFX9-SAFE-LABEL: test_fmin_legacy_ule_v8f16:

▲ Show 20 Lines • Show All 95 Lines • ▼ Show 20 Lines
; VI-NNAN-NEXT:    v_or_b32_e32 v1, v1, v10
; VI-NNAN-NEXT:    v_or_b32_e32 v1, v1, v10

; VI-NNAN-NEXT:    v_or_b32_e32 v2, v2, v9
; VI-NNAN-NEXT:    v_or_b32_e32 v2, v2, v9

; VI-NNAN-NEXT:    v_or_b32_e32 v3, v3, v8
; VI-NNAN-NEXT:    v_or_b32_e32 v3, v3, v8

; VI-NNAN-NEXT:    s_setpc_b64 s[30:31]
; VI-NNAN-NEXT:    s_setpc_b64 s[30:31]

;
;

; SI-SAFE-LABEL: test_fmin_legacy_ule_v8f16:
; SI-SAFE-LABEL: test_fmin_legacy_ule_v8f16:

; SI-SAFE:       ; %bb.0:
; SI-SAFE:       ; %bb.0:

; SI-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v0, v0

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v8, v8

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v1, v1

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v9, v9

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v2, v2

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v10, v10

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v3, v3

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v11, v11

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v4, v4

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v12, v12

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v5, v5

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v13, v13

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v6, v6

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v14, v14

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v7, v7
; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v7, v7

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v15, v15
; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v15, v15

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v0, v0

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v8, v8

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v1, v1

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v9, v9

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v2, v2

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v10, v10

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v3, v3

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v11, v11

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v4, v4

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v12, v12

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v5, v5

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v13, v13

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v6, v6

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v14, v14

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v7, v7

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v15, v15

; SI-SAFE-NEXT:    v_min_legacy_f32_e32 v7, v15, v7

; SI-SAFE-NEXT:    v_min_legacy_f32_e32 v6, v14, v6

; SI-SAFE-NEXT:    v_min_legacy_f32_e32 v5, v13, v5

; SI-SAFE-NEXT:    v_min_legacy_f32_e32 v4, v12, v4

; SI-SAFE-NEXT:    v_min_legacy_f32_e32 v3, v11, v3

; SI-SAFE-NEXT:    v_min_legacy_f32_e32 v2, v10, v2

; SI-SAFE-NEXT:    v_min_legacy_f32_e32 v1, v9, v1

; SI-SAFE-NEXT:    v_min_legacy_f32_e32 v0, v8, v0

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v7, v7

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v6, v6
; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v6, v6

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v14, v14

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v5, v5
; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v5, v5

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v13, v13

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v4, v4
; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v4, v4

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v12, v12

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v3, v3
; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v3, v3

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v11, v11

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v2, v2
; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v2, v2

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v10, v10

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v1, v1
; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v1, v1

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v9, v9

; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v0, v0
; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v0, v0

; SI-SAFE-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v8, v8

; SI-SAFE-NEXT:    v_lshlrev_b32_e32 v5, 16, v5

; SI-SAFE-NEXT:    v_lshlrev_b32_e32 v3, 16, v3

; SI-SAFE-NEXT:    v_lshlrev_b32_e32 v1, 16, v1

; SI-SAFE-NEXT:    v_or_b32_e32 v7, v6, v7

; SI-SAFE-NEXT:    v_or_b32_e32 v5, v4, v5

; SI-SAFE-NEXT:    v_or_b32_e32 v3, v2, v3

; SI-SAFE-NEXT:    v_or_b32_e32 v1, v0, v1

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v0, v1

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v2, v3

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v4, v5

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v6, v7

; SI-SAFE-NEXT:    v_lshrrev_b32_e32 v1, 16, v1

; SI-SAFE-NEXT:    v_lshrrev_b32_e32 v3, 16, v3

; SI-SAFE-NEXT:    v_lshrrev_b32_e32 v5, 16, v5

; SI-SAFE-NEXT:    v_lshrrev_b32_e32 v7, 16, v7

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v1, v1

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v3, v3

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v5, v5

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v7, v7
; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v7, v7

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v15, v15

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v6, v6

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v14, v14

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v5, v5

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v13, v13

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v4, v4

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v12, v12

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v3, v3

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v11, v11

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v2, v2

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v10, v10

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v1, v1

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v9, v9

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v0, v0

; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v8, v8

; SI-SAFE-NEXT:    v_min_legacy_f32_e32 v0, v8, v0

; SI-SAFE-NEXT:    v_min_legacy_f32_e32 v1, v9, v1

; SI-SAFE-NEXT:    v_min_legacy_f32_e32 v2, v10, v2

; SI-SAFE-NEXT:    v_min_legacy_f32_e32 v3, v11, v3

; SI-SAFE-NEXT:    v_min_legacy_f32_e32 v4, v12, v4

; SI-SAFE-NEXT:    v_min_legacy_f32_e32 v5, v13, v5

; SI-SAFE-NEXT:    v_min_legacy_f32_e32 v6, v14, v6

; SI-SAFE-NEXT:    v_min_legacy_f32_e32 v7, v15, v7

; SI-SAFE-NEXT:    s_setpc_b64 s[30:31]
; SI-SAFE-NEXT:    s_setpc_b64 s[30:31]

;
;

; SI-NNAN-LABEL: test_fmin_legacy_ule_v8f16:
; SI-NNAN-LABEL: test_fmin_legacy_ule_v8f16:

; SI-NNAN:       ; %bb.0:
; SI-NNAN:       ; %bb.0:

; SI-NNAN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NNAN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v8, v8

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v0, v0

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v9, v9

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v1, v1

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v10, v10

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v2, v2

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v11, v11

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v3, v3

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v12, v12

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v4, v4

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v13, v13

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v5, v5

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v14, v14

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v6, v6

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v15, v15
; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v15, v15

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v7, v7
; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v7, v7

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v8, v8
; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v14, v14

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v0, v0

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v9, v9

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v1, v1

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v10, v10

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v2, v2

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v11, v11

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v3, v3

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v12, v12

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v4, v4

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v13, v13

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v5, v5

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v14, v14

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v6, v6

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v15, v15

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v7, v7

; SI-NNAN-NEXT:    v_min_f32_e32 v7, v7, v15

; SI-NNAN-NEXT:    v_min_f32_e32 v6, v6, v14

; SI-NNAN-NEXT:    v_min_f32_e32 v5, v5, v13

; SI-NNAN-NEXT:    v_min_f32_e32 v4, v4, v12

; SI-NNAN-NEXT:    v_min_f32_e32 v3, v3, v11

; SI-NNAN-NEXT:    v_min_f32_e32 v2, v2, v10

; SI-NNAN-NEXT:    v_min_f32_e32 v1, v1, v9

; SI-NNAN-NEXT:    v_min_f32_e32 v0, v0, v8

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v7, v7

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v6, v6
; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v6, v6

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v13, v13

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v5, v5
; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v5, v5

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v12, v12

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v4, v4
; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v4, v4

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v11, v11

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v3, v3
; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v3, v3

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v10, v10

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v2, v2
; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v2, v2

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v9, v9

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v1, v1
; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v1, v1

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v8, v8

; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v0, v0
; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v0, v0

; SI-NNAN-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v15, v15

; SI-NNAN-NEXT:    v_lshlrev_b32_e32 v5, 16, v5

; SI-NNAN-NEXT:    v_lshlrev_b32_e32 v3, 16, v3

; SI-NNAN-NEXT:    v_lshlrev_b32_e32 v1, 16, v1

; SI-NNAN-NEXT:    v_or_b32_e32 v7, v6, v7

; SI-NNAN-NEXT:    v_or_b32_e32 v5, v4, v5

; SI-NNAN-NEXT:    v_or_b32_e32 v3, v2, v3

; SI-NNAN-NEXT:    v_or_b32_e32 v1, v0, v1

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v0, v1

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v2, v3

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v4, v5

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v6, v7

; SI-NNAN-NEXT:    v_lshrrev_b32_e32 v1, 16, v1

; SI-NNAN-NEXT:    v_lshrrev_b32_e32 v3, 16, v3

; SI-NNAN-NEXT:    v_lshrrev_b32_e32 v5, 16, v5

; SI-NNAN-NEXT:    v_lshrrev_b32_e32 v7, 16, v7

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v1, v1

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v3, v3

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v5, v5

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v7, v7
; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v7, v7

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v14, v14

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v6, v6

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v13, v13

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v5, v5

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v12, v12

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v4, v4

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v11, v11

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v3, v3

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v10, v10

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v2, v2

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v9, v9

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v1, v1

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v8, v8

; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v0, v0

; SI-NNAN-NEXT:    v_min_f32_e32 v0, v0, v8

; SI-NNAN-NEXT:    v_min_f32_e32 v1, v1, v9

; SI-NNAN-NEXT:    v_min_f32_e32 v2, v2, v10

; SI-NNAN-NEXT:    v_min_f32_e32 v3, v3, v11

; SI-NNAN-NEXT:    v_min_f32_e32 v4, v4, v12

; SI-NNAN-NEXT:    v_min_f32_e32 v5, v5, v13

; SI-NNAN-NEXT:    v_min_f32_e32 v6, v6, v14

; SI-NNAN-NEXT:    v_min_f32_e32 v7, v7, v15

; SI-NNAN-NEXT:    s_setpc_b64 s[30:31]
; SI-NNAN-NEXT:    s_setpc_b64 s[30:31]

  %cmp = fcmp ule <8 x half> %a, %b
  %cmp = fcmp ule <8 x half> %a, %b

  %val = select <8 x i1> %cmp, <8 x half> %a, <8 x half> %b
  %val = select <8 x i1> %cmp, <8 x half> %a, <8 x half> %b

  ret <8 x half> %val
  ret <8 x half> %val

}
}




attributes #0 = { nounwind }
attributes #0 = { nounwind }

test/CodeGen/AMDGPU/reduction.ll
Show First 20 Lines • Show All 41 Lines • ▼ Show 20 Lines
; GCN-LABEL: {{^}}reduction_fsub_v4f16_preserve_fmf:
; GCN-LABEL: {{^}}reduction_fsub_v4f16_preserve_fmf:

; GFX9: s_waitcnt
; GFX9: s_waitcnt

; GFX9-NEXT: v_pk_add_f16 v0, v0, v1 neg_lo:[0,1] neg_hi:[0,1]{{$}}
; GFX9-NEXT: v_pk_add_f16 v0, v0, v1 neg_lo:[0,1] neg_hi:[0,1]{{$}}

; GFX9-NEXT: v_sub_f16_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX9-NEXT: v_sub_f16_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD

; GFX9-NEXT: s_setpc_b64
; GFX9-NEXT: s_setpc_b64




; VI: s_waitcnt
; VI: s_waitcnt

; VI-NEXT: v_sub_f16_sdwa v2, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; VI-NEXT: v_sub_f16_sdwa v2, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1

; VI-NEXT: v_sub_f16_e32 v0, v0, v1
; VI-NEXT: v_sub_f16_e32 v0, v1, v0

; VI-NEXT: v_sub_f16_e32 v0, v2, v0
; VI-NEXT: v_add_f16_e32 v0, v2, v0

; VI-NEXT: s_setpc_b64
; VI-NEXT: s_setpc_b64

define half @reduction_fsub_v4f16_preserve_fmf(<4 x half> %vec4) {
define half @reduction_fsub_v4f16_preserve_fmf(<4 x half> %vec4) {

entry:
entry:

  %rdx.shuf = shufflevector <4 x half> %vec4, <4 x half> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
  %rdx.shuf = shufflevector <4 x half> %vec4, <4 x half> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>

  %bin.rdx = fsub nsz <4 x half> %vec4, %rdx.shuf
  %bin.rdx = fsub nsz <4 x half> %vec4, %rdx.shuf

  %rdx.shuf1 = shufflevector <4 x half> %bin.rdx, <4 x half> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
  %rdx.shuf1 = shufflevector <4 x half> %bin.rdx, <4 x half> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>

  %bin.rdx2 = fsub nsz <4 x half> %bin.rdx, %rdx.shuf1
  %bin.rdx2 = fsub nsz <4 x half> %bin.rdx, %rdx.shuf1

  %res = extractelement <4 x half> %bin.rdx2, i32 0
  %res = extractelement <4 x half> %bin.rdx2, i32 0

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