This is an archive of the discontinued LLVM Phabricator instance.

[X86][BtVer2] Remove wrong ReadAdvance from AVX vbroadcast(ss|sd|F128) instructions.
ClosedPublic

Authored by andreadb on Aug 31 2018, 4:23 AM.

Details

Summary

The presence of a ReadAdvance for the input operand at index 0 is problematic (as shown by the diff in the llvm-mca test).
A broadcast cannot start executing if the base address for the load hasn't been computed yet.

In the llvm-mca example, the VBROADCASTSS has to wait on the write from LEAQ. If we apply ReadAdvance to the register read associated with the base address, then we wrongly assume that the load can start 3 cycles in advance.

Diff Detail

Event Timeline

andreadb created this revision.Aug 31 2018, 4:23 AM
spatel accepted this revision.Aug 31 2018, 8:42 AM

LGTM. I did a quick grep of the other sched models, and I don't see this bug copy-pasted for other CPUs (with broadcast at least).

This revision is now accepted and ready to land.Aug 31 2018, 8:42 AM
This revision was automatically updated to reflect the committed changes.