DAG: Check transformed type for forming fminnum/fmaxnum from vselect

[arsenm]

Summary

Follow up to r340655 to fix vector types which are split.

[nhaehnle]

Nice catch. One suggestion for improvement, apart from that LGTM.

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

7052

Maybe rename to TargetVT or TransformedVT? After all, this VT isn't necessarily legal...

[arsenm]

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

7052

I think it is?

[arsenm]

r340766

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

 /// Generate Min/Max node
 static SDValue combineMinNumMaxNum(const SDLoc &DL, EVT VT, SDValue LHS,
                                    SDValue RHS, SDValue True, SDValue False,
                                    ISD::CondCode CC, const TargetLowering &TLI,
                                    SelectionDAG &DAG) {
   if (!(LHS == True && RHS == False) && !(LHS == False && RHS == True))
     return SDValue();
 
+  EVT LegalVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
   switch (CC) {
   case ISD::SETOLT:
   case ISD::SETOLE:
   case ISD::SETLT:
   case ISD::SETLE:
   case ISD::SETULT:
   case ISD::SETULE: {
     unsigned Opcode = (LHS == True) ? ISD::FMINNUM : ISD::FMAXNUM;
-    if (TLI.isOperationLegalOrCustom(Opcode, VT))
+    if (TLI.isOperationLegalOrCustom(Opcode, LegalVT))
       return DAG.getNode(Opcode, DL, VT, LHS, RHS);
     return SDValue();
   }
   case ISD::SETOGT:
   case ISD::SETOGE:
   case ISD::SETGT:
   case ISD::SETGE:
   case ISD::SETUGT:
   case ISD::SETUGE: {
     unsigned Opcode = (LHS == True) ? ISD::FMAXNUM : ISD::FMINNUM;
-    if (TLI.isOperationLegalOrCustom(Opcode, VT))
+    if (TLI.isOperationLegalOrCustom(Opcode, LegalVT))
       return DAG.getNode(Opcode, DL, VT, LHS, RHS);
     return SDValue();
   }
   default:
     return SDValue();
   }
 }
 

test/CodeGen/AMDGPU/fmax_legacy.f16.ll

 ; GFX9-SAFE-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc
 ; GFX9-SAFE-NEXT:    v_and_b32_e32 v0, 0xffff, v0
 ; GFX9-SAFE-NEXT:    v_lshl_or_b32 v0, v4, 16, v0
 ; GFX9-SAFE-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-NNAN-LABEL: test_fmax_legacy_ugt_v3f16:
 ; GFX9-NNAN:       ; %bb.0:
 ; GFX9-NNAN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NNAN-NEXT:    v_max_f16_sdwa v4, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9-NNAN-NEXT:    v_max_f16_e32 v0, v0, v2
-; GFX9-NNAN-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX9-NNAN-NEXT:    v_max_f16_e32 v1, v1, v3
-; GFX9-NNAN-NEXT:    v_lshl_or_b32 v0, v4, 16, v0
+; GFX9-NNAN-NEXT:    v_pk_max_f16 v1, v1, v3
+; GFX9-NNAN-NEXT:    v_pk_max_f16 v0, v0, v2
 ; GFX9-NNAN-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; VI-SAFE-LABEL: test_fmax_legacy_ugt_v3f16:
 ; VI-SAFE:       ; %bb.0:
 ; VI-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-SAFE-NEXT:    v_lshrrev_b32_e32 v4, 16, v2
 ; VI-SAFE-NEXT:    v_lshrrev_b32_e32 v5, 16, v0
 ; VI-SAFE-NEXT:    v_cmp_nle_f16_e32 vcc, v5, v4

 ; GFX9-SAFE-NEXT:    v_lshl_or_b32 v1, v10, 16, v1
 ; GFX9-SAFE-NEXT:    v_lshl_or_b32 v2, v12, 16, v2
 ; GFX9-SAFE-NEXT:    v_lshl_or_b32 v3, v14, 16, v3
 ; GFX9-SAFE-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-NNAN-LABEL: test_fmax_legacy_ugt_v8f16:
 ; GFX9-NNAN:       ; %bb.0:
 ; GFX9-NNAN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NNAN-NEXT:    v_max_f16_sdwa v8, v3, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9-NNAN-NEXT:    v_max_f16_sdwa v9, v2, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9-NNAN-NEXT:    v_max_f16_sdwa v10, v1, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9-NNAN-NEXT:    v_max_f16_sdwa v11, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9-NNAN-NEXT:    v_max_f16_e32 v0, v0, v4
-; GFX9-NNAN-NEXT:    v_mov_b32_e32 v4, 0xffff
-; GFX9-NNAN-NEXT:    v_max_f16_e32 v3, v3, v7
-; GFX9-NNAN-NEXT:    v_max_f16_e32 v2, v2, v6
-; GFX9-NNAN-NEXT:    v_max_f16_e32 v1, v1, v5
-; GFX9-NNAN-NEXT:    v_and_b32_e32 v0, v4, v0
-; GFX9-NNAN-NEXT:    v_and_b32_e32 v1, v4, v1
-; GFX9-NNAN-NEXT:    v_and_b32_e32 v2, v4, v2
-; GFX9-NNAN-NEXT:    v_and_b32_e32 v3, v4, v3
-; GFX9-NNAN-NEXT:    v_lshl_or_b32 v0, v11, 16, v0
-; GFX9-NNAN-NEXT:    v_lshl_or_b32 v1, v10, 16, v1
-; GFX9-NNAN-NEXT:    v_lshl_or_b32 v2, v9, 16, v2
-; GFX9-NNAN-NEXT:    v_lshl_or_b32 v3, v8, 16, v3
+; GFX9-NNAN-NEXT:    v_pk_max_f16 v0, v0, v4
+; GFX9-NNAN-NEXT:    v_pk_max_f16 v1, v1, v5
+; GFX9-NNAN-NEXT:    v_pk_max_f16 v2, v2, v6
+; GFX9-NNAN-NEXT:    v_pk_max_f16 v3, v3, v7
 ; GFX9-NNAN-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; VI-SAFE-LABEL: test_fmax_legacy_ugt_v8f16:
 ; VI-SAFE:       ; %bb.0:
 ; VI-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-SAFE-NEXT:    v_lshrrev_b32_e32 v14, 16, v7
 ; VI-SAFE-NEXT:    v_lshrrev_b32_e32 v15, 16, v3
 ; VI-SAFE-NEXT:    v_cmp_nle_f16_e32 vcc, v15, v14

test/CodeGen/AMDGPU/fmin_legacy.f16.ll

 ; GFX9-SAFE-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc
 ; GFX9-SAFE-NEXT:    v_and_b32_e32 v0, 0xffff, v0
 ; GFX9-SAFE-NEXT:    v_lshl_or_b32 v0, v4, 16, v0
 ; GFX9-SAFE-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-NNAN-LABEL: test_fmin_legacy_ule_v3f16:
 ; GFX9-NNAN:       ; %bb.0:
 ; GFX9-NNAN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NNAN-NEXT:    v_min_f16_sdwa v4, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9-NNAN-NEXT:    v_min_f16_e32 v0, v0, v2
-; GFX9-NNAN-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX9-NNAN-NEXT:    v_min_f16_e32 v1, v1, v3
-; GFX9-NNAN-NEXT:    v_lshl_or_b32 v0, v4, 16, v0
+; GFX9-NNAN-NEXT:    v_pk_min_f16 v1, v1, v3
+; GFX9-NNAN-NEXT:    v_pk_min_f16 v0, v0, v2
 ; GFX9-NNAN-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; VI-SAFE-LABEL: test_fmin_legacy_ule_v3f16:
 ; VI-SAFE:       ; %bb.0:
 ; VI-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-SAFE-NEXT:    v_lshrrev_b32_e32 v4, 16, v2
 ; VI-SAFE-NEXT:    v_lshrrev_b32_e32 v5, 16, v0
 ; VI-SAFE-NEXT:    v_cmp_ngt_f16_e32 vcc, v5, v4

 ; GFX9-SAFE-NEXT:    v_lshl_or_b32 v1, v10, 16, v1
 ; GFX9-SAFE-NEXT:    v_lshl_or_b32 v2, v12, 16, v2
 ; GFX9-SAFE-NEXT:    v_lshl_or_b32 v3, v14, 16, v3
 ; GFX9-SAFE-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-NNAN-LABEL: test_fmin_legacy_ule_v8f16:
 ; GFX9-NNAN:       ; %bb.0:
 ; GFX9-NNAN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NNAN-NEXT:    v_min_f16_sdwa v8, v3, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9-NNAN-NEXT:    v_min_f16_sdwa v9, v2, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9-NNAN-NEXT:    v_min_f16_sdwa v10, v1, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9-NNAN-NEXT:    v_min_f16_sdwa v11, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9-NNAN-NEXT:    v_min_f16_e32 v0, v0, v4
-; GFX9-NNAN-NEXT:    v_mov_b32_e32 v4, 0xffff
-; GFX9-NNAN-NEXT:    v_min_f16_e32 v3, v3, v7
-; GFX9-NNAN-NEXT:    v_min_f16_e32 v2, v2, v6
-; GFX9-NNAN-NEXT:    v_min_f16_e32 v1, v1, v5
-; GFX9-NNAN-NEXT:    v_and_b32_e32 v0, v4, v0
-; GFX9-NNAN-NEXT:    v_and_b32_e32 v1, v4, v1
-; GFX9-NNAN-NEXT:    v_and_b32_e32 v2, v4, v2
-; GFX9-NNAN-NEXT:    v_and_b32_e32 v3, v4, v3
-; GFX9-NNAN-NEXT:    v_lshl_or_b32 v0, v11, 16, v0
-; GFX9-NNAN-NEXT:    v_lshl_or_b32 v1, v10, 16, v1
-; GFX9-NNAN-NEXT:    v_lshl_or_b32 v2, v9, 16, v2
-; GFX9-NNAN-NEXT:    v_lshl_or_b32 v3, v8, 16, v3
+; GFX9-NNAN-NEXT:    v_pk_min_f16 v0, v0, v4
+; GFX9-NNAN-NEXT:    v_pk_min_f16 v1, v1, v5
+; GFX9-NNAN-NEXT:    v_pk_min_f16 v2, v2, v6
+; GFX9-NNAN-NEXT:    v_pk_min_f16 v3, v3, v7
 ; GFX9-NNAN-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; VI-SAFE-LABEL: test_fmin_legacy_ule_v8f16:
 ; VI-SAFE:       ; %bb.0:
 ; VI-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-SAFE-NEXT:    v_lshrrev_b32_e32 v14, 16, v7
 ; VI-SAFE-NEXT:    v_lshrrev_b32_e32 v15, 16, v3
 ; VI-SAFE-NEXT:    v_cmp_ngt_f16_e32 vcc, v15, v14