[RISCV] atomic_store_nn have a different layout to regular store

[rogfer01]

Summary

We cannot directy reuse the patters of StPat because for some reason the store DAG node and the atomic_store_nn DAG nodes put the ptr and the value in different positions. Currently we attempt to store the address to an address formed by the value.

[rogfer01]

lib/Target/RISCV/RISCVInstrInfoA.td

47 ↗

(On Diff #162378)

My tblgen-fu is not great but perhaps we can swap the operands before using the original StPat, without having to repeat them here.

[asb]

Really good catch - thanks for the fix!

lib/Target/RISCV/RISCVInstrInfoA.td

106 ↗

(On Diff #162378)

Could you fix the extra whitespace after atomic_store_16, while you're doing this? i.e. ensuring SB/SH/SW are aligned.

[rogfer01]

Thanks for the prompt review @asb!

I'll commit this soon.

[rogfer01]

ChangeLog:

• Align syntax

llvm/trunk/lib/Target/RISCV/RISCVInstrInfoA.td

 
 multiclass AMO_rr_aq_rl<bits<5> funct5, bits<3> funct3, string opcodestr> {
   def ""     : AMO_rr<funct5, 0, 0, funct3, opcodestr>;
   def _AQ    : AMO_rr<funct5, 1, 0, funct3, opcodestr # ".aq">;
   def _RL    : AMO_rr<funct5, 0, 1, funct3, opcodestr # ".rl">;
   def _AQ_RL : AMO_rr<funct5, 1, 1, funct3, opcodestr # ".aqrl">;
 }
 
+multiclass AtomicStPat<PatFrag StoreOp, RVInst Inst, RegisterClass StTy> {
+  def : Pat<(StoreOp GPR:$rs1, StTy:$rs2), (Inst StTy:$rs2, GPR:$rs1, 0)>;
+  def : Pat<(StoreOp AddrFI:$rs1, StTy:$rs2), (Inst StTy:$rs2, AddrFI:$rs1, 0)>;
+  def : Pat<(StoreOp (add GPR:$rs1, simm12:$imm12), StTy:$rs2),
+            (Inst StTy:$rs2, GPR:$rs1, simm12:$imm12)>;
+  def : Pat<(StoreOp (add AddrFI:$rs1, simm12:$imm12), StTy:$rs2),
+            (Inst StTy:$rs2, AddrFI:$rs1, simm12:$imm12)>;
+  def : Pat<(StoreOp (IsOrAdd AddrFI:$rs1, simm12:$imm12), StTy:$rs2),
+            (Inst StTy:$rs2, AddrFI:$rs1, simm12:$imm12)>;
+}
+
 //===----------------------------------------------------------------------===//
 // Instructions
 //===----------------------------------------------------------------------===//
 
 let Predicates = [HasStdExtA] in {
 defm LR_W       : LR_r_aq_rl<0b010, "lr.w">;
 defm SC_W       : AMO_rr_aq_rl<0b00011, 0b010, "sc.w">;
 defm AMOSWAP_W  : AMO_rr_aq_rl<0b00001, 0b010, "amoswap.w">;

 
 // Fences will be inserted for atomic load/stores according to the logic in
 // RISCVTargetLowering::{emitLeadingFence,emitTrailingFence}.
 
 defm : LdPat<atomic_load_8,  LB>;
 defm : LdPat<atomic_load_16, LH>;
 defm : LdPat<atomic_load_32, LW>;
 
-defm : StPat<atomic_store_8,  SB, GPR>;
-defm : StPat<atomic_store_16,  SH, GPR>;
-defm : StPat<atomic_store_32, SW, GPR>;
-} // Predicates = [HasStdExtF]
+defm : AtomicStPat<atomic_store_8,  SB, GPR>;
+defm : AtomicStPat<atomic_store_16, SH, GPR>;
+defm : AtomicStPat<atomic_store_32, SW, GPR>;
+} // Predicates = [HasStdExtA]

llvm/trunk/test/CodeGen/RISCV/atomic-load-store.ll

 ; RV32I-NEXT:    mv a2, zero
 ; RV32I-NEXT:    call __atomic_store_1
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV32IA-LABEL: atomic_store_i8_unordered:
 ; RV32IA:       # %bb.0:
-; RV32IA-NEXT:    sb a0, 0(a1)
+; RV32IA-NEXT:    sb a1, 0(a0)
 ; RV32IA-NEXT:    ret
   store atomic i8 %b, i8* %a unordered, align 1
   ret void
 }
 
 define void @atomic_store_i8_monotonic(i8 *%a, i8 %b) nounwind {
 ; RV32I-LABEL: atomic_store_i8_monotonic:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
 ; RV32I-NEXT:    mv a2, zero
 ; RV32I-NEXT:    call __atomic_store_1
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV32IA-LABEL: atomic_store_i8_monotonic:
 ; RV32IA:       # %bb.0:
-; RV32IA-NEXT:    sb a0, 0(a1)
+; RV32IA-NEXT:    sb a1, 0(a0)
 ; RV32IA-NEXT:    ret
   store atomic i8 %b, i8* %a monotonic, align 1
   ret void
 }
 
 define void @atomic_store_i8_release(i8 *%a, i8 %b) nounwind {
 ; RV32I-LABEL: atomic_store_i8_release:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
 ; RV32I-NEXT:    addi a2, zero, 3
 ; RV32I-NEXT:    call __atomic_store_1
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV32IA-LABEL: atomic_store_i8_release:
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    fence rw, w
-; RV32IA-NEXT:    sb a0, 0(a1)
+; RV32IA-NEXT:    sb a1, 0(a0)
 ; RV32IA-NEXT:    ret
   store atomic i8 %b, i8* %a release, align 1
   ret void
 }
 
 define void @atomic_store_i8_seq_cst(i8 *%a, i8 %b) nounwind {
 ; RV32I-LABEL: atomic_store_i8_seq_cst:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
 ; RV32I-NEXT:    addi a2, zero, 5
 ; RV32I-NEXT:    call __atomic_store_1
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV32IA-LABEL: atomic_store_i8_seq_cst:
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    fence rw, w
-; RV32IA-NEXT:    sb a0, 0(a1)
+; RV32IA-NEXT:    sb a1, 0(a0)
 ; RV32IA-NEXT:    ret
   store atomic i8 %b, i8* %a seq_cst, align 1
   ret void
 }
 
 define void @atomic_store_i16_unordered(i16 *%a, i16 %b) nounwind {
 ; RV32I-LABEL: atomic_store_i16_unordered:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
 ; RV32I-NEXT:    mv a2, zero
 ; RV32I-NEXT:    call __atomic_store_2
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV32IA-LABEL: atomic_store_i16_unordered:
 ; RV32IA:       # %bb.0:
-; RV32IA-NEXT:    sh a0, 0(a1)
+; RV32IA-NEXT:    sh a1, 0(a0)
 ; RV32IA-NEXT:    ret
   store atomic i16 %b, i16* %a unordered, align 2
   ret void
 }
 
 define void @atomic_store_i16_monotonic(i16 *%a, i16 %b) nounwind {
 ; RV32I-LABEL: atomic_store_i16_monotonic:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
 ; RV32I-NEXT:    mv a2, zero
 ; RV32I-NEXT:    call __atomic_store_2
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV32IA-LABEL: atomic_store_i16_monotonic:
 ; RV32IA:       # %bb.0:
-; RV32IA-NEXT:    sh a0, 0(a1)
+; RV32IA-NEXT:    sh a1, 0(a0)
 ; RV32IA-NEXT:    ret
   store atomic i16 %b, i16* %a monotonic, align 2
   ret void
 }
 
 define void @atomic_store_i16_release(i16 *%a, i16 %b) nounwind {
 ; RV32I-LABEL: atomic_store_i16_release:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
 ; RV32I-NEXT:    addi a2, zero, 3
 ; RV32I-NEXT:    call __atomic_store_2
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV32IA-LABEL: atomic_store_i16_release:
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    fence rw, w
-; RV32IA-NEXT:    sh a0, 0(a1)
+; RV32IA-NEXT:    sh a1, 0(a0)
 ; RV32IA-NEXT:    ret
   store atomic i16 %b, i16* %a release, align 2
   ret void
 }
 
 define void @atomic_store_i16_seq_cst(i16 *%a, i16 %b) nounwind {
 ; RV32I-LABEL: atomic_store_i16_seq_cst:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
 ; RV32I-NEXT:    addi a2, zero, 5
 ; RV32I-NEXT:    call __atomic_store_2
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV32IA-LABEL: atomic_store_i16_seq_cst:
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    fence rw, w
-; RV32IA-NEXT:    sh a0, 0(a1)
+; RV32IA-NEXT:    sh a1, 0(a0)
 ; RV32IA-NEXT:    ret
   store atomic i16 %b, i16* %a seq_cst, align 2
   ret void
 }
 
 define void @atomic_store_i32_unordered(i32 *%a, i32 %b) nounwind {
 ; RV32I-LABEL: atomic_store_i32_unordered:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
 ; RV32I-NEXT:    mv a2, zero
 ; RV32I-NEXT:    call __atomic_store_4
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV32IA-LABEL: atomic_store_i32_unordered:
 ; RV32IA:       # %bb.0:
-; RV32IA-NEXT:    sw a0, 0(a1)
+; RV32IA-NEXT:    sw a1, 0(a0)
 ; RV32IA-NEXT:    ret
   store atomic i32 %b, i32* %a unordered, align 4
   ret void
 }
 
 define void @atomic_store_i32_monotonic(i32 *%a, i32 %b) nounwind {
 ; RV32I-LABEL: atomic_store_i32_monotonic:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
 ; RV32I-NEXT:    mv a2, zero
 ; RV32I-NEXT:    call __atomic_store_4
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV32IA-LABEL: atomic_store_i32_monotonic:
 ; RV32IA:       # %bb.0:
-; RV32IA-NEXT:    sw a0, 0(a1)
+; RV32IA-NEXT:    sw a1, 0(a0)
 ; RV32IA-NEXT:    ret
   store atomic i32 %b, i32* %a monotonic, align 4
   ret void
 }
 
 define void @atomic_store_i32_release(i32 *%a, i32 %b) nounwind {
 ; RV32I-LABEL: atomic_store_i32_release:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
 ; RV32I-NEXT:    addi a2, zero, 3
 ; RV32I-NEXT:    call __atomic_store_4
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV32IA-LABEL: atomic_store_i32_release:
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    fence rw, w
-; RV32IA-NEXT:    sw a0, 0(a1)
+; RV32IA-NEXT:    sw a1, 0(a0)
 ; RV32IA-NEXT:    ret
   store atomic i32 %b, i32* %a release, align 4
   ret void
 }
 
 define void @atomic_store_i32_seq_cst(i32 *%a, i32 %b) nounwind {
 ; RV32I-LABEL: atomic_store_i32_seq_cst:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
 ; RV32I-NEXT:    addi a2, zero, 5
 ; RV32I-NEXT:    call __atomic_store_4
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV32IA-LABEL: atomic_store_i32_seq_cst:
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    fence rw, w
-; RV32IA-NEXT:    sw a0, 0(a1)
+; RV32IA-NEXT:    sw a1, 0(a0)
 ; RV32IA-NEXT:    ret
   store atomic i32 %b, i32* %a seq_cst, align 4
   ret void
 }
 
 define void @atomic_store_i64_unordered(i64 *%a, i64 %b) nounwind {
 ; RV32I-LABEL: atomic_store_i64_unordered:
 ; RV32I:       # %bb.0: