This is an archive of the discontinued LLVM Phabricator instance.

Differential D51182

[WebAssembly] Added default stack-only instruction mode for MC.
AbandonedPublic

Authored by aardappel on Aug 23 2018, 2:10 PM.

Details

Reviewers
dschuff
sunfish
Summary

Made it convert from register to stack based instructions, and removed the registers.
Fixes to related code that was expecting register based instructions.
Added the correct testing flag to all tests, depending on what the
format they were expecting so far.
Translated one test to stack format as example: reg-stackify-stack.ll

tested:
llvm-lit -v find test -name WebAssembly
unittests/MC/*

Diff Detail

Event Timeline

aardappel created this revision.Aug 23 2018, 2:10 PM
Harbormaster completed remote builds in B21848: Diff 162264.Aug 23 2018, 2:10 PM
aardappel added a comment.Aug 23 2018, 2:11 PM

Apologies, this is still WiP

aheejin added inline comments.Aug 23 2018, 2:13 PM
test/CodeGen/WebAssembly/exception.ll
63

Fixed separately in rL339736.

aardappel abandoned this revision.May 7 2020, 3:24 PM

Obsolete, fixed elsewhere since.

Herald added a project: Restricted Project. · View Herald TranscriptMay 7 2020, 3:24 PM

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Diff 162264

lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp

Show All 28 Lines
#include "llvm/Support/TargetRegistry.h" #include "llvm/Support/TargetRegistry.h"
using namespace llvm; using namespace llvm;
#define DEBUG_TYPE "wasm-asm-parser" #define DEBUG_TYPE "wasm-asm-parser"
namespace { namespace {
// We store register types as SimpleValueType to retain SIMD layout
// information, but must also be able to supply them as the (unnamed)
// register enum from WebAssemblyRegisterInfo.td/.inc.
static unsigned MVTToWasmReg(MVT::SimpleValueType Type) {
switch(Type) {
case MVT::i32: return WebAssembly::I32_0;
case MVT::i64: return WebAssembly::I64_0;
case MVT::f32: return WebAssembly::F32_0;
case MVT::f64: return WebAssembly::F64_0;
case MVT::v16i8: return WebAssembly::V128_0;
case MVT::v8i16: return WebAssembly::V128_0;
case MVT::v4i32: return WebAssembly::V128_0;
case MVT::v4f32: return WebAssembly::V128_0;
default: return MVT::INVALID_SIMPLE_VALUE_TYPE;
}
}
/// WebAssemblyOperand - Instances of this class represent the operands in a /// WebAssemblyOperand - Instances of this class represent the operands in a
/// parsed WASM machine instruction. /// parsed WASM machine instruction.
struct WebAssemblyOperand : public MCParsedAsmOperand { struct WebAssemblyOperand : public MCParsedAsmOperand {
enum KindTy { Token, Local, Stack, Integer, Float, Symbol } Kind; enum KindTy { Token, Integer, Float, Symbol } Kind;
SMLoc StartLoc, EndLoc; SMLoc StartLoc, EndLoc;
struct TokOp { struct TokOp {
StringRef Tok; StringRef Tok;
}; };
struct RegOp {
// This is a (virtual) local or stack register represented as 0..
unsigned RegNo;
// In most targets, the register number also encodes the type, but for
// wasm we have to track that seperately since we have an unbounded
// number of registers.
// This has the unfortunate side effect that we supply a different value
// to the table-gen matcher at different times in the process (when it
// calls getReg() or addRegOperands().
// TODO: While this works, it feels brittle. and would be nice to clean up.
MVT::SimpleValueType Type;
};
struct IntOp { struct IntOp {
int64_t Val; int64_t Val;
}; };
struct FltOp { struct FltOp {
double Val; double Val;
}; };
struct SymOp { struct SymOp {
const MCExpr *Exp; const MCExpr *Exp;
}; };
union { union {
struct TokOp Tok; struct TokOp Tok;
struct RegOp Reg;
struct IntOp Int; struct IntOp Int;
struct FltOp Flt; struct FltOp Flt;
struct SymOp Sym; struct SymOp Sym;
}; };
WebAssemblyOperand(KindTy K, SMLoc Start, SMLoc End, TokOp T) WebAssemblyOperand(KindTy K, SMLoc Start, SMLoc End, TokOp T)
: Kind(K), StartLoc(Start), EndLoc(End), Tok(T) {} : Kind(K), StartLoc(Start), EndLoc(End), Tok(T) {}
WebAssemblyOperand(KindTy K, SMLoc Start, SMLoc End, RegOp R)
: Kind(K), StartLoc(Start), EndLoc(End), Reg(R) {}
WebAssemblyOperand(KindTy K, SMLoc Start, SMLoc End, IntOp I) WebAssemblyOperand(KindTy K, SMLoc Start, SMLoc End, IntOp I)
: Kind(K), StartLoc(Start), EndLoc(End), Int(I) {} : Kind(K), StartLoc(Start), EndLoc(End), Int(I) {}
WebAssemblyOperand(KindTy K, SMLoc Start, SMLoc End, FltOp F) WebAssemblyOperand(KindTy K, SMLoc Start, SMLoc End, FltOp F)
: Kind(K), StartLoc(Start), EndLoc(End), Flt(F) {} : Kind(K), StartLoc(Start), EndLoc(End), Flt(F) {}
WebAssemblyOperand(KindTy K, SMLoc Start, SMLoc End, SymOp S) WebAssemblyOperand(KindTy K, SMLoc Start, SMLoc End, SymOp S)
: Kind(K), StartLoc(Start), EndLoc(End), Sym(S) {} : Kind(K), StartLoc(Start), EndLoc(End), Sym(S) {}
bool isToken() const override { return Kind == Token; } bool isToken() const override { return Kind == Token; }
bool isImm() const override { return Kind == Integer || bool isImm() const override { return Kind == Integer ||
Kind == Float || Kind == Float ||
Kind == Symbol; } Kind == Symbol; }
bool isReg() const override { return Kind == Local || Kind == Stack; }
bool isMem() const override { return false; } bool isMem() const override { return false; }
bool isReg() const override { return false; }
unsigned getReg() const override { unsigned getReg() const override {
assert(isReg()); llvm_unreachable("Assembly inspects a register operand");
// This is called from the tablegen matcher (MatchInstructionImpl) return 0;
// where it expects to match the type of register, see RegOp above.
return MVTToWasmReg(Reg.Type);
} }
StringRef getToken() const { StringRef getToken() const {
assert(isToken()); assert(isToken());
return Tok.Tok; return Tok.Tok;
} }
SMLoc getStartLoc() const override { return StartLoc; } SMLoc getStartLoc() const override { return StartLoc; }
SMLoc getEndLoc() const override { return EndLoc; } SMLoc getEndLoc() const override { return EndLoc; }
void addRegOperands(MCInst &Inst, unsigned N) const { void addRegOperands(MCInst &, unsigned) const {
assert(N == 1 && "Invalid number of operands!"); // Required by the assembly matcher.
assert(isReg() && "Not a register operand!"); llvm_unreachable("Assembly matcher creates register operands");
// This is called from the tablegen matcher (MatchInstructionImpl)
// where it expects to output the actual register index, see RegOp above.
unsigned R = Reg.RegNo;
if (Kind == Stack) {
// A stack register is represented as a large negative number.
// See WebAssemblyRegNumbering::runOnMachineFunction and
// getWARegStackId for why this | is needed.
R |= INT32_MIN;
}
Inst.addOperand(MCOperand::createReg(R));
} }
void addImmOperands(MCInst &Inst, unsigned N) const { void addImmOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!"); assert(N == 1 && "Invalid number of operands!");
if (Kind == Integer) if (Kind == Integer)
Inst.addOperand(MCOperand::createImm(Int.Val)); Inst.addOperand(MCOperand::createImm(Int.Val));
else if (Kind == Float) else if (Kind == Float)
Inst.addOperand(MCOperand::createFPImm(Flt.Val)); Inst.addOperand(MCOperand::createFPImm(Flt.Val));
else if (Kind == Symbol) else if (Kind == Symbol)
Inst.addOperand(MCOperand::createExpr(Sym.Exp)); Inst.addOperand(MCOperand::createExpr(Sym.Exp));
else else
llvm_unreachable("Should be immediate or symbol!"); llvm_unreachable("Should be immediate or symbol!");
} }
void print(raw_ostream &OS) const override { void print(raw_ostream &OS) const override {
switch (Kind) { switch (Kind) {
case Token: case Token:
OS << "Tok:" << Tok.Tok; OS << "Tok:" << Tok.Tok;
break; break;
case Local:
OS << "Loc:" << Reg.RegNo << ":" << static_cast<int>(Reg.Type);
break;
case Stack:
OS << "Stk:" << Reg.RegNo << ":" << static_cast<int>(Reg.Type);
break;
case Integer: case Integer:
OS << "Int:" << Int.Val; OS << "Int:" << Int.Val;
break; break;
case Float: case Float:
OS << "Flt:" << Flt.Val; OS << "Flt:" << Flt.Val;
break; break;
case Symbol: case Symbol:
OS << "Sym:" << Sym.Exp; OS << "Sym:" << Sym.Exp;
break; break;
} }
} }
}; };
class WebAssemblyAsmParser final : public MCTargetAsmParser { class WebAssemblyAsmParser final : public MCTargetAsmParser {
MCAsmParser &Parser; MCAsmParser &Parser;
MCAsmLexer &Lexer; MCAsmLexer &Lexer;
// These are for the current function being parsed:
// These are vectors since register assignments are so far non-sparse.
// Replace by map if necessary.
std::vector<MVT::SimpleValueType> LocalTypes;
std::vector<MVT::SimpleValueType> StackTypes;
MCSymbol *LastLabel; MCSymbol *LastLabel;
public: public:
WebAssemblyAsmParser(const MCSubtargetInfo &sti, MCAsmParser &Parser, WebAssemblyAsmParser(const MCSubtargetInfo &sti, MCAsmParser &Parser,
const MCInstrInfo &mii, const MCTargetOptions &Options) const MCInstrInfo &mii, const MCTargetOptions &Options)
: MCTargetAsmParser(Options, sti, mii), Parser(Parser), : MCTargetAsmParser(Options, sti, mii), Parser(Parser),
Lexer(Parser.getLexer()), LastLabel(nullptr) { Lexer(Parser.getLexer()), LastLabel(nullptr) {
} }
Show All 33 Lines return StringSwitch<MVT::SimpleValueType>(RegType)
.Case("f64", MVT::f64) .Case("f64", MVT::f64)
.Case("i8x16", MVT::v16i8) .Case("i8x16", MVT::v16i8)
.Case("i16x8", MVT::v8i16) .Case("i16x8", MVT::v8i16)
.Case("i32x4", MVT::v4i32) .Case("i32x4", MVT::v4i32)
.Case("f32x4", MVT::v4f32) .Case("f32x4", MVT::v4f32)
.Default(MVT::INVALID_SIMPLE_VALUE_TYPE); .Default(MVT::INVALID_SIMPLE_VALUE_TYPE);
} }
MVT::SimpleValueType &GetType(
std::vector<MVT::SimpleValueType> &Types, size_t i) {
Types.resize(std::max(i + 1, Types.size()), MVT::INVALID_SIMPLE_VALUE_TYPE);
return Types[i];
}
bool ParseReg(OperandVector &Operands, StringRef TypePrefix) {
if (Lexer.is(AsmToken::Integer)) {
auto &Local = Lexer.getTok();
// This is a reference to a local, turn it into a virtual register.
auto LocalNo = static_cast<unsigned>(Local.getIntVal());
Operands.push_back(make_unique<WebAssemblyOperand>(
WebAssemblyOperand::Local, Local.getLoc(),
Local.getEndLoc(),
WebAssemblyOperand::RegOp{LocalNo,
GetType(LocalTypes, LocalNo)}));
Parser.Lex();
} else if (Lexer.is(AsmToken::Identifier)) {
auto &StackRegTok = Lexer.getTok();
// These are push/pop/drop pseudo stack registers, which we turn
// into virtual registers also. The stackify pass will later turn them
// back into implicit stack references if possible.
auto StackReg = StackRegTok.getString();
auto StackOp = StackReg.take_while([](char c) { return isalpha(c); });
auto Reg = StackReg.drop_front(StackOp.size());
unsigned long long ParsedRegNo = 0;
if (!Reg.empty() && getAsUnsignedInteger(Reg, 10, ParsedRegNo))
return Error("Cannot parse stack register index: ", StackRegTok);
unsigned RegNo = static_cast<unsigned>(ParsedRegNo);
if (StackOp == "push") {
// This defines a result, record register type.
auto RegType = ParseRegType(TypePrefix);
GetType(StackTypes, RegNo) = RegType;
Operands.push_back(make_unique<WebAssemblyOperand>(
WebAssemblyOperand::Stack,
StackRegTok.getLoc(),
StackRegTok.getEndLoc(),
WebAssemblyOperand::RegOp{RegNo, RegType}));
} else if (StackOp == "pop") {
// This uses a previously defined stack value.
auto RegType = GetType(StackTypes, RegNo);
Operands.push_back(make_unique<WebAssemblyOperand>(
WebAssemblyOperand::Stack,
StackRegTok.getLoc(),
StackRegTok.getEndLoc(),
WebAssemblyOperand::RegOp{RegNo, RegType}));
} else if (StackOp == "drop") {
// This operand will be dropped, since it is part of an instruction
// whose result is void.
} else {
return Error("Unknown stack register prefix: ", StackRegTok);
}
Parser.Lex();
} else {
return Error(
"Expected identifier/integer following $, instead got: ",
Lexer.getTok());
}
IsNext(AsmToken::Equal);
return false;
}
void ParseSingleInteger(bool IsNegative, OperandVector &Operands) { void ParseSingleInteger(bool IsNegative, OperandVector &Operands) {
auto &Int = Lexer.getTok(); auto &Int = Lexer.getTok();
int64_t Val = Int.getIntVal(); int64_t Val = Int.getIntVal();
if (IsNegative) Val = -Val; if (IsNegative) Val = -Val;
Operands.push_back(make_unique<WebAssemblyOperand>( Operands.push_back(make_unique<WebAssemblyOperand>(
WebAssemblyOperand::Integer, Int.getLoc(), WebAssemblyOperand::Integer, Int.getLoc(),
Int.getEndLoc(), WebAssemblyOperand::IntOp{Val})); Int.getEndLoc(), WebAssemblyOperand::IntOp{Val}));
Parser.Lex(); Parser.Lex();
} }
bool ParseOperandStartingWithInteger(bool IsNegative, bool ParseOperandStartingWithInteger(bool IsNegative,
OperandVector &Operands, OperandVector &Operands,
StringRef InstType) { StringRef InstName) {
ParseSingleInteger(IsNegative, Operands); ParseSingleInteger(IsNegative, Operands);
if (Lexer.is(AsmToken::LParen)) { // FIXME: there is probably a cleaner way to do this.
// Parse load/store operands of the form: offset($reg)align auto IsLoadStore = InstName.startswith("load") ||
auto &LParen = Lexer.getTok(); InstName.startswith("store") ||
Operands.push_back( InstName.startswith("atomic_load") ||
make_unique<WebAssemblyOperand>(WebAssemblyOperand::Token, InstName.startswith("atomic_store");
LParen.getLoc(), if (IsLoadStore) {
LParen.getEndLoc(), // Parse load/store operands of the form: offset align
WebAssemblyOperand::TokOp{ auto &Offset = Lexer.getTok();
LParen.getString()})); if (Offset.is(AsmToken::Integer)) {
Parser.Lex();
if (Expect(AsmToken::Dollar, "register")) return true;
if (ParseReg(Operands, InstType)) return true;
auto &RParen = Lexer.getTok();
Operands.push_back(
make_unique<WebAssemblyOperand>(WebAssemblyOperand::Token,
RParen.getLoc(),
RParen.getEndLoc(),
WebAssemblyOperand::TokOp{
RParen.getString()}));
if (Expect(AsmToken::RParen, ")")) return true;
if (Lexer.is(AsmToken::Integer)) {
ParseSingleInteger(false, Operands); ParseSingleInteger(false, Operands);
} else { } else {
// Alignment not specified. // Alignment not specified.
// FIXME: correctly derive a default from the instruction. // FIXME: correctly derive a default from the instruction.
// We can't just call WebAssembly::GetDefaultP2Align since we don't have
// an opcode until after the assembly matcher.
Operands.push_back(make_unique<WebAssemblyOperand>( Operands.push_back(make_unique<WebAssemblyOperand>(
WebAssemblyOperand::Integer, RParen.getLoc(), WebAssemblyOperand::Integer, Offset.getLoc(),
RParen.getEndLoc(), WebAssemblyOperand::IntOp{0})); Offset.getEndLoc(), WebAssemblyOperand::IntOp{0}));
} }
} }
return false; return false;
} }
bool ParseInstruction(ParseInstructionInfo &/*Info*/, StringRef Name, bool ParseInstruction(ParseInstructionInfo &/*Info*/, StringRef Name,
SMLoc NameLoc, OperandVector &Operands) override { SMLoc NameLoc, OperandVector &Operands) override {
Operands.push_back( Operands.push_back(
make_unique<WebAssemblyOperand>(WebAssemblyOperand::Token, NameLoc, make_unique<WebAssemblyOperand>(WebAssemblyOperand::Token, NameLoc,
SMLoc::getFromPointer( SMLoc::getFromPointer(
NameLoc.getPointer() + Name.size()), NameLoc.getPointer() + Name.size()),
WebAssemblyOperand::TokOp{ WebAssemblyOperand::TokOp{
StringRef(NameLoc.getPointer(), StringRef(NameLoc.getPointer(),
Name.size())})); Name.size())}));
auto NamePair = Name.split('.'); auto NamePair = Name.split('.');
// If no '.', there is no type prefix. // If no '.', there is no type prefix.
if (NamePair.second.empty()) std::swap(NamePair.first, NamePair.second); if (NamePair.second.empty()) std::swap(NamePair.first, NamePair.second);
while (Lexer.isNot(AsmToken::EndOfStatement)) { while (Lexer.isNot(AsmToken::EndOfStatement)) {
auto &Tok = Lexer.getTok(); auto &Tok = Lexer.getTok();
switch (Tok.getKind()) { switch (Tok.getKind()) {
case AsmToken::Dollar: {
Parser.Lex();
if (ParseReg(Operands, NamePair.first)) return true;
break;
}
case AsmToken::Identifier: { case AsmToken::Identifier: {
auto &Id = Lexer.getTok(); auto &Id = Lexer.getTok();
const MCExpr *Val; const MCExpr *Val;
SMLoc End; SMLoc End;
if (Parser.parsePrimaryExpr(Val, End)) if (Parser.parsePrimaryExpr(Val, End))
return Error("Cannot parse symbol: ", Lexer.getTok()); return Error("Cannot parse symbol: ", Lexer.getTok());
Operands.push_back(make_unique<WebAssemblyOperand>( Operands.push_back(make_unique<WebAssemblyOperand>(
WebAssemblyOperand::Symbol, Id.getLoc(), WebAssemblyOperand::Symbol, Id.getLoc(),
Id.getEndLoc(), WebAssemblyOperand::SymOp{Val})); Id.getEndLoc(), WebAssemblyOperand::SymOp{Val}));
break; break;
} }
case AsmToken::Minus: case AsmToken::Minus:
Parser.Lex(); Parser.Lex();
if (Lexer.isNot(AsmToken::Integer)) if (Lexer.isNot(AsmToken::Integer))
return Error("Expected integer instead got: ", Lexer.getTok()); return Error("Expected integer instead got: ", Lexer.getTok());
if (ParseOperandStartingWithInteger(true, Operands, NamePair.first)) if (ParseOperandStartingWithInteger(true, Operands, NamePair.second))
return true; return true;
break; break;
case AsmToken::Integer: case AsmToken::Integer:
if (ParseOperandStartingWithInteger(false, Operands, NamePair.first)) if (ParseOperandStartingWithInteger(false, Operands, NamePair.second))
return true; return true;
break; break;
case AsmToken::Real: { case AsmToken::Real: {
double Val; double Val;
if (Tok.getString().getAsDouble(Val, false)) if (Tok.getString().getAsDouble(Val, false))
return Error("Cannot parse real: ", Tok); return Error("Cannot parse real: ", Tok);
Operands.push_back(make_unique<WebAssemblyOperand>( Operands.push_back(make_unique<WebAssemblyOperand>(
WebAssemblyOperand::Float, Tok.getLoc(), WebAssemblyOperand::Float, Tok.getLoc(),
Tok.getEndLoc(), WebAssemblyOperand::FltOp{Val})); Tok.getEndLoc(), WebAssemblyOperand::FltOp{Val}));
Parser.Lex(); Parser.Lex();
break; break;
} }
default: default:
return Error("Unexpected token in operand: ", Tok); return Error("Unexpected token in operand: ", Tok);
} }
if (Lexer.isNot(AsmToken::EndOfStatement)) { if (Lexer.isNot(AsmToken::EndOfStatement)) {
if (Expect(AsmToken::Comma, ",")) return true; if (Expect(AsmToken::Comma, ",")) return true;
} }
} }
Parser.Lex(); Parser.Lex();
// Call instructions are vararg, but the tablegen matcher doesn't seem to
// support that, so for now we strip these extra operands.
// This is problematic if these arguments are not simple $pop stack
// registers, since e.g. a local register would get lost, so we check for
// this. This can be the case when using -disable-wasm-explicit-locals
// which currently s2wasm requires.
// TODO: Instead, we can move this code to MatchAndEmitInstruction below and
// actually generate get_local instructions on the fly.
// Or even better, improve the matcher to support vararg?
auto IsIndirect = NamePair.second == "call_indirect";
if (IsIndirect || NamePair.second == "call") {
// Figure out number of fixed operands from the instruction.
size_t CallOperands = 1; // The name token.
if (!IsIndirect) CallOperands++; // The function index.
if (!NamePair.first.empty()) CallOperands++; // The result register.
if (Operands.size() > CallOperands) {
// Ensure operands we drop are all $pop.
for (size_t I = CallOperands; I < Operands.size(); I++) {
auto Operand =
reinterpret_cast<WebAssemblyOperand *>(Operands[I].get());
if (Operand->Kind != WebAssemblyOperand::Stack)
Parser.Error(NameLoc,
"Call instruction has non-stack arguments, if this code was "
"generated with -disable-wasm-explicit-locals please remove it");
}
// Drop unneeded operands.
Operands.resize(CallOperands);
}
}
// Block instructions require a signature index, but these are missing in // Block instructions require a signature index, but these are missing in
// assembly, so we add a dummy one explicitly (since we have no control // assembly, so we add a dummy one explicitly (since we have no control
// over signature tables here, we assume these will be regenerated when // over signature tables here, we assume these will be regenerated when
// the wasm module is generated). // the wasm module is generated).
if (NamePair.second == "block" || NamePair.second == "loop") { if (NamePair.second == "block" || NamePair.second == "loop") {
Operands.push_back(make_unique<WebAssemblyOperand>( Operands.push_back(make_unique<WebAssemblyOperand>(
WebAssemblyOperand::Integer, NameLoc, WebAssemblyOperand::Integer, NameLoc,
NameLoc, WebAssemblyOperand::IntOp{-1})); NameLoc, WebAssemblyOperand::IntOp{-1}));
} }
// These don't specify the type, which has to derived from the local index.
if (NamePair.second == "get_local" || NamePair.second == "tee_local") {
if (Operands.size() >= 3 && Operands[1]->isReg() &&
Operands[2]->isImm()) {
auto Op1 = reinterpret_cast<WebAssemblyOperand *>(Operands[1].get());
auto Op2 = reinterpret_cast<WebAssemblyOperand *>(Operands[2].get());
auto Type = GetType(LocalTypes, static_cast<size_t>(Op2->Int.Val));
Op1->Reg.Type = Type;
GetType(StackTypes, Op1->Reg.RegNo) = Type;
}
}
return false; return false;
} }
void onLabelParsed(MCSymbol *Symbol) override { void onLabelParsed(MCSymbol *Symbol) override {
LastLabel = Symbol; LastLabel = Symbol;
} }
bool ParseDirective(AsmToken DirectiveID) override { bool ParseDirective(AsmToken DirectiveID) override {
assert(DirectiveID.getKind() == AsmToken::Identifier); assert(DirectiveID.getKind() == AsmToken::Identifier);
auto &Out = getStreamer(); auto &Out = getStreamer();
auto &TOut = reinterpret_cast<WebAssemblyTargetStreamer &>( auto &TOut = reinterpret_cast<WebAssemblyTargetStreamer &>(
*Out.getTargetStreamer()); *Out.getTargetStreamer());
// TODO: we're just parsing the subset of directives we're interested in, // TODO: we're just parsing the subset of directives we're interested in,
// and ignoring ones we don't recognise. We should ideally verify // and ignoring ones we don't recognise. We should ideally verify
// all directives here. // all directives here.
if (DirectiveID.getString() == ".type") { if (DirectiveID.getString() == ".type") {
// This could be the start of a function, check if followed by // This could be the start of a function, check if followed by
// "label,@function" // "label,@function"
if (!(IsNext(AsmToken::Identifier) && if (!(IsNext(AsmToken::Identifier) &&
IsNext(AsmToken::Comma) && IsNext(AsmToken::Comma) &&
IsNext(AsmToken::At) && IsNext(AsmToken::At) &&
Lexer.is(AsmToken::Identifier))) Lexer.is(AsmToken::Identifier)))
return Error("Expected label,@type declaration, got: ", Lexer.getTok()); return Error("Expected label,@type declaration, got: ", Lexer.getTok());
if (Lexer.getTok().getString() == "function") {
// Track locals from start of function.
LocalTypes.clear();
StackTypes.clear();
}
Parser.Lex(); Parser.Lex();
//Out.EmitSymbolAttribute(??, MCSA_ELF_TypeFunction); //Out.EmitSymbolAttribute(??, MCSA_ELF_TypeFunction);
} else if (DirectiveID.getString() == ".param" || } else if (DirectiveID.getString() == ".param" ||
DirectiveID.getString() == ".local") { DirectiveID.getString() == ".local") {
// Track the number of locals, needed for correct virtual register // Track the number of locals, needed for correct virtual register
// assignment elsewhere. // assignment elsewhere.
// Also output a directive to the streamer. // Also output a directive to the streamer.
std::vector<MVT> Params; std::vector<MVT> Params;
std::vector<MVT> Locals; std::vector<MVT> Locals;
while (Lexer.is(AsmToken::Identifier)) { while (Lexer.is(AsmToken::Identifier)) {
auto RegType = ParseRegType(Lexer.getTok().getString()); auto RegType = ParseRegType(Lexer.getTok().getString());
if (RegType == MVT::INVALID_SIMPLE_VALUE_TYPE) return true; if (RegType == MVT::INVALID_SIMPLE_VALUE_TYPE) return true;
LocalTypes.push_back(RegType);
if (DirectiveID.getString() == ".param") { if (DirectiveID.getString() == ".param") {
Params.push_back(RegType); Params.push_back(RegType);
} else { } else {
Locals.push_back(RegType); Locals.push_back(RegType);
} }
Parser.Lex(); Parser.Lex();
if (!IsNext(AsmToken::Comma)) break; if (!IsNext(AsmToken::Comma)) break;
} }
▲ Show 20 Lines • Show All 56 Lines • Show Last 20 Lines

lib/Target/WebAssembly/InstPrinter/WebAssemblyInstPrinter.cpp

Show First 20 Lines • Show All 52 Lines • ▼ Show 20 Linesvoid WebAssemblyInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
// Print any additional variadic operands. // Print any additional variadic operands.
const MCInstrDesc &Desc = MII.get(MI->getOpcode()); const MCInstrDesc &Desc = MII.get(MI->getOpcode());
if (Desc.isVariadic()) if (Desc.isVariadic())
for (auto i = Desc.getNumOperands(), e = MI->getNumOperands(); i < e; ++i) { for (auto i = Desc.getNumOperands(), e = MI->getNumOperands(); i < e; ++i) {
// FIXME: For CALL_INDIRECT_VOID, don't print a leading comma, because // FIXME: For CALL_INDIRECT_VOID, don't print a leading comma, because
// we have an extra flags operand which is not currently printed, for // we have an extra flags operand which is not currently printed, for
// compatiblity reasons. // compatiblity reasons.
if (i != 0 && if (i != 0 &&
(MI->getOpcode() != WebAssembly::CALL_INDIRECT_VOID || ((MI->getOpcode() != WebAssembly::CALL_INDIRECT_VOID &&
MI->getOpcode() != WebAssembly::CALL_INDIRECT_VOID_S) ||
i != Desc.getNumOperands())) i != Desc.getNumOperands()))
OS << ", "; OS << ", ";
printOperand(MI, i, OS); printOperand(MI, i, OS);
} }
// Print any added annotation. // Print any added annotation.
printAnnotation(OS, Annot); printAnnotation(OS, Annot);
▲ Show 20 Lines • Show All 188 Lines • Show Last 20 Lines

lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp

Show First 20 Lines • Show All 163 Lines • ▼ Show 20 Linesvoid WebAssemblyAsmPrinter::EmitFunctionBodyStart() {
AsmPrinter::EmitFunctionBodyStart(); AsmPrinter::EmitFunctionBodyStart();
} }
void WebAssemblyAsmPrinter::EmitInstruction(const MachineInstr *MI) { void WebAssemblyAsmPrinter::EmitInstruction(const MachineInstr *MI) {
LLVM_DEBUG(dbgs() << "EmitInstruction: " << *MI << '\n'); LLVM_DEBUG(dbgs() << "EmitInstruction: " << *MI << '\n');
switch (MI->getOpcode()) { switch (MI->getOpcode()) {
case WebAssembly::ARGUMENT_I32: case WebAssembly::ARGUMENT_I32:
case WebAssembly::ARGUMENT_I32_S:
case WebAssembly::ARGUMENT_I64: case WebAssembly::ARGUMENT_I64:
case WebAssembly::ARGUMENT_I64_S:
case WebAssembly::ARGUMENT_F32: case WebAssembly::ARGUMENT_F32:
case WebAssembly::ARGUMENT_F32_S:
case WebAssembly::ARGUMENT_F64: case WebAssembly::ARGUMENT_F64:
case WebAssembly::ARGUMENT_F64_S:
case WebAssembly::ARGUMENT_v16i8: case WebAssembly::ARGUMENT_v16i8:
case WebAssembly::ARGUMENT_v16i8_S:
case WebAssembly::ARGUMENT_v8i16: case WebAssembly::ARGUMENT_v8i16:
case WebAssembly::ARGUMENT_v8i16_S:
case WebAssembly::ARGUMENT_v4i32: case WebAssembly::ARGUMENT_v4i32:
case WebAssembly::ARGUMENT_v4i32_S:
case WebAssembly::ARGUMENT_v2i64: case WebAssembly::ARGUMENT_v2i64:
case WebAssembly::ARGUMENT_v2i64_S:
case WebAssembly::ARGUMENT_v4f32: case WebAssembly::ARGUMENT_v4f32:
case WebAssembly::ARGUMENT_v4f32_S:
case WebAssembly::ARGUMENT_v2f64: case WebAssembly::ARGUMENT_v2f64:
case WebAssembly::ARGUMENT_v2f64_S:
// These represent values which are live into the function entry, so there's // These represent values which are live into the function entry, so there's
// no instruction to emit. // no instruction to emit.
break; break;
case WebAssembly::FALLTHROUGH_RETURN_I32: case WebAssembly::FALLTHROUGH_RETURN_I32:
case WebAssembly::FALLTHROUGH_RETURN_I32_S:
case WebAssembly::FALLTHROUGH_RETURN_I64: case WebAssembly::FALLTHROUGH_RETURN_I64:
case WebAssembly::FALLTHROUGH_RETURN_I64_S:
case WebAssembly::FALLTHROUGH_RETURN_F32: case WebAssembly::FALLTHROUGH_RETURN_F32:
case WebAssembly::FALLTHROUGH_RETURN_F32_S:
case WebAssembly::FALLTHROUGH_RETURN_F64: case WebAssembly::FALLTHROUGH_RETURN_F64:
case WebAssembly::FALLTHROUGH_RETURN_F64_S:
case WebAssembly::FALLTHROUGH_RETURN_v16i8: case WebAssembly::FALLTHROUGH_RETURN_v16i8:
case WebAssembly::FALLTHROUGH_RETURN_v16i8_S:
case WebAssembly::FALLTHROUGH_RETURN_v8i16: case WebAssembly::FALLTHROUGH_RETURN_v8i16:
case WebAssembly::FALLTHROUGH_RETURN_v8i16_S:
case WebAssembly::FALLTHROUGH_RETURN_v4i32: case WebAssembly::FALLTHROUGH_RETURN_v4i32:
case WebAssembly::FALLTHROUGH_RETURN_v4i32_S:
case WebAssembly::FALLTHROUGH_RETURN_v2i64: case WebAssembly::FALLTHROUGH_RETURN_v2i64:
case WebAssembly::FALLTHROUGH_RETURN_v2i64_S:
case WebAssembly::FALLTHROUGH_RETURN_v4f32: case WebAssembly::FALLTHROUGH_RETURN_v4f32:
case WebAssembly::FALLTHROUGH_RETURN_v2f64: { case WebAssembly::FALLTHROUGH_RETURN_v4f32_S:
case WebAssembly::FALLTHROUGH_RETURN_v2f64:
case WebAssembly::FALLTHROUGH_RETURN_v2f64_S: {
// These instructions represent the implicit return at the end of a // These instructions represent the implicit return at the end of a
// function body. The operand is always a pop. // function body. Always pops one value off the stack.
assert(MFI->isVRegStackified(MI->getOperand(0).getReg()));
if (isVerbose()) { if (isVerbose()) {
OutStreamer->AddComment("fallthrough-return: $pop" + OutStreamer->AddComment("fallthrough-return-value");
Twine(MFI->getWARegStackId(
MFI->getWAReg(MI->getOperand(0).getReg()))));
OutStreamer->AddBlankLine(); OutStreamer->AddBlankLine();
} }
break; break;
} }
case WebAssembly::FALLTHROUGH_RETURN_VOID: case WebAssembly::FALLTHROUGH_RETURN_VOID:
case WebAssembly::FALLTHROUGH_RETURN_VOID_S:
// This instruction represents the implicit return at the end of a // This instruction represents the implicit return at the end of a
// function body with no return value. // function body with no return value.
if (isVerbose()) { if (isVerbose()) {
OutStreamer->AddComment("fallthrough-return"); OutStreamer->AddComment("fallthrough-return-void");
OutStreamer->AddBlankLine(); OutStreamer->AddBlankLine();
} }
break; break;
default: { default: {
WebAssemblyMCInstLower MCInstLowering(OutContext, *this); WebAssemblyMCInstLower MCInstLowering(OutContext, *this);
MCInst TmpInst; MCInst TmpInst;
MCInstLowering.Lower(MI, TmpInst); MCInstLowering.Lower(MI, TmpInst);
EmitToStreamer(*OutStreamer, TmpInst); EmitToStreamer(*OutStreamer, TmpInst);
Show All 24 Linesbool WebAssemblyAsmPrinter::PrintAsmOperand(const MachineInstr *MI,
if (!ExtraCode) { if (!ExtraCode) {
const MachineOperand &MO = MI->getOperand(OpNo); const MachineOperand &MO = MI->getOperand(OpNo);
switch (MO.getType()) { switch (MO.getType()) {
case MachineOperand::MO_Immediate: case MachineOperand::MO_Immediate:
OS << MO.getImm(); OS << MO.getImm();
return false; return false;
case MachineOperand::MO_Register: case MachineOperand::MO_Register:
// FIXME: only opcode that still contains registers, as required by
// MachineInstr::getDebugVariable().
assert(MI->getOpcode() == WebAssembly::INLINEASM);
OS << regToString(MO); OS << regToString(MO);
return false; return false;
case MachineOperand::MO_GlobalAddress: case MachineOperand::MO_GlobalAddress:
getSymbol(MO.getGlobal())->print(OS, MAI); getSymbol(MO.getGlobal())->print(OS, MAI);
printOffset(MO.getOffset(), OS); printOffset(MO.getOffset(), OS);
return false; return false;
case MachineOperand::MO_ExternalSymbol: case MachineOperand::MO_ExternalSymbol:
GetExternalSymbolSymbol(MO.getSymbolName())->print(OS, MAI); GetExternalSymbolSymbol(MO.getSymbolName())->print(OS, MAI);
Show All 35 Lines

lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp

Show All 25 Lines
#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/Passes.h" #include "llvm/CodeGen/Passes.h"
#include "llvm/Support/Debug.h" #include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h" #include "llvm/Support/raw_ostream.h"
using namespace llvm; using namespace llvm;
#define DEBUG_TYPE "wasm-explicit-locals" #define DEBUG_TYPE "wasm-explicit-locals"
// A command-line option to disable this pass. Note that this produces output // A command-line option to disable this pass, and keep implicit locals
// which is not valid WebAssembly, though it may be more convenient for writing // for the purpose of testing with lit/llc ONLY.
// LLVM unit tests with. // This produces output which is not valid WebAssembly, and is not supported
static cl::opt<bool> DisableWebAssemblyExplicitLocals( // by assemblers/disassemblers and other MC based tools.
"disable-wasm-explicit-locals", cl::ReallyHidden, static cl::opt<bool> WasmDisableExplicitLocals(
cl::desc("WebAssembly: Disable emission of get_local/set_local."), "wasm-disable-explicit-locals", cl::Hidden,
cl::desc("WebAssembly: output implicit locals in"
" instruction output for test purposes only."),
cl::init(false)); cl::init(false));
namespace { namespace {
class WebAssemblyExplicitLocals final : public MachineFunctionPass { class WebAssemblyExplicitLocals final : public MachineFunctionPass {
StringRef getPassName() const override { StringRef getPassName() const override {
return "WebAssembly Explicit Locals"; return "WebAssembly Explicit Locals";
} }
▲ Show 20 Lines • Show All 109 Lines • ▼ Show 20 Lines if (RC == &WebAssembly::F64RegClass)
return MVT::f64; return MVT::f64;
if (RC == &WebAssembly::EXCEPT_REFRegClass) if (RC == &WebAssembly::EXCEPT_REFRegClass)
return MVT::ExceptRef; return MVT::ExceptRef;
llvm_unreachable("unrecognized register class"); llvm_unreachable("unrecognized register class");
} }
/// Given a MachineOperand of a stackified vreg, return the instruction at the /// Given a MachineOperand of a stackified vreg, return the instruction at the
/// start of the expression tree. /// start of the expression tree.
static MachineInstr *FindStartOfTree(MachineOperand &MO, static MachineInstr *findStartOfTree(MachineOperand &MO,
MachineRegisterInfo &MRI, MachineRegisterInfo &MRI,
WebAssemblyFunctionInfo &MFI) { WebAssemblyFunctionInfo &MFI) {
unsigned Reg = MO.getReg(); unsigned Reg = MO.getReg();
assert(MFI.isVRegStackified(Reg)); assert(MFI.isVRegStackified(Reg));
MachineInstr *Def = MRI.getVRegDef(Reg); MachineInstr *Def = MRI.getVRegDef(Reg);
// Find the first stackified use and proceed from there. // Find the first stackified use and proceed from there.
for (MachineOperand &DefMO : Def->explicit_uses()) { for (MachineOperand &DefMO : Def->explicit_uses()) {
if (!DefMO.isReg()) if (!DefMO.isReg())
continue; continue;
return FindStartOfTree(DefMO, MRI, MFI); return findStartOfTree(DefMO, MRI, MFI);
} }
// If there were no stackified uses, we've reached the start. // If there were no stackified uses, we've reached the start.
return Def; return Def;
} }
bool WebAssemblyExplicitLocals::runOnMachineFunction(MachineFunction &MF) { bool WebAssemblyExplicitLocals::runOnMachineFunction(MachineFunction &MF) {
LLVM_DEBUG(dbgs() << "********** Make Locals Explicit **********\n" LLVM_DEBUG(dbgs() << "********** Make Locals Explicit **********\n"
"********** Function: " "********** Function: "
<< MF.getName() << '\n'); << MF.getName() << '\n');
// Disable this pass if directed to do so. // Disable this pass if directed to do so.
if (DisableWebAssemblyExplicitLocals) if (WasmDisableExplicitLocals)
return false; return false;
bool Changed = false; bool Changed = false;
MachineRegisterInfo &MRI = MF.getRegInfo(); MachineRegisterInfo &MRI = MF.getRegInfo();
WebAssemblyFunctionInfo &MFI = *MF.getInfo<WebAssemblyFunctionInfo>(); WebAssemblyFunctionInfo &MFI = *MF.getInfo<WebAssemblyFunctionInfo>();
const auto *TII = MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo(); const auto *TII = MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo();
// Map non-stackified virtual registers to their local ids. // Map non-stackified virtual registers to their local ids.
DenseMap<unsigned, unsigned> Reg2Local; DenseMap<unsigned, unsigned> Reg2Local;
// Handle ARGUMENTS first to ensure that they get the designated numbers. // Handle ARGUMENTS first to ensure that they get the designated numbers.
for (MachineBasicBlock::iterator I = MF.begin()->begin(), for (MachineBasicBlock::iterator I = MF.begin()->begin(),
E = MF.begin()->end(); E = MF.begin()->end();
I != E;) { I != E;) {
MachineInstr &MI = *I++; MachineInstr &MI = *I++;
if (!WebAssembly::isArgument(MI)) if (!WebAssembly::isArgument(MI))
break; break;
unsigned Reg = MI.getOperand(0).getReg(); unsigned Reg = MI.getOperand(0).getReg();
assert(!MFI.isVRegStackified(Reg)); assert(!MFI.isVRegStackified(Reg));
Reg2Local[Reg] = MI.getOperand(1).getImm(); Reg2Local[Reg] = static_cast<unsigned>(MI.getOperand(1).getImm());
MI.eraseFromParent(); MI.eraseFromParent();
Changed = true; Changed = true;
} }
// Start assigning local numbers after the last parameter. // Start assigning local numbers after the last parameter.
unsigned CurLocal = MFI.getParams().size(); unsigned CurLocal = static_cast<unsigned>(MFI.getParams().size());
// Precompute the set of registers that are unused, so that we can insert // Precompute the set of registers that are unused, so that we can insert
// drops to their defs. // drops to their defs.
BitVector UseEmpty(MRI.getNumVirtRegs()); BitVector UseEmpty(MRI.getNumVirtRegs());
for (unsigned i = 0, e = MRI.getNumVirtRegs(); i < e; ++i) for (unsigned I = 0, E = MRI.getNumVirtRegs(); I < E; ++I)
UseEmpty[i] = MRI.use_empty(TargetRegisterInfo::index2VirtReg(i)); UseEmpty[I] = MRI.use_empty(TargetRegisterInfo::index2VirtReg(I));
// Visit each instruction in the function. // Visit each instruction in the function.
for (MachineBasicBlock &MBB : MF) { for (MachineBasicBlock &MBB : MF) {
for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E;) { for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E;) {
MachineInstr &MI = *I++; MachineInstr &MI = *I++;
assert(!WebAssembly::isArgument(MI)); assert(!WebAssembly::isArgument(MI));
if (MI.isDebugInstr() || MI.isLabel()) if (MI.isDebugInstr() || MI.isLabel())
▲ Show 20 Lines • Show All 87 Lines • ▼ Show 20 Lines for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E;) {
MRI.removeRegOperandFromUseList(&MO); MRI.removeRegOperandFromUseList(&MO);
MO = MachineOperand::CreateImm(LocalId); MO = MachineOperand::CreateImm(LocalId);
continue; continue;
} }
// If we see a stackified register, prepare to insert subsequent // If we see a stackified register, prepare to insert subsequent
// get_locals before the start of its tree. // get_locals before the start of its tree.
if (MFI.isVRegStackified(OldReg)) { if (MFI.isVRegStackified(OldReg)) {
InsertPt = FindStartOfTree(MO, MRI, MFI); InsertPt = findStartOfTree(MO, MRI, MFI);
continue; continue;
} }
// Our contract with inline asm register operands is to provide local // Our contract with inline asm register operands is to provide local
// indices as immediates. // indices as immediates.
if (MI.getOpcode() == TargetOpcode::INLINEASM) { if (MI.getOpcode() == TargetOpcode::INLINEASM) {
unsigned LocalId = getLocalId(Reg2Local, CurLocal, OldReg); unsigned LocalId = getLocalId(Reg2Local, CurLocal, OldReg);
MRI.removeRegOperandFromUseList(&MO); MRI.removeRegOperandFromUseList(&MO);
Show All 22 Lines for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E;) {
Changed = true; Changed = true;
} }
} }
} }
// Define the locals. // Define the locals.
// TODO: Sort the locals for better compression. // TODO: Sort the locals for better compression.
MFI.setNumLocals(CurLocal - MFI.getParams().size()); MFI.setNumLocals(CurLocal - MFI.getParams().size());
for (size_t i = 0, e = MRI.getNumVirtRegs(); i < e; ++i) { for (unsigned I = 0, E = MRI.getNumVirtRegs(); I < E; ++I) {
unsigned Reg = TargetRegisterInfo::index2VirtReg(i); unsigned Reg = TargetRegisterInfo::index2VirtReg(I);
auto I = Reg2Local.find(Reg); auto RL = Reg2Local.find(Reg);
if (I == Reg2Local.end() || I->second < MFI.getParams().size()) if (RL == Reg2Local.end() || RL->second < MFI.getParams().size())
continue; continue;
MFI.setLocal(I->second - MFI.getParams().size(), MFI.setLocal(RL->second - MFI.getParams().size(),
typeForRegClass(MRI.getRegClass(Reg))); typeForRegClass(MRI.getRegClass(Reg)));
Changed = true; Changed = true;
} }
#ifndef NDEBUG
// Assert that all registers have been stackified at this point.
for (const MachineBasicBlock &MBB : MF) {
for (const MachineInstr &MI : MBB) {
if (MI.isDebugInstr() || MI.isLabel())
continue;
for (const MachineOperand &MO : MI.explicit_operands()) {
assert(
(!MO.isReg() || MRI.use_empty(MO.getReg()) ||
MFI.isVRegStackified(MO.getReg())) &&
"WebAssemblyExplicitLocals failed to stackify a register operand");
}
}
}
#endif
return Changed; return Changed;
} }

lib/Target/WebAssembly/WebAssemblyInstrControl.td

Show First 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
// multiclass and still have the let statements. // multiclass and still have the let statements.
let isTerminator = 1, hasCtrlDep = 1, isBarrier = 1 in { let isTerminator = 1, hasCtrlDep = 1, isBarrier = 1 in {
def BR_TABLE_I32 : NI<(outs), (ins I32:$index, variable_ops), def BR_TABLE_I32 : NI<(outs), (ins I32:$index, variable_ops),
[(WebAssemblybr_table I32:$index)], 0, [(WebAssemblybr_table I32:$index)], 0,
"br_table \t$index", 0x0e> { "br_table \t$index", 0x0e> {
let TSFlags{0} = 1; let TSFlags{0} = 1;
let TSFlags{1} = 1; let TSFlags{1} = 1;
} }
def BR_TABLE_I32_S : NI<(outs), (ins I32:$index), def BR_TABLE_I32_S : NI<(outs), (ins variable_ops),
[], 1, [], 1,
"br_table \t$index", 0x0e> { "br_table", 0x0e> {
let TSFlags{0} = 1; let TSFlags{0} = 1;
let TSFlags{1} = 1; let TSFlags{1} = 1;
} }
def BR_TABLE_I64 : NI<(outs), (ins I64:$index, variable_ops), def BR_TABLE_I64 : NI<(outs), (ins I64:$index, variable_ops),
[(WebAssemblybr_table I64:$index)], 0, [(WebAssemblybr_table I64:$index)], 0,
"br_table \t$index"> { "br_table \t$index"> {
let TSFlags{0} = 1; let TSFlags{0} = 1;
let TSFlags{1} = 1; let TSFlags{1} = 1;
} }
def BR_TABLE_I64_S : NI<(outs), (ins I64:$index), def BR_TABLE_I64_S : NI<(outs), (ins variable_ops),
[], 1, [], 1,
"br_table \t$index"> { "br_table"> {
let TSFlags{0} = 1; let TSFlags{0} = 1;
let TSFlags{1} = 1; let TSFlags{1} = 1;
} }
} // isTerminator = 1, hasCtrlDep = 1, isBarrier = 1 } // isTerminator = 1, hasCtrlDep = 1, isBarrier = 1
// This is technically a control-flow instruction, since all it affects is the // This is technically a control-flow instruction, since all it affects is the
// IP. // IP.
defm NOP : NRI<(outs), (ins), [], "nop", 0x01>; defm NOP : NRI<(outs), (ins), [], "nop", 0x01>;
▲ Show 20 Lines • Show All 118 Lines • Show Last 20 Lines

lib/Target/WebAssembly/WebAssemblyInstrMemory.td

Show First 20 Lines • Show All 51 Lines • ▼ Show 20 Lines
// We don't need a regPlusES because external symbols never have constant // We don't need a regPlusES because external symbols never have constant
// offsets folded into them, so we can just use add. // offsets folded into them, so we can just use add.
let Defs = [ARGUMENTS] in { let Defs = [ARGUMENTS] in {
// Defines atomic and non-atomic loads, regular and extending. // Defines atomic and non-atomic loads, regular and extending.
multiclass WebAssemblyLoad<WebAssemblyRegClass rc, string Name, int Opcode> { multiclass WebAssemblyLoad<WebAssemblyRegClass rc, string Name, int Opcode> {
let mayLoad = 1 in
defm "": I<(outs rc:$dst), defm "": I<(outs rc:$dst),
(ins P2Align:$p2align, offset32_op:$off, I32:$addr), (ins P2Align:$p2align, offset32_op:$off, I32:$addr),
(outs), (ins P2Align:$p2align, offset32_op:$off), (outs), (ins P2Align:$p2align, offset32_op:$off),
[], !strconcat(Name, "\t$dst, ${off}(${addr})${p2align}"), [], !strconcat(Name, "\t$dst, ${off}(${addr})${p2align}"),
!strconcat(Name, "\t${off}, ${p2align}"), Opcode>; !strconcat(Name, "\t${off}${p2align}"), Opcode>;
} }
// Basic load. // Basic load.
// FIXME: When we can break syntax compatibility, reorder the fields in the // FIXME: When we can break syntax compatibility, reorder the fields in the
// asmstrings to match the binary encoding. // asmstrings to match the binary encoding.
defm LOAD_I32 : WebAssemblyLoad<I32, "i32.load", 0x28>; defm LOAD_I32 : WebAssemblyLoad<I32, "i32.load", 0x28>;
defm LOAD_I64 : WebAssemblyLoad<I64, "i64.load", 0x29>; defm LOAD_I64 : WebAssemblyLoad<I64, "i64.load", 0x29>;
defm LOAD_F32 : WebAssemblyLoad<F32, "f32.load", 0x2a>; defm LOAD_F32 : WebAssemblyLoad<F32, "f32.load", 0x2a>;
▲ Show 20 Lines • Show All 229 Lines • ▼ Show 20 Lines
def : LoadPatExternSymOffOnly<i64, extloadi16, LOAD16_U_I64>; def : LoadPatExternSymOffOnly<i64, extloadi16, LOAD16_U_I64>;
def : LoadPatExternSymOffOnly<i64, extloadi32, LOAD32_U_I64>; def : LoadPatExternSymOffOnly<i64, extloadi32, LOAD32_U_I64>;
let Defs = [ARGUMENTS] in { let Defs = [ARGUMENTS] in {
// Defines atomic and non-atomic stores, regular and truncating // Defines atomic and non-atomic stores, regular and truncating
multiclass WebAssemblyStore<WebAssemblyRegClass rc, string Name, int Opcode> { multiclass WebAssemblyStore<WebAssemblyRegClass rc, string Name, int Opcode> {
let mayStore = 1 in
defm "" : I<(outs), defm "" : I<(outs),
(ins P2Align:$p2align, offset32_op:$off, I32:$addr, rc:$val), (ins P2Align:$p2align, offset32_op:$off, I32:$addr, rc:$val),
(outs), (outs),
(ins P2Align:$p2align, offset32_op:$off), [], (ins P2Align:$p2align, offset32_op:$off), [],
!strconcat(Name, "\t${off}(${addr})${p2align}, $val"), !strconcat(Name, "\t${off}(${addr})${p2align}, $val"),
!strconcat(Name, "\t${off}, ${p2align}"), Opcode>; !strconcat(Name, "\t${off}${p2align}"), Opcode>;
} }
// Basic store. // Basic store.
// Note: WebAssembly inverts SelectionDAG's usual operand order. // Note: WebAssembly inverts SelectionDAG's usual operand order.
defm STORE_I32 : WebAssemblyStore<I32, "i32.store", 0x36>; defm STORE_I32 : WebAssemblyStore<I32, "i32.store", 0x36>;
defm STORE_I64 : WebAssemblyStore<I64, "i64.store", 0x37>; defm STORE_I64 : WebAssemblyStore<I64, "i64.store", 0x37>;
defm STORE_F32 : WebAssemblyStore<F32, "f32.store", 0x38>; defm STORE_F32 : WebAssemblyStore<F32, "f32.store", 0x38>;
defm STORE_F64 : WebAssemblyStore<F64, "f64.store", 0x39>; defm STORE_F64 : WebAssemblyStore<F64, "f64.store", 0x39>;
▲ Show 20 Lines • Show All 141 Lines • ▼ Show 20 Linesdefm CURRENT_MEMORY_I32 : I<(outs I32:$dst), (ins i32imm:$flags),
(outs), (ins i32imm:$flags), (outs), (ins i32imm:$flags),
[], [],
"current_memory\t$dst", "current_memory\t$dst",
"current_memory\t$flags", 0x3f>, "current_memory\t$flags", 0x3f>,
Requires<[HasAddr32]>; Requires<[HasAddr32]>;
// Grow memory. // Grow memory.
defm MEMORY_GROW_I32 : I<(outs I32:$dst), (ins i32imm:$flags, I32:$delta), defm MEMORY_GROW_I32 : I<(outs I32:$dst), (ins i32imm:$flags, I32:$delta),
(outs), (ins i32imm:$flags, I32:$delta), (outs), (ins i32imm:$flags),
[(set I32:$dst, [(set I32:$dst,
(int_wasm_memory_grow (i32 imm:$flags), (int_wasm_memory_grow (i32 imm:$flags),
I32:$delta))], I32:$delta))],
"memory.grow\t$dst, $flags, $delta", "memory.grow\t$dst, $flags, $delta",
"memory.grow\t$flags, $delta", 0x3f>, "memory.grow\t$flags", 0x3f>,
Requires<[HasAddr32]>; Requires<[HasAddr32]>;
defm MEM_GROW_I32 : I<(outs I32:$dst), (ins i32imm:$flags, I32:$delta), defm MEM_GROW_I32 : I<(outs I32:$dst), (ins i32imm:$flags, I32:$delta),
(outs), (ins i32imm:$flags), (outs), (ins i32imm:$flags),
[(set I32:$dst, [(set I32:$dst,
(int_wasm_mem_grow (i32 imm:$flags), I32:$delta))], (int_wasm_mem_grow (i32 imm:$flags), I32:$delta))],
"mem.grow\t$dst, $flags, $delta", "mem.grow\t$flags", "mem.grow\t$dst, $flags, $delta", "mem.grow\t$flags",
0x3f>, 0x3f>,
Requires<[HasAddr32]>; Requires<[HasAddr32]>;
Show All 13 Lines

lib/Target/WebAssembly/WebAssemblyMCInstLower.cpp

Show All 24 Lines
#include "llvm/MC/MCContext.h" #include "llvm/MC/MCContext.h"
#include "llvm/MC/MCExpr.h" #include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCInst.h" #include "llvm/MC/MCInst.h"
#include "llvm/MC/MCSymbolWasm.h" #include "llvm/MC/MCSymbolWasm.h"
#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h" #include "llvm/Support/raw_ostream.h"
using namespace llvm; using namespace llvm;
// This disables the removal of registers when lowering into MC, as required
// by some current tests.
static cl::opt<bool> WasmKeepRegisters(
"wasm-keep-registers", cl::Hidden,
cl::desc("WebAssembly: output stack registers in"
" instruction output for test purposes only."),
cl::init(false));
static unsigned regInstructionToStackInstruction(unsigned OpCode);
MCSymbol * MCSymbol *
WebAssemblyMCInstLower::GetGlobalAddressSymbol(const MachineOperand &MO) const { WebAssemblyMCInstLower::GetGlobalAddressSymbol(const MachineOperand &MO) const {
const GlobalValue *Global = MO.getGlobal(); const GlobalValue *Global = MO.getGlobal();
MCSymbolWasm *WasmSym = cast<MCSymbolWasm>(Printer.getSymbol(Global)); MCSymbolWasm *WasmSym = cast<MCSymbolWasm>(Printer.getSymbol(Global));
if (const auto *FuncTy = dyn_cast<FunctionType>(Global->getValueType())) { if (const auto *FuncTy = dyn_cast<FunctionType>(Global->getValueType())) {
const MachineFunction &MF = *MO.getParent()->getParent()->getParent(); const MachineFunction &MF = *MO.getParent()->getParent()->getParent();
const TargetMachine &TM = MF.getTarget(); const TargetMachine &TM = MF.getTarget();
▲ Show 20 Lines • Show All 189 Lines • ▼ Show 20 Lines case MachineOperand::MO_ExternalSymbol:
MCOp = LowerSymbolOperand(GetExternalSymbolSymbol(MO), /*Offset=*/0, MCOp = LowerSymbolOperand(GetExternalSymbolSymbol(MO), /*Offset=*/0,
(MO.getTargetFlags() & WebAssemblyII::MO_SYMBOL_FUNCTION) != 0, (MO.getTargetFlags() & WebAssemblyII::MO_SYMBOL_FUNCTION) != 0,
(MO.getTargetFlags() & WebAssemblyII::MO_SYMBOL_GLOBAL) != 0); (MO.getTargetFlags() & WebAssemblyII::MO_SYMBOL_GLOBAL) != 0);
break; break;
} }
OutMI.addOperand(MCOp); OutMI.addOperand(MCOp);
} }
if (!WasmKeepRegisters) {
// Remove all uses of stackified registers to bring the instruction format
// into its final stack form used thruout MC, and transition opcodes to
// their _S variant.
// We do this seperate from the above code that still may need these
// registers for e.g. call_indirect signatures.
// See comments in lib/Target/WebAssembly/WebAssemblyInstrFormats.td for
// details.
// TODO: the code above creates new registers which are then removed here.
// That code could be slightly simplified by not doing that, though maybe
// it is simpler conceptually to keep the code above in "register mode"
// until this transition point.
// FIXME: we are not processing inline assembly, which contains register
// operands, because it is used by later target generic code.
if (MI->isDebugInstr() || MI->isLabel() || MI->isInlineAsm())
return;
auto RegOpcode = OutMI.getOpcode();
auto StackOpcode = regInstructionToStackInstruction(RegOpcode);
OutMI.setOpcode(StackOpcode);
// Now remove all register operands.
for (auto I = OutMI.getNumOperands(); I; --I) {
auto &MO = OutMI.getOperand(I - 1);
if (MO.isReg()) {
OutMI.erase(&MO);
}
}
}
}
static unsigned regInstructionToStackInstruction(unsigned OpCode) {
switch (OpCode) {
default:
// You may hit this if you add new instructions, please add them below.
// For most of these opcodes, this function could have been implemented
// as "return OpCode + 1", but since table-gen alphabetically sorts them,
// this cannot be guaranteed (see e.g. BR and BR_IF).
// The approach below is the same as what the x87 backend does.
// TODO(wvo): to make this code cleaner, create a custom tablegen
// code generator that emits the table below automatically.
llvm_unreachable(
"unknown WebAssembly instruction in Explicit Locals pass");
case WebAssembly::ABS_F32: return WebAssembly::ABS_F32_S;
case WebAssembly::ABS_F64: return WebAssembly::ABS_F64_S;
case WebAssembly::ADD_F32: return WebAssembly::ADD_F32_S;
case WebAssembly::ADD_F32x4: return WebAssembly::ADD_F32x4_S;
case WebAssembly::ADD_F64: return WebAssembly::ADD_F64_S;
case WebAssembly::ADD_I16x8: return WebAssembly::ADD_I16x8_S;
case WebAssembly::ADD_I32: return WebAssembly::ADD_I32_S;
case WebAssembly::ADD_I32x4: return WebAssembly::ADD_I32x4_S;
case WebAssembly::ADD_I64: return WebAssembly::ADD_I64_S;
case WebAssembly::ADD_I8x16: return WebAssembly::ADD_I8x16_S;
case WebAssembly::ADJCALLSTACKDOWN: return WebAssembly::ADJCALLSTACKDOWN_S;
case WebAssembly::ADJCALLSTACKUP: return WebAssembly::ADJCALLSTACKUP_S;
case WebAssembly::AND_I32: return WebAssembly::AND_I32_S;
case WebAssembly::AND_I64: return WebAssembly::AND_I64_S;
case WebAssembly::ARGUMENT_EXCEPT_REF: return WebAssembly::ARGUMENT_EXCEPT_REF_S;
case WebAssembly::ARGUMENT_F32: return WebAssembly::ARGUMENT_F32_S;
case WebAssembly::ARGUMENT_F64: return WebAssembly::ARGUMENT_F64_S;
case WebAssembly::ARGUMENT_I32: return WebAssembly::ARGUMENT_I32_S;
case WebAssembly::ARGUMENT_I64: return WebAssembly::ARGUMENT_I64_S;
case WebAssembly::ARGUMENT_v16i8: return WebAssembly::ARGUMENT_v16i8_S;
case WebAssembly::ARGUMENT_v4f32: return WebAssembly::ARGUMENT_v4f32_S;
case WebAssembly::ARGUMENT_v4i32: return WebAssembly::ARGUMENT_v4i32_S;
case WebAssembly::ARGUMENT_v8i16: return WebAssembly::ARGUMENT_v8i16_S;
case WebAssembly::ARGUMENT_v2f64: return WebAssembly::ARGUMENT_v2f64_S;
case WebAssembly::ARGUMENT_v2i64: return WebAssembly::ARGUMENT_v2i64_S;
case WebAssembly::ATOMIC_LOAD16_U_I32: return WebAssembly::ATOMIC_LOAD16_U_I32_S;
case WebAssembly::ATOMIC_LOAD16_U_I64: return WebAssembly::ATOMIC_LOAD16_U_I64_S;
case WebAssembly::ATOMIC_LOAD32_U_I64: return WebAssembly::ATOMIC_LOAD32_U_I64_S;
case WebAssembly::ATOMIC_LOAD8_U_I32: return WebAssembly::ATOMIC_LOAD8_U_I32_S;
case WebAssembly::ATOMIC_LOAD8_U_I64: return WebAssembly::ATOMIC_LOAD8_U_I64_S;
case WebAssembly::ATOMIC_LOAD_I32: return WebAssembly::ATOMIC_LOAD_I32_S;
case WebAssembly::ATOMIC_LOAD_I64: return WebAssembly::ATOMIC_LOAD_I64_S;
case WebAssembly::ATOMIC_STORE16_I32: return WebAssembly::ATOMIC_STORE16_I32_S;
case WebAssembly::ATOMIC_STORE16_I64: return WebAssembly::ATOMIC_STORE16_I64_S;
case WebAssembly::ATOMIC_STORE32_I64: return WebAssembly::ATOMIC_STORE32_I64_S;
case WebAssembly::ATOMIC_STORE8_I32: return WebAssembly::ATOMIC_STORE8_I32_S;
case WebAssembly::ATOMIC_STORE8_I64: return WebAssembly::ATOMIC_STORE8_I64_S;
case WebAssembly::ATOMIC_STORE_I32: return WebAssembly::ATOMIC_STORE_I32_S;
case WebAssembly::ATOMIC_STORE_I64: return WebAssembly::ATOMIC_STORE_I64_S;
case WebAssembly::BLOCK: return WebAssembly::BLOCK_S;
case WebAssembly::BR: return WebAssembly::BR_S;
case WebAssembly::BR_IF: return WebAssembly::BR_IF_S;
case WebAssembly::BR_TABLE_I32: return WebAssembly::BR_TABLE_I32_S;
case WebAssembly::BR_TABLE_I64: return WebAssembly::BR_TABLE_I64_S;
case WebAssembly::BR_UNLESS: return WebAssembly::BR_UNLESS_S;
case WebAssembly::CALL_EXCEPT_REF: return WebAssembly::CALL_EXCEPT_REF_S;
case WebAssembly::CALL_F32: return WebAssembly::CALL_F32_S;
case WebAssembly::CALL_F64: return WebAssembly::CALL_F64_S;
case WebAssembly::CALL_I32: return WebAssembly::CALL_I32_S;
case WebAssembly::CALL_I64: return WebAssembly::CALL_I64_S;
case WebAssembly::CALL_INDIRECT_EXCEPT_REF: return WebAssembly::CALL_INDIRECT_EXCEPT_REF_S;
case WebAssembly::CALL_INDIRECT_F32: return WebAssembly::CALL_INDIRECT_F32_S;
case WebAssembly::CALL_INDIRECT_F64: return WebAssembly::CALL_INDIRECT_F64_S;
case WebAssembly::CALL_INDIRECT_I32: return WebAssembly::CALL_INDIRECT_I32_S;
case WebAssembly::CALL_INDIRECT_I64: return WebAssembly::CALL_INDIRECT_I64_S;
case WebAssembly::CALL_INDIRECT_VOID: return WebAssembly::CALL_INDIRECT_VOID_S;
case WebAssembly::CALL_INDIRECT_v16i8: return WebAssembly::CALL_INDIRECT_v16i8_S;
case WebAssembly::CALL_INDIRECT_v4f32: return WebAssembly::CALL_INDIRECT_v4f32_S;
case WebAssembly::CALL_INDIRECT_v4i32: return WebAssembly::CALL_INDIRECT_v4i32_S;
case WebAssembly::CALL_INDIRECT_v8i16: return WebAssembly::CALL_INDIRECT_v8i16_S;
case WebAssembly::CALL_VOID: return WebAssembly::CALL_VOID_S;
case WebAssembly::CALL_v16i8: return WebAssembly::CALL_v16i8_S;
case WebAssembly::CALL_v4f32: return WebAssembly::CALL_v4f32_S;
case WebAssembly::CALL_v4i32: return WebAssembly::CALL_v4i32_S;
case WebAssembly::CALL_v8i16: return WebAssembly::CALL_v8i16_S;
case WebAssembly::CATCHRET: return WebAssembly::CATCHRET_S;
case WebAssembly::CATCH_ALL: return WebAssembly::CATCH_ALL_S;
case WebAssembly::CATCH_I32: return WebAssembly::CATCH_I32_S;
case WebAssembly::CATCH_I64: return WebAssembly::CATCH_I64_S;
case WebAssembly::CEIL_F32: return WebAssembly::CEIL_F32_S;
case WebAssembly::CEIL_F64: return WebAssembly::CEIL_F64_S;
case WebAssembly::CLEANUPRET: return WebAssembly::CLEANUPRET_S;
case WebAssembly::CLZ_I32: return WebAssembly::CLZ_I32_S;
case WebAssembly::CLZ_I64: return WebAssembly::CLZ_I64_S;
case WebAssembly::CONST_F32: return WebAssembly::CONST_F32_S;
case WebAssembly::CONST_F64: return WebAssembly::CONST_F64_S;
case WebAssembly::CONST_I32: return WebAssembly::CONST_I32_S;
case WebAssembly::CONST_I64: return WebAssembly::CONST_I64_S;
case WebAssembly::COPYSIGN_F32: return WebAssembly::COPYSIGN_F32_S;
case WebAssembly::COPYSIGN_F64: return WebAssembly::COPYSIGN_F64_S;
case WebAssembly::COPY_EXCEPT_REF: return WebAssembly::COPY_EXCEPT_REF_S;
case WebAssembly::COPY_F32: return WebAssembly::COPY_F32_S;
case WebAssembly::COPY_F64: return WebAssembly::COPY_F64_S;
case WebAssembly::COPY_I32: return WebAssembly::COPY_I32_S;
case WebAssembly::COPY_I64: return WebAssembly::COPY_I64_S;
case WebAssembly::COPY_V128: return WebAssembly::COPY_V128_S;
case WebAssembly::CTZ_I32: return WebAssembly::CTZ_I32_S;
case WebAssembly::CTZ_I64: return WebAssembly::CTZ_I64_S;
case WebAssembly::CURRENT_MEMORY_I32: return WebAssembly::CURRENT_MEMORY_I32_S;
case WebAssembly::DIV_F32: return WebAssembly::DIV_F32_S;
case WebAssembly::DIV_F64: return WebAssembly::DIV_F64_S;
case WebAssembly::DIV_S_I32: return WebAssembly::DIV_S_I32_S;
case WebAssembly::DIV_S_I64: return WebAssembly::DIV_S_I64_S;
case WebAssembly::DIV_U_I32: return WebAssembly::DIV_U_I32_S;
case WebAssembly::DIV_U_I64: return WebAssembly::DIV_U_I64_S;
case WebAssembly::DROP_EXCEPT_REF: return WebAssembly::DROP_EXCEPT_REF_S;
case WebAssembly::DROP_F32: return WebAssembly::DROP_F32_S;
case WebAssembly::DROP_F64: return WebAssembly::DROP_F64_S;
case WebAssembly::DROP_I32: return WebAssembly::DROP_I32_S;
case WebAssembly::DROP_I64: return WebAssembly::DROP_I64_S;
case WebAssembly::DROP_V128: return WebAssembly::DROP_V128_S;
case WebAssembly::END_BLOCK: return WebAssembly::END_BLOCK_S;
case WebAssembly::END_FUNCTION: return WebAssembly::END_FUNCTION_S;
case WebAssembly::END_LOOP: return WebAssembly::END_LOOP_S;
case WebAssembly::END_TRY: return WebAssembly::END_TRY_S;
case WebAssembly::EQZ_I32: return WebAssembly::EQZ_I32_S;
case WebAssembly::EQZ_I64: return WebAssembly::EQZ_I64_S;
case WebAssembly::EQ_F32: return WebAssembly::EQ_F32_S;
case WebAssembly::EQ_F64: return WebAssembly::EQ_F64_S;
case WebAssembly::EQ_I32: return WebAssembly::EQ_I32_S;
case WebAssembly::EQ_I64: return WebAssembly::EQ_I64_S;
case WebAssembly::F32_CONVERT_S_I32: return WebAssembly::F32_CONVERT_S_I32_S;
case WebAssembly::F32_CONVERT_S_I64: return WebAssembly::F32_CONVERT_S_I64_S;
case WebAssembly::F32_CONVERT_U_I32: return WebAssembly::F32_CONVERT_U_I32_S;
case WebAssembly::F32_CONVERT_U_I64: return WebAssembly::F32_CONVERT_U_I64_S;
case WebAssembly::F32_DEMOTE_F64: return WebAssembly::F32_DEMOTE_F64_S;
case WebAssembly::F32_REINTERPRET_I32: return WebAssembly::F32_REINTERPRET_I32_S;
case WebAssembly::F64_CONVERT_S_I32: return WebAssembly::F64_CONVERT_S_I32_S;
case WebAssembly::F64_CONVERT_S_I64: return WebAssembly::F64_CONVERT_S_I64_S;
case WebAssembly::F64_CONVERT_U_I32: return WebAssembly::F64_CONVERT_U_I32_S;
case WebAssembly::F64_CONVERT_U_I64: return WebAssembly::F64_CONVERT_U_I64_S;
case WebAssembly::F64_PROMOTE_F32: return WebAssembly::F64_PROMOTE_F32_S;
case WebAssembly::F64_REINTERPRET_I64: return WebAssembly::F64_REINTERPRET_I64_S;
case WebAssembly::FALLTHROUGH_RETURN_EXCEPT_REF: return WebAssembly::FALLTHROUGH_RETURN_EXCEPT_REF_S;
case WebAssembly::FALLTHROUGH_RETURN_F32: return WebAssembly::FALLTHROUGH_RETURN_F32_S;
case WebAssembly::FALLTHROUGH_RETURN_F64: return WebAssembly::FALLTHROUGH_RETURN_F64_S;
case WebAssembly::FALLTHROUGH_RETURN_I32: return WebAssembly::FALLTHROUGH_RETURN_I32_S;
case WebAssembly::FALLTHROUGH_RETURN_I64: return WebAssembly::FALLTHROUGH_RETURN_I64_S;
case WebAssembly::FALLTHROUGH_RETURN_VOID: return WebAssembly::FALLTHROUGH_RETURN_VOID_S;
case WebAssembly::FALLTHROUGH_RETURN_v16i8: return WebAssembly::FALLTHROUGH_RETURN_v16i8_S;
case WebAssembly::FALLTHROUGH_RETURN_v4f32: return WebAssembly::FALLTHROUGH_RETURN_v4f32_S;
case WebAssembly::FALLTHROUGH_RETURN_v4i32: return WebAssembly::FALLTHROUGH_RETURN_v4i32_S;
case WebAssembly::FALLTHROUGH_RETURN_v8i16: return WebAssembly::FALLTHROUGH_RETURN_v8i16_S;
case WebAssembly::FALLTHROUGH_RETURN_v2f64: return WebAssembly::FALLTHROUGH_RETURN_v2f64_S;
case WebAssembly::FALLTHROUGH_RETURN_v2i64: return WebAssembly::FALLTHROUGH_RETURN_v2i64_S;
case WebAssembly::FLOOR_F32: return WebAssembly::FLOOR_F32_S;
case WebAssembly::FLOOR_F64: return WebAssembly::FLOOR_F64_S;
case WebAssembly::FP_TO_SINT_I32_F32: return WebAssembly::FP_TO_SINT_I32_F32_S;
case WebAssembly::FP_TO_SINT_I32_F64: return WebAssembly::FP_TO_SINT_I32_F64_S;
case WebAssembly::FP_TO_SINT_I64_F32: return WebAssembly::FP_TO_SINT_I64_F32_S;
case WebAssembly::FP_TO_SINT_I64_F64: return WebAssembly::FP_TO_SINT_I64_F64_S;
case WebAssembly::FP_TO_UINT_I32_F32: return WebAssembly::FP_TO_UINT_I32_F32_S;
case WebAssembly::FP_TO_UINT_I32_F64: return WebAssembly::FP_TO_UINT_I32_F64_S;
case WebAssembly::FP_TO_UINT_I64_F32: return WebAssembly::FP_TO_UINT_I64_F32_S;
case WebAssembly::FP_TO_UINT_I64_F64: return WebAssembly::FP_TO_UINT_I64_F64_S;
case WebAssembly::GET_GLOBAL_EXCEPT_REF: return WebAssembly::GET_GLOBAL_EXCEPT_REF_S;
case WebAssembly::GET_GLOBAL_F32: return WebAssembly::GET_GLOBAL_F32_S;
case WebAssembly::GET_GLOBAL_F64: return WebAssembly::GET_GLOBAL_F64_S;
case WebAssembly::GET_GLOBAL_I32: return WebAssembly::GET_GLOBAL_I32_S;
case WebAssembly::GET_GLOBAL_I64: return WebAssembly::GET_GLOBAL_I64_S;
case WebAssembly::GET_GLOBAL_V128: return WebAssembly::GET_GLOBAL_V128_S;
case WebAssembly::GET_LOCAL_EXCEPT_REF: return WebAssembly::GET_LOCAL_EXCEPT_REF_S;
case WebAssembly::GET_LOCAL_F32: return WebAssembly::GET_LOCAL_F32_S;
case WebAssembly::GET_LOCAL_F64: return WebAssembly::GET_LOCAL_F64_S;
case WebAssembly::GET_LOCAL_I32: return WebAssembly::GET_LOCAL_I32_S;
case WebAssembly::GET_LOCAL_I64: return WebAssembly::GET_LOCAL_I64_S;
case WebAssembly::GET_LOCAL_V128: return WebAssembly::GET_LOCAL_V128_S;
case WebAssembly::GE_F32: return WebAssembly::GE_F32_S;
case WebAssembly::GE_F64: return WebAssembly::GE_F64_S;
case WebAssembly::GE_S_I32: return WebAssembly::GE_S_I32_S;
case WebAssembly::GE_S_I64: return WebAssembly::GE_S_I64_S;
case WebAssembly::GE_U_I32: return WebAssembly::GE_U_I32_S;
case WebAssembly::GE_U_I64: return WebAssembly::GE_U_I64_S;
case WebAssembly::GROW_MEMORY_I32: return WebAssembly::GROW_MEMORY_I32_S;
case WebAssembly::GT_F32: return WebAssembly::GT_F32_S;
case WebAssembly::GT_F64: return WebAssembly::GT_F64_S;
case WebAssembly::GT_S_I32: return WebAssembly::GT_S_I32_S;
case WebAssembly::GT_S_I64: return WebAssembly::GT_S_I64_S;
case WebAssembly::GT_U_I32: return WebAssembly::GT_U_I32_S;
case WebAssembly::GT_U_I64: return WebAssembly::GT_U_I64_S;
case WebAssembly::I32_EXTEND16_S_I32: return WebAssembly::I32_EXTEND16_S_I32_S;
case WebAssembly::I32_EXTEND8_S_I32: return WebAssembly::I32_EXTEND8_S_I32_S;
case WebAssembly::I32_REINTERPRET_F32: return WebAssembly::I32_REINTERPRET_F32_S;
case WebAssembly::I32_TRUNC_S_F32: return WebAssembly::I32_TRUNC_S_F32_S;
case WebAssembly::I32_TRUNC_S_F64: return WebAssembly::I32_TRUNC_S_F64_S;
case WebAssembly::I32_TRUNC_S_SAT_F32: return WebAssembly::I32_TRUNC_S_SAT_F32_S;
case WebAssembly::I32_TRUNC_S_SAT_F64: return WebAssembly::I32_TRUNC_S_SAT_F64_S;
case WebAssembly::I32_TRUNC_U_F32: return WebAssembly::I32_TRUNC_U_F32_S;
case WebAssembly::I32_TRUNC_U_F64: return WebAssembly::I32_TRUNC_U_F64_S;
case WebAssembly::I32_TRUNC_U_SAT_F32: return WebAssembly::I32_TRUNC_U_SAT_F32_S;
case WebAssembly::I32_TRUNC_U_SAT_F64: return WebAssembly::I32_TRUNC_U_SAT_F64_S;
case WebAssembly::I32_WRAP_I64: return WebAssembly::I32_WRAP_I64_S;
case WebAssembly::I64_EXTEND16_S_I64: return WebAssembly::I64_EXTEND16_S_I64_S;
case WebAssembly::I64_EXTEND32_S_I64: return WebAssembly::I64_EXTEND32_S_I64_S;
case WebAssembly::I64_EXTEND8_S_I64: return WebAssembly::I64_EXTEND8_S_I64_S;
case WebAssembly::I64_EXTEND_S_I32: return WebAssembly::I64_EXTEND_S_I32_S;
case WebAssembly::I64_EXTEND_U_I32: return WebAssembly::I64_EXTEND_U_I32_S;
case WebAssembly::I64_REINTERPRET_F64: return WebAssembly::I64_REINTERPRET_F64_S;
case WebAssembly::I64_TRUNC_S_F32: return WebAssembly::I64_TRUNC_S_F32_S;
case WebAssembly::I64_TRUNC_S_F64: return WebAssembly::I64_TRUNC_S_F64_S;
case WebAssembly::I64_TRUNC_S_SAT_F32: return WebAssembly::I64_TRUNC_S_SAT_F32_S;
case WebAssembly::I64_TRUNC_S_SAT_F64: return WebAssembly::I64_TRUNC_S_SAT_F64_S;
case WebAssembly::I64_TRUNC_U_F32: return WebAssembly::I64_TRUNC_U_F32_S;
case WebAssembly::I64_TRUNC_U_F64: return WebAssembly::I64_TRUNC_U_F64_S;
case WebAssembly::I64_TRUNC_U_SAT_F32: return WebAssembly::I64_TRUNC_U_SAT_F32_S;
case WebAssembly::I64_TRUNC_U_SAT_F64: return WebAssembly::I64_TRUNC_U_SAT_F64_S;
case WebAssembly::LE_F32: return WebAssembly::LE_F32_S;
case WebAssembly::LE_F64: return WebAssembly::LE_F64_S;
case WebAssembly::LE_S_I32: return WebAssembly::LE_S_I32_S;
case WebAssembly::LE_S_I64: return WebAssembly::LE_S_I64_S;
case WebAssembly::LE_U_I32: return WebAssembly::LE_U_I32_S;
case WebAssembly::LE_U_I64: return WebAssembly::LE_U_I64_S;
case WebAssembly::LOAD16_S_I32: return WebAssembly::LOAD16_S_I32_S;
case WebAssembly::LOAD16_S_I64: return WebAssembly::LOAD16_S_I64_S;
case WebAssembly::LOAD16_U_I32: return WebAssembly::LOAD16_U_I32_S;
case WebAssembly::LOAD16_U_I64: return WebAssembly::LOAD16_U_I64_S;
case WebAssembly::LOAD32_S_I64: return WebAssembly::LOAD32_S_I64_S;
case WebAssembly::LOAD32_U_I64: return WebAssembly::LOAD32_U_I64_S;
case WebAssembly::LOAD8_S_I32: return WebAssembly::LOAD8_S_I32_S;
case WebAssembly::LOAD8_S_I64: return WebAssembly::LOAD8_S_I64_S;
case WebAssembly::LOAD8_U_I32: return WebAssembly::LOAD8_U_I32_S;
case WebAssembly::LOAD8_U_I64: return WebAssembly::LOAD8_U_I64_S;
case WebAssembly::LOAD_F32: return WebAssembly::LOAD_F32_S;
case WebAssembly::LOAD_F64: return WebAssembly::LOAD_F64_S;
case WebAssembly::LOAD_I32: return WebAssembly::LOAD_I32_S;
case WebAssembly::LOAD_I64: return WebAssembly::LOAD_I64_S;
case WebAssembly::LOOP: return WebAssembly::LOOP_S;
case WebAssembly::LT_F32: return WebAssembly::LT_F32_S;
case WebAssembly::LT_F64: return WebAssembly::LT_F64_S;
case WebAssembly::LT_S_I32: return WebAssembly::LT_S_I32_S;
case WebAssembly::LT_S_I64: return WebAssembly::LT_S_I64_S;
case WebAssembly::LT_U_I32: return WebAssembly::LT_U_I32_S;
case WebAssembly::LT_U_I64: return WebAssembly::LT_U_I64_S;
case WebAssembly::MAX_F32: return WebAssembly::MAX_F32_S;
case WebAssembly::MAX_F64: return WebAssembly::MAX_F64_S;
case WebAssembly::MEMORY_GROW_I32: return WebAssembly::MEMORY_GROW_I32_S;
case WebAssembly::MEMORY_SIZE_I32: return WebAssembly::MEMORY_SIZE_I32_S;
case WebAssembly::MEM_GROW_I32: return WebAssembly::MEM_GROW_I32_S;
case WebAssembly::MEM_SIZE_I32: return WebAssembly::MEM_SIZE_I32_S;
case WebAssembly::MIN_F32: return WebAssembly::MIN_F32_S;
case WebAssembly::MIN_F64: return WebAssembly::MIN_F64_S;
case WebAssembly::MUL_F32: return WebAssembly::MUL_F32_S;
case WebAssembly::MUL_F32x4: return WebAssembly::MUL_F32x4_S;
case WebAssembly::MUL_F64: return WebAssembly::MUL_F64_S;
case WebAssembly::MUL_I16x8: return WebAssembly::MUL_I16x8_S;
case WebAssembly::MUL_I32: return WebAssembly::MUL_I32_S;
case WebAssembly::MUL_I32x4: return WebAssembly::MUL_I32x4_S;
case WebAssembly::MUL_I64: return WebAssembly::MUL_I64_S;
case WebAssembly::MUL_I8x16: return WebAssembly::MUL_I8x16_S;
case WebAssembly::NEAREST_F32: return WebAssembly::NEAREST_F32_S;
case WebAssembly::NEAREST_F64: return WebAssembly::NEAREST_F64_S;
case WebAssembly::NEG_F32: return WebAssembly::NEG_F32_S;
case WebAssembly::NEG_F64: return WebAssembly::NEG_F64_S;
case WebAssembly::NE_F32: return WebAssembly::NE_F32_S;
case WebAssembly::NE_F64: return WebAssembly::NE_F64_S;
case WebAssembly::NE_I32: return WebAssembly::NE_I32_S;
case WebAssembly::NE_I64: return WebAssembly::NE_I64_S;
case WebAssembly::NOP: return WebAssembly::NOP_S;
case WebAssembly::OR_I32: return WebAssembly::OR_I32_S;
case WebAssembly::OR_I64: return WebAssembly::OR_I64_S;
case WebAssembly::PCALL_INDIRECT_EXCEPT_REF: return WebAssembly::PCALL_INDIRECT_EXCEPT_REF_S;
case WebAssembly::PCALL_INDIRECT_F32: return WebAssembly::PCALL_INDIRECT_F32_S;
case WebAssembly::PCALL_INDIRECT_F64: return WebAssembly::PCALL_INDIRECT_F64_S;
case WebAssembly::PCALL_INDIRECT_I32: return WebAssembly::PCALL_INDIRECT_I32_S;
case WebAssembly::PCALL_INDIRECT_I64: return WebAssembly::PCALL_INDIRECT_I64_S;
case WebAssembly::PCALL_INDIRECT_VOID: return WebAssembly::PCALL_INDIRECT_VOID_S;
case WebAssembly::PCALL_INDIRECT_v16i8: return WebAssembly::PCALL_INDIRECT_v16i8_S;
case WebAssembly::PCALL_INDIRECT_v4f32: return WebAssembly::PCALL_INDIRECT_v4f32_S;
case WebAssembly::PCALL_INDIRECT_v4i32: return WebAssembly::PCALL_INDIRECT_v4i32_S;
case WebAssembly::PCALL_INDIRECT_v8i16: return WebAssembly::PCALL_INDIRECT_v8i16_S;
case WebAssembly::POPCNT_I32: return WebAssembly::POPCNT_I32_S;
case WebAssembly::POPCNT_I64: return WebAssembly::POPCNT_I64_S;
case WebAssembly::REM_S_I32: return WebAssembly::REM_S_I32_S;
case WebAssembly::REM_S_I64: return WebAssembly::REM_S_I64_S;
case WebAssembly::REM_U_I32: return WebAssembly::REM_U_I32_S;
case WebAssembly::REM_U_I64: return WebAssembly::REM_U_I64_S;
case WebAssembly::RETHROW: return WebAssembly::RETHROW_S;
case WebAssembly::RETHROW_TO_CALLER: return WebAssembly::RETHROW_TO_CALLER_S;
case WebAssembly::RETURN_EXCEPT_REF: return WebAssembly::RETURN_EXCEPT_REF_S;
case WebAssembly::RETURN_F32: return WebAssembly::RETURN_F32_S;
case WebAssembly::RETURN_F64: return WebAssembly::RETURN_F64_S;
case WebAssembly::RETURN_I32: return WebAssembly::RETURN_I32_S;
case WebAssembly::RETURN_I64: return WebAssembly::RETURN_I64_S;
case WebAssembly::RETURN_VOID: return WebAssembly::RETURN_VOID_S;
case WebAssembly::RETURN_v16i8: return WebAssembly::RETURN_v16i8_S;
case WebAssembly::RETURN_v4f32: return WebAssembly::RETURN_v4f32_S;
case WebAssembly::RETURN_v4i32: return WebAssembly::RETURN_v4i32_S;
case WebAssembly::RETURN_v8i16: return WebAssembly::RETURN_v8i16_S;
case WebAssembly::ROTL_I32: return WebAssembly::ROTL_I32_S;
case WebAssembly::ROTL_I64: return WebAssembly::ROTL_I64_S;
case WebAssembly::ROTR_I32: return WebAssembly::ROTR_I32_S;
case WebAssembly::ROTR_I64: return WebAssembly::ROTR_I64_S;
case WebAssembly::SELECT_EXCEPT_REF: return WebAssembly::SELECT_EXCEPT_REF_S;
case WebAssembly::SELECT_F32: return WebAssembly::SELECT_F32_S;
case WebAssembly::SELECT_F64: return WebAssembly::SELECT_F64_S;
case WebAssembly::SELECT_I32: return WebAssembly::SELECT_I32_S;
case WebAssembly::SELECT_I64: return WebAssembly::SELECT_I64_S;
case WebAssembly::SET_GLOBAL_EXCEPT_REF: return WebAssembly::SET_GLOBAL_EXCEPT_REF_S;
case WebAssembly::SET_GLOBAL_F32: return WebAssembly::SET_GLOBAL_F32_S;
case WebAssembly::SET_GLOBAL_F64: return WebAssembly::SET_GLOBAL_F64_S;
case WebAssembly::SET_GLOBAL_I32: return WebAssembly::SET_GLOBAL_I32_S;
case WebAssembly::SET_GLOBAL_I64: return WebAssembly::SET_GLOBAL_I64_S;
case WebAssembly::SET_GLOBAL_V128: return WebAssembly::SET_GLOBAL_V128_S;
case WebAssembly::SET_LOCAL_EXCEPT_REF: return WebAssembly::SET_LOCAL_EXCEPT_REF_S;
case WebAssembly::SET_LOCAL_F32: return WebAssembly::SET_LOCAL_F32_S;
case WebAssembly::SET_LOCAL_F64: return WebAssembly::SET_LOCAL_F64_S;
case WebAssembly::SET_LOCAL_I32: return WebAssembly::SET_LOCAL_I32_S;
case WebAssembly::SET_LOCAL_I64: return WebAssembly::SET_LOCAL_I64_S;
case WebAssembly::SET_LOCAL_V128: return WebAssembly::SET_LOCAL_V128_S;
case WebAssembly::SHL_I32: return WebAssembly::SHL_I32_S;
case WebAssembly::SHL_I64: return WebAssembly::SHL_I64_S;
case WebAssembly::SHR_S_I32: return WebAssembly::SHR_S_I32_S;
case WebAssembly::SHR_S_I64: return WebAssembly::SHR_S_I64_S;
case WebAssembly::SHR_U_I32: return WebAssembly::SHR_U_I32_S;
case WebAssembly::SHR_U_I64: return WebAssembly::SHR_U_I64_S;
case WebAssembly::SQRT_F32: return WebAssembly::SQRT_F32_S;
case WebAssembly::SQRT_F64: return WebAssembly::SQRT_F64_S;
case WebAssembly::STORE16_I32: return WebAssembly::STORE16_I32_S;
case WebAssembly::STORE16_I64: return WebAssembly::STORE16_I64_S;
case WebAssembly::STORE32_I64: return WebAssembly::STORE32_I64_S;
case WebAssembly::STORE8_I32: return WebAssembly::STORE8_I32_S;
case WebAssembly::STORE8_I64: return WebAssembly::STORE8_I64_S;
case WebAssembly::STORE_F32: return WebAssembly::STORE_F32_S;
case WebAssembly::STORE_F64: return WebAssembly::STORE_F64_S;
case WebAssembly::STORE_I32: return WebAssembly::STORE_I32_S;
case WebAssembly::STORE_I64: return WebAssembly::STORE_I64_S;
case WebAssembly::SUB_F32: return WebAssembly::SUB_F32_S;
case WebAssembly::SUB_F32x4: return WebAssembly::SUB_F32x4_S;
case WebAssembly::SUB_F64: return WebAssembly::SUB_F64_S;
case WebAssembly::SUB_I16x8: return WebAssembly::SUB_I16x8_S;
case WebAssembly::SUB_I32: return WebAssembly::SUB_I32_S;
case WebAssembly::SUB_I32x4: return WebAssembly::SUB_I32x4_S;
case WebAssembly::SUB_I64: return WebAssembly::SUB_I64_S;
case WebAssembly::SUB_I8x16: return WebAssembly::SUB_I8x16_S;
case WebAssembly::TEE_EXCEPT_REF: return WebAssembly::TEE_EXCEPT_REF_S;
case WebAssembly::TEE_F32: return WebAssembly::TEE_F32_S;
case WebAssembly::TEE_F64: return WebAssembly::TEE_F64_S;
case WebAssembly::TEE_I32: return WebAssembly::TEE_I32_S;
case WebAssembly::TEE_I64: return WebAssembly::TEE_I64_S;
case WebAssembly::TEE_LOCAL_EXCEPT_REF: return WebAssembly::TEE_LOCAL_EXCEPT_REF_S;
case WebAssembly::TEE_LOCAL_F32: return WebAssembly::TEE_LOCAL_F32_S;
case WebAssembly::TEE_LOCAL_F64: return WebAssembly::TEE_LOCAL_F64_S;
case WebAssembly::TEE_LOCAL_I32: return WebAssembly::TEE_LOCAL_I32_S;
case WebAssembly::TEE_LOCAL_I64: return WebAssembly::TEE_LOCAL_I64_S;
case WebAssembly::TEE_LOCAL_V128: return WebAssembly::TEE_LOCAL_V128_S;
case WebAssembly::TEE_V128: return WebAssembly::TEE_V128_S;
case WebAssembly::THROW_I32: return WebAssembly::THROW_I32_S;
case WebAssembly::THROW_I64: return WebAssembly::THROW_I64_S;
case WebAssembly::TRUNC_F32: return WebAssembly::TRUNC_F32_S;
case WebAssembly::TRUNC_F64: return WebAssembly::TRUNC_F64_S;
case WebAssembly::TRY: return WebAssembly::TRY_S;
case WebAssembly::UNREACHABLE: return WebAssembly::UNREACHABLE_S;
case WebAssembly::XOR_I32: return WebAssembly::XOR_I32_S;
case WebAssembly::XOR_I64: return WebAssembly::XOR_I64_S;
}
} }

lib/Target/WebAssembly/WebAssemblyUtilities.cpp

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const char *const WebAssembly::CxaRethrowFn = "__cxa_rethrow"; const char *const WebAssembly::CxaRethrowFn = "__cxa_rethrow";
const char *const WebAssembly::StdTerminateFn = "_ZSt9terminatev"; const char *const WebAssembly::StdTerminateFn = "_ZSt9terminatev";
const char *const WebAssembly::PersonalityWrapperFn = const char *const WebAssembly::PersonalityWrapperFn =
"_Unwind_Wasm_CallPersonality"; "_Unwind_Wasm_CallPersonality";
bool WebAssembly::isArgument(const MachineInstr &MI) { bool WebAssembly::isArgument(const MachineInstr &MI) {
switch (MI.getOpcode()) { switch (MI.getOpcode()) {
case WebAssembly::ARGUMENT_I32: case WebAssembly::ARGUMENT_I32:
case WebAssembly::ARGUMENT_I32_S:
case WebAssembly::ARGUMENT_I64: case WebAssembly::ARGUMENT_I64:
case WebAssembly::ARGUMENT_I64_S:
case WebAssembly::ARGUMENT_F32: case WebAssembly::ARGUMENT_F32:
case WebAssembly::ARGUMENT_F32_S:
case WebAssembly::ARGUMENT_F64: case WebAssembly::ARGUMENT_F64:
case WebAssembly::ARGUMENT_F64_S:
case WebAssembly::ARGUMENT_v16i8: case WebAssembly::ARGUMENT_v16i8:
case WebAssembly::ARGUMENT_v16i8_S:
case WebAssembly::ARGUMENT_v8i16: case WebAssembly::ARGUMENT_v8i16:
case WebAssembly::ARGUMENT_v8i16_S:
case WebAssembly::ARGUMENT_v4i32: case WebAssembly::ARGUMENT_v4i32:
case WebAssembly::ARGUMENT_v4i32_S:
case WebAssembly::ARGUMENT_v2i64: case WebAssembly::ARGUMENT_v2i64:
case WebAssembly::ARGUMENT_v2i64_S:
case WebAssembly::ARGUMENT_v4f32: case WebAssembly::ARGUMENT_v4f32:
case WebAssembly::ARGUMENT_v4f32_S:
case WebAssembly::ARGUMENT_v2f64: case WebAssembly::ARGUMENT_v2f64:
case WebAssembly::ARGUMENT_v2f64_S:
return true; return true;
default: default:
return false; return false;
} }
} }
bool WebAssembly::isCopy(const MachineInstr &MI) { bool WebAssembly::isCopy(const MachineInstr &MI) {
switch (MI.getOpcode()) { switch (MI.getOpcode()) {
case WebAssembly::COPY_I32: case WebAssembly::COPY_I32:
case WebAssembly::COPY_I32_S:
case WebAssembly::COPY_I64: case WebAssembly::COPY_I64:
case WebAssembly::COPY_I64_S:
case WebAssembly::COPY_F32: case WebAssembly::COPY_F32:
case WebAssembly::COPY_F32_S:
case WebAssembly::COPY_F64: case WebAssembly::COPY_F64:
case WebAssembly::COPY_F64_S:
return true; return true;
default: default:
return false; return false;
} }
} }
bool WebAssembly::isTee(const MachineInstr &MI) { bool WebAssembly::isTee(const MachineInstr &MI) {
switch (MI.getOpcode()) { switch (MI.getOpcode()) {
case WebAssembly::TEE_I32: case WebAssembly::TEE_I32:
case WebAssembly::TEE_I32_S:
case WebAssembly::TEE_I64: case WebAssembly::TEE_I64:
case WebAssembly::TEE_I64_S:
case WebAssembly::TEE_F32: case WebAssembly::TEE_F32:
case WebAssembly::TEE_F32_S:
case WebAssembly::TEE_F64: case WebAssembly::TEE_F64:
case WebAssembly::TEE_F64_S:
return true; return true;
default: default:
return false; return false;
} }
} }
/// Test whether MI is a child of some other node in an expression tree. /// Test whether MI is a child of some other node in an expression tree.
bool WebAssembly::isChild(const MachineInstr &MI, bool WebAssembly::isChild(const MachineInstr &MI,
const WebAssemblyFunctionInfo &MFI) { const WebAssemblyFunctionInfo &MFI) {
if (MI.getNumOperands() == 0) if (MI.getNumOperands() == 0)
return false; return false;
const MachineOperand &MO = MI.getOperand(0); const MachineOperand &MO = MI.getOperand(0);
if (!MO.isReg() || MO.isImplicit() || !MO.isDef()) if (!MO.isReg() || MO.isImplicit() || !MO.isDef())
return false; return false;
unsigned Reg = MO.getReg(); unsigned Reg = MO.getReg();
return TargetRegisterInfo::isVirtualRegister(Reg) && return TargetRegisterInfo::isVirtualRegister(Reg) &&
MFI.isVRegStackified(Reg); MFI.isVRegStackified(Reg);
} }
bool WebAssembly::isCallDirect(const MachineInstr &MI) { bool WebAssembly::isCallDirect(const MachineInstr &MI) {
switch (MI.getOpcode()) { switch (MI.getOpcode()) {
case WebAssembly::CALL_VOID: case WebAssembly::CALL_VOID:
case WebAssembly::CALL_VOID_S:
case WebAssembly::CALL_I32: case WebAssembly::CALL_I32:
case WebAssembly::CALL_I32_S:
case WebAssembly::CALL_I64: case WebAssembly::CALL_I64:
case WebAssembly::CALL_I64_S:
case WebAssembly::CALL_F32: case WebAssembly::CALL_F32:
case WebAssembly::CALL_F32_S:
case WebAssembly::CALL_F64: case WebAssembly::CALL_F64:
case WebAssembly::CALL_F64_S:
case WebAssembly::CALL_v16i8: case WebAssembly::CALL_v16i8:
case WebAssembly::CALL_v16i8_S:
case WebAssembly::CALL_v8i16: case WebAssembly::CALL_v8i16:
case WebAssembly::CALL_v8i16_S:
case WebAssembly::CALL_v4i32: case WebAssembly::CALL_v4i32:
case WebAssembly::CALL_v4i32_S:
case WebAssembly::CALL_v2i64: case WebAssembly::CALL_v2i64:
case WebAssembly::CALL_v2i64_S:
case WebAssembly::CALL_v4f32: case WebAssembly::CALL_v4f32:
case WebAssembly::CALL_v4f32_S:
case WebAssembly::CALL_v2f64: case WebAssembly::CALL_v2f64:
case WebAssembly::CALL_v2f64_S:
case WebAssembly::CALL_EXCEPT_REF: case WebAssembly::CALL_EXCEPT_REF:
case WebAssembly::CALL_EXCEPT_REF_S:
return true; return true;
default: default:
return false; return false;
} }
} }
bool WebAssembly::isCallIndirect(const MachineInstr &MI) { bool WebAssembly::isCallIndirect(const MachineInstr &MI) {
switch (MI.getOpcode()) { switch (MI.getOpcode()) {
case WebAssembly::CALL_INDIRECT_VOID: case WebAssembly::CALL_INDIRECT_VOID:
case WebAssembly::CALL_INDIRECT_VOID_S:
case WebAssembly::CALL_INDIRECT_I32: case WebAssembly::CALL_INDIRECT_I32:
case WebAssembly::CALL_INDIRECT_I32_S:
case WebAssembly::CALL_INDIRECT_I64: case WebAssembly::CALL_INDIRECT_I64:
case WebAssembly::CALL_INDIRECT_I64_S:
case WebAssembly::CALL_INDIRECT_F32: case WebAssembly::CALL_INDIRECT_F32:
case WebAssembly::CALL_INDIRECT_F32_S:
case WebAssembly::CALL_INDIRECT_F64: case WebAssembly::CALL_INDIRECT_F64:
case WebAssembly::CALL_INDIRECT_F64_S:
case WebAssembly::CALL_INDIRECT_v16i8: case WebAssembly::CALL_INDIRECT_v16i8:
case WebAssembly::CALL_INDIRECT_v16i8_S:
case WebAssembly::CALL_INDIRECT_v8i16: case WebAssembly::CALL_INDIRECT_v8i16:
case WebAssembly::CALL_INDIRECT_v8i16_S:
case WebAssembly::CALL_INDIRECT_v4i32: case WebAssembly::CALL_INDIRECT_v4i32:
case WebAssembly::CALL_INDIRECT_v4i32_S:
case WebAssembly::CALL_INDIRECT_v2i64: case WebAssembly::CALL_INDIRECT_v2i64:
case WebAssembly::CALL_INDIRECT_v2i64_S:
case WebAssembly::CALL_INDIRECT_v4f32: case WebAssembly::CALL_INDIRECT_v4f32:
case WebAssembly::CALL_INDIRECT_v4f32_S:
case WebAssembly::CALL_INDIRECT_v2f64: case WebAssembly::CALL_INDIRECT_v2f64:
case WebAssembly::CALL_INDIRECT_v2f64_S:
case WebAssembly::CALL_INDIRECT_EXCEPT_REF: case WebAssembly::CALL_INDIRECT_EXCEPT_REF:
case WebAssembly::CALL_INDIRECT_EXCEPT_REF_S:
return true; return true;
default: default:
return false; return false;
} }
} }
unsigned WebAssembly::getCalleeOpNo(const MachineInstr &MI) { unsigned WebAssembly::getCalleeOpNo(const MachineInstr &MI) {
switch (MI.getOpcode()) { switch (MI.getOpcode()) {
case WebAssembly::CALL_VOID: case WebAssembly::CALL_VOID:
case WebAssembly::CALL_VOID_S:
case WebAssembly::CALL_INDIRECT_VOID: case WebAssembly::CALL_INDIRECT_VOID:
case WebAssembly::CALL_INDIRECT_VOID_S:
return 0; return 0;
case WebAssembly::CALL_I32: case WebAssembly::CALL_I32:
case WebAssembly::CALL_I32_S:
case WebAssembly::CALL_I64: case WebAssembly::CALL_I64:
case WebAssembly::CALL_I64_S:
case WebAssembly::CALL_F32: case WebAssembly::CALL_F32:
case WebAssembly::CALL_F32_S:
case WebAssembly::CALL_F64: case WebAssembly::CALL_F64:
case WebAssembly::CALL_F64_S:
case WebAssembly::CALL_EXCEPT_REF: case WebAssembly::CALL_EXCEPT_REF:
case WebAssembly::CALL_EXCEPT_REF_S:
case WebAssembly::CALL_INDIRECT_I32: case WebAssembly::CALL_INDIRECT_I32:
case WebAssembly::CALL_INDIRECT_I32_S:
case WebAssembly::CALL_INDIRECT_I64: case WebAssembly::CALL_INDIRECT_I64:
case WebAssembly::CALL_INDIRECT_I64_S:
case WebAssembly::CALL_INDIRECT_F32: case WebAssembly::CALL_INDIRECT_F32:
case WebAssembly::CALL_INDIRECT_F32_S:
case WebAssembly::CALL_INDIRECT_F64: case WebAssembly::CALL_INDIRECT_F64:
case WebAssembly::CALL_INDIRECT_F64_S:
case WebAssembly::CALL_INDIRECT_EXCEPT_REF: case WebAssembly::CALL_INDIRECT_EXCEPT_REF:
case WebAssembly::CALL_INDIRECT_EXCEPT_REF_S:
return 1; return 1;
default: default:
llvm_unreachable("Not a call instruction"); llvm_unreachable("Not a call instruction");
} }
} }
bool WebAssembly::isMarker(const MachineInstr &MI) { bool WebAssembly::isMarker(const MachineInstr &MI) {
switch (MI.getOpcode()) { switch (MI.getOpcode()) {
case WebAssembly::BLOCK: case WebAssembly::BLOCK:
case WebAssembly::BLOCK_S:
case WebAssembly::END_BLOCK: case WebAssembly::END_BLOCK:
case WebAssembly::END_BLOCK_S:
case WebAssembly::LOOP: case WebAssembly::LOOP:
case WebAssembly::LOOP_S:
case WebAssembly::END_LOOP: case WebAssembly::END_LOOP:
case WebAssembly::END_LOOP_S:
case WebAssembly::TRY: case WebAssembly::TRY:
case WebAssembly::TRY_S:
case WebAssembly::END_TRY: case WebAssembly::END_TRY:
case WebAssembly::END_TRY_S:
return true; return true;
default: default:
return false; return false;
} }
} }
bool WebAssembly::isThrow(const MachineInstr &MI) { bool WebAssembly::isThrow(const MachineInstr &MI) {
switch (MI.getOpcode()) { switch (MI.getOpcode()) {
case WebAssembly::THROW_I32: case WebAssembly::THROW_I32:
case WebAssembly::THROW_I32_S:
case WebAssembly::THROW_I64: case WebAssembly::THROW_I64:
case WebAssembly::THROW_I64_S:
return true; return true;
default: default:
return false; return false;
} }
} }
bool WebAssembly::isRethrow(const MachineInstr &MI) { bool WebAssembly::isRethrow(const MachineInstr &MI) {
switch (MI.getOpcode()) { switch (MI.getOpcode()) {
case WebAssembly::RETHROW: case WebAssembly::RETHROW:
case WebAssembly::RETHROW_S:
case WebAssembly::RETHROW_TO_CALLER: case WebAssembly::RETHROW_TO_CALLER:
case WebAssembly::RETHROW_TO_CALLER_S:
return true; return true;
default: default:
return false; return false;
} }
} }
bool WebAssembly::isCatch(const MachineInstr &MI) { bool WebAssembly::isCatch(const MachineInstr &MI) {
switch (MI.getOpcode()) { switch (MI.getOpcode()) {
case WebAssembly::CATCH_I32: case WebAssembly::CATCH_I32:
case WebAssembly::CATCH_I32_S:
case WebAssembly::CATCH_I64: case WebAssembly::CATCH_I64:
case WebAssembly::CATCH_I64_S:
case WebAssembly::CATCH_ALL: case WebAssembly::CATCH_ALL:
case WebAssembly::CATCH_ALL_S:
return true; return true;
default: default:
return false; return false;
} }
} }
bool WebAssembly::mayThrow(const MachineInstr &MI) { bool WebAssembly::mayThrow(const MachineInstr &MI) {
switch (MI.getOpcode()) { switch (MI.getOpcode()) {
case WebAssembly::THROW_I32: case WebAssembly::THROW_I32:
case WebAssembly::THROW_I32_S:
case WebAssembly::THROW_I64: case WebAssembly::THROW_I64:
case WebAssembly::THROW_I64_S:
case WebAssembly::RETHROW: case WebAssembly::RETHROW:
case WebAssembly::RETHROW_S:
return true; return true;
} }
if (isCallIndirect(MI)) if (isCallIndirect(MI))
return true; return true;
if (!MI.isCall()) if (!MI.isCall())
return false; return false;
const MachineOperand &MO = MI.getOperand(getCalleeOpNo(MI)); const MachineOperand &MO = MI.getOperand(getCalleeOpNo(MI));
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} }
bool WebAssembly::isCatchTerminatePad(const MachineBasicBlock &MBB) { bool WebAssembly::isCatchTerminatePad(const MachineBasicBlock &MBB) {
if (!MBB.isEHPad()) if (!MBB.isEHPad())
return false; return false;
bool SeenCatch = false; bool SeenCatch = false;
for (auto &MI : MBB) { for (auto &MI : MBB) {
if (MI.getOpcode() == WebAssembly::CATCH_I32 || if (MI.getOpcode() == WebAssembly::CATCH_I32 ||
MI.getOpcode() == WebAssembly::CATCH_I64) MI.getOpcode() == WebAssembly::CATCH_I64 ||
MI.getOpcode() == WebAssembly::CATCH_I32_S ||
MI.getOpcode() == WebAssembly::CATCH_I64_S)
SeenCatch = true; SeenCatch = true;
if (SeenCatch && MI.isCall()) { if (SeenCatch && MI.isCall()) {
const MachineOperand &CalleeOp = MI.getOperand(getCalleeOpNo(MI)); const MachineOperand &CalleeOp = MI.getOperand(getCalleeOpNo(MI));
if (CalleeOp.isGlobal() && if (CalleeOp.isGlobal() &&
CalleeOp.getGlobal()->getName() == ClangCallTerminateFn) CalleeOp.getGlobal()->getName() == ClangCallTerminateFn)
return true; return true;
} }
} }
return false; return false;
} }
bool WebAssembly::isCatchAllTerminatePad(const MachineBasicBlock &MBB) { bool WebAssembly::isCatchAllTerminatePad(const MachineBasicBlock &MBB) {
if (!MBB.isEHPad()) if (!MBB.isEHPad())
return false; return false;
bool SeenCatchAll = false; bool SeenCatchAll = false;
for (auto &MI : MBB) { for (auto &MI : MBB) {
if (MI.getOpcode() == WebAssembly::CATCH_ALL) if (MI.getOpcode() == WebAssembly::CATCH_ALL ||
MI.getOpcode() == WebAssembly::CATCH_ALL_S)
SeenCatchAll = true; SeenCatchAll = true;
if (SeenCatchAll && MI.isCall()) { if (SeenCatchAll && MI.isCall()) {
const MachineOperand &CalleeOp = MI.getOperand(getCalleeOpNo(MI)); const MachineOperand &CalleeOp = MI.getOperand(getCalleeOpNo(MI));
if (CalleeOp.isGlobal() && if (CalleeOp.isGlobal() &&
CalleeOp.getGlobal()->getName() == StdTerminateFn) CalleeOp.getGlobal()->getName() == StdTerminateFn)
return true; return true;
} }
} }
return false; return false;
} }

test/CodeGen/WebAssembly/address-offsets.ll

; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals | FileCheck %s ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers | FileCheck %s
; Test folding constant offsets and symbols into load and store addresses under ; Test folding constant offsets and symbols into load and store addresses under
; a variety of circumstances. ; a variety of circumstances.
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
@g = external global [0 x i32], align 4 @g = external global [0 x i32], align 4
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test/CodeGen/WebAssembly/atomic-mem-consistency.ll

; RUN: not llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt ; RUN: not llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt
; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -mattr=+atomics,+sign-ext | FileCheck %s ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+atomics,+sign-ext | FileCheck %s
; Currently all wasm atomic memory access instructions are sequentially ; Currently all wasm atomic memory access instructions are sequentially
; consistent, so even if LLVM IR specifies weaker orderings than that, we ; consistent, so even if LLVM IR specifies weaker orderings than that, we
; should upgrade them to sequential ordering and treat them in the same way. ; should upgrade them to sequential ordering and treat them in the same way.
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
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test/CodeGen/WebAssembly/atomic-rmw.ll

; RUN: not llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt ; RUN: not llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-keep-registers
; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -mattr=+atomics,+sign-ext | FileCheck %s ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+atomics,+sign-ext | FileCheck %s
; Test atomic RMW (read-modify-write) instructions are assembled properly. ; Test atomic RMW (read-modify-write) instructions are assembled properly.
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
;===---------------------------------------------------------------------------- ;===----------------------------------------------------------------------------
; Atomic read-modify-writes: 32-bit ; Atomic read-modify-writes: 32-bit
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test/CodeGen/WebAssembly/byval.ll

; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -verify-machineinstrs | FileCheck %s ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -verify-machineinstrs | FileCheck %s
; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -verify-machineinstrs -fast-isel | FileCheck %s ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -verify-machineinstrs -fast-isel | FileCheck %s
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
%SmallStruct = type { i32 } %SmallStruct = type { i32 }
%OddStruct = type { i32, i8, i32 } %OddStruct = type { i32, i8, i32 }
%AlignedStruct = type { double, double } %AlignedStruct = type { double, double }
%BigStruct = type { double, double, double, double, double, double, double, double, double, double, double, i8, i8, i8 } %BigStruct = type { double, double, double, double, double, double, double, double, double, double, double, i8, i8, i8 }
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test/CodeGen/WebAssembly/call.ll

; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-temporary-workarounds=false | FileCheck %s ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-temporary-workarounds=false | FileCheck %s
; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -fast-isel -fast-isel-abort=1 -wasm-temporary-workarounds=false | FileCheck %s ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-keep-registers -fast-isel -fast-isel-abort=1 -wasm-temporary-workarounds=false | FileCheck %s
; Test that basic call operations assemble as expected. ; Test that basic call operations assemble as expected.
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
declare i32 @i32_nullary() declare i32 @i32_nullary()
declare i32 @i32_unary(i32) declare i32 @i32_unary(i32)
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test/CodeGen/WebAssembly/cfg-stackify-eh.ll

; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -disable-block-placement -verify-machineinstrs -fast-isel=false -machine-sink-split-probability-threshold=0 -cgp-freq-ratio-to-skip-merge=1000 -exception-model=wasm -mattr=+exception-handling | FileCheck %s ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -disable-block-placement -verify-machineinstrs -fast-isel=false -machine-sink-split-probability-threshold=0 -cgp-freq-ratio-to-skip-merge=1000 -exception-model=wasm -mattr=+exception-handling | FileCheck %s
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
@_ZTIi = external constant i8* @_ZTIi = external constant i8*
@_ZTId = external constant i8* @_ZTId = external constant i8*
; Simple test case with two catch clauses ; Simple test case with two catch clauses
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test/CodeGen/WebAssembly/cfg-stackify.ll

; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -disable-block-placement -verify-machineinstrs -fast-isel=false -machine-sink-split-probability-threshold=0 -cgp-freq-ratio-to-skip-merge=1000 | FileCheck %s ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -disable-block-placement -verify-machineinstrs -fast-isel=false -machine-sink-split-probability-threshold=0 -cgp-freq-ratio-to-skip-merge=1000 | FileCheck %s
; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -tail-dup-placement=0 -verify-machineinstrs -fast-isel=false -machine-sink-split-probability-threshold=0 -cgp-freq-ratio-to-skip-merge=1000 | FileCheck -check-prefix=OPT %s ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -tail-dup-placement=0 -verify-machineinstrs -fast-isel=false -machine-sink-split-probability-threshold=0 -cgp-freq-ratio-to-skip-merge=1000 | FileCheck -check-prefix=OPT %s
; Test the CFG stackifier pass. ; Test the CFG stackifier pass.
; Explicitly disable fast-isel, since it gets implicitly enabled in the ; Explicitly disable fast-isel, since it gets implicitly enabled in the
; optnone test. ; optnone test.
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
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test/CodeGen/WebAssembly/cfi.ll

; RUN: opt -S -lowertypetests < %s | llc -asm-verbose=false -disable-wasm-fallthrough-return-opt | FileCheck %s ; RUN: opt -S -lowertypetests < %s | llc -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-keep-registers | FileCheck %s
; Tests that we correctly assign indexes for control flow integrity. ; Tests that we correctly assign indexes for control flow integrity.
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
@0 = private unnamed_addr constant [2 x void (...)*] [void (...)* bitcast (void ()* @f to void (...)*), void (...)* bitcast (void ()* @g to void (...)*)], align 16 @0 = private unnamed_addr constant [2 x void (...)*] [void (...)* bitcast (void ()* @f to void (...)*), void (...)* bitcast (void ()* @g to void (...)*)], align 16
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test/CodeGen/WebAssembly/comparisons_f32.ll

; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt | FileCheck %s ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-keep-registers | FileCheck %s
; Test that basic 32-bit floating-point comparison operations assemble as ; Test that basic 32-bit floating-point comparison operations assemble as
; expected. ; expected.
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
; CHECK-LABEL: ord_f32: ; CHECK-LABEL: ord_f32:
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test/CodeGen/WebAssembly/comparisons_f64.ll

; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt | FileCheck %s ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-keep-registers | FileCheck %s
; Test that basic 64-bit floating-point comparison operations assemble as ; Test that basic 64-bit floating-point comparison operations assemble as
; expected. ; expected.
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
; CHECK-LABEL: ord_f64: ; CHECK-LABEL: ord_f64:
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test/CodeGen/WebAssembly/comparisons_i32.ll

; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt | FileCheck %s ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-keep-registers | FileCheck %s
; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -fast-isel -fast-isel-abort=1 | FileCheck %s ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-keep-registers -fast-isel -fast-isel-abort=1 | FileCheck %s
; Test that basic 32-bit integer comparison operations assemble as expected. ; Test that basic 32-bit integer comparison operations assemble as expected.
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
; CHECK-LABEL: eq_i32: ; CHECK-LABEL: eq_i32:
; CHECK-NEXT: .param i32, i32{{$}} ; CHECK-NEXT: .param i32, i32{{$}}
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test/CodeGen/WebAssembly/comparisons_i64.ll

; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt | FileCheck %s ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-keep-registers | FileCheck %s
; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -fast-isel -fast-isel-abort=1 | FileCheck %s ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-keep-registers -fast-isel -fast-isel-abort=1 | FileCheck %s
; Test that basic 64-bit integer comparison operations assemble as expected. ; Test that basic 64-bit integer comparison operations assemble as expected.
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
; CHECK-LABEL: eq_i64: ; CHECK-LABEL: eq_i64:
; CHECK-NEXT: .param i64, i64{{$}} ; CHECK-NEXT: .param i64, i64{{$}}
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test/CodeGen/WebAssembly/conv-trap.ll

; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -mattr=-nontrapping-fptoint | FileCheck %s ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=-nontrapping-fptoint | FileCheck %s
; Test that basic conversion operations assemble as expected using ; Test that basic conversion operations assemble as expected using
; the trapping opcodes and explicit code to suppress the trapping. ; the trapping opcodes and explicit code to suppress the trapping.
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
; CHECK-LABEL: i32_trunc_s_f32: ; CHECK-LABEL: i32_trunc_s_f32:
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test/CodeGen/WebAssembly/conv.ll

; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -mattr=+nontrapping-fptoint | FileCheck %s ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+nontrapping-fptoint | FileCheck %s
; Test that basic conversion operations assemble as expected. ; Test that basic conversion operations assemble as expected.
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
; CHECK-LABEL: i32_wrap_i64: ; CHECK-LABEL: i32_wrap_i64:
; CHECK-NEXT: .param i64{{$}} ; CHECK-NEXT: .param i64{{$}}
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test/CodeGen/WebAssembly/copysign-casts.ll

; RUN: llc < %s -asm-verbose=false | FileCheck %s ; RUN: llc < %s -asm-verbose=false -wasm-keep-registers | FileCheck %s
; DAGCombiner oddly folds casts into the rhs of copysign. Test that they get ; DAGCombiner oddly folds casts into the rhs of copysign. Test that they get
; unfolded. ; unfolded.
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
declare double @copysign(double, double) nounwind readnone declare double @copysign(double, double) nounwind readnone
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test/CodeGen/WebAssembly/divrem-constant.ll

; RUN: llc < %s -asm-verbose=false | FileCheck %s ; RUN: llc < %s -asm-verbose=false -wasm-keep-registers | FileCheck %s
; Test that integer div and rem by constant are optimized appropriately. ; Test that integer div and rem by constant are optimized appropriately.
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
; CHECK-LABEL: test_udiv_2: ; CHECK-LABEL: test_udiv_2:
; CHECK: i32.shr_u ; CHECK: i32.shr_u
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test/CodeGen/WebAssembly/exception.ll

; RUN: not llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -exception-model=wasm ; RUN: not llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-keep-registers -exception-model=wasm
; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -exception-model=wasm -mattr=+exception-handling | FileCheck -allow-deprecated-dag-overlap %s ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-keep-registers -exception-model=wasm -mattr=+exception-handling | FileCheck -allow-deprecated-dag-overlap %s
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
%struct.Cleanup = type { i8 } %struct.Cleanup = type { i8 }
@_ZTIi = external constant i8* @_ZTIi = external constant i8*
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try.cont: ; preds = %entry, %catch try.cont: ; preds = %entry, %catch
ret void ret void
} }
; CHECK-LABEL: test_cleanup: ; CHECK-LABEL: test_cleanup:
; CHECK: call foo@FUNCTION ; CHECK: call foo@FUNCTION
; CHECK: catch_all ; CHECK: catch_all
; CHECK: i32.call $push20=, _ZN7CleanupD1Ev@FUNCTION ; CHECK: i32.call $push{{.+}}=, _ZN7CleanupD1Ev@FUNCTION
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Fixed separately in rL339736.

aheejin: Fixed separately in rL339736.
; CHECK: rethrow ; CHECK: rethrow
define void @test_cleanup() personality i8* bitcast (i32 (...)* @__gxx_wasm_personality_v0 to i8*) { define void @test_cleanup() personality i8* bitcast (i32 (...)* @__gxx_wasm_personality_v0 to i8*) {
entry: entry:
%c = alloca %struct.Cleanup, align 1 %c = alloca %struct.Cleanup, align 1
invoke void @foo() invoke void @foo()
to label %invoke.cont unwind label %ehcleanup to label %invoke.cont unwind label %ehcleanup
invoke.cont: ; preds = %entry invoke.cont: ; preds = %entry
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test/CodeGen/WebAssembly/explicit-locals.mir

# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass wasm-explicit-locals %s -o - | FileCheck %s # RUN: llc -mtriple=wasm32-unknown-unknown -run-pass wasm-explicit-locals -wasm-keep-registers %s -o - | FileCheck %s
# When a drop instruction is inserted to drop a dead register operand, the # When a drop instruction is inserted to drop a dead register operand, the
# original operand should be marked not dead anymore because it is now used by # original operand should be marked not dead anymore because it is now used by
# the new drop instruction. And the operand to the new drop instruction should # the new drop instruction. And the operand to the new drop instruction should
# be marked killed instead. # be marked killed instead.
--- ---
name: drop_test name: drop_test
liveins: liveins:
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test/CodeGen/WebAssembly/f16.ll

; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt | FileCheck %s ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-keep-registers | FileCheck %s
; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -fast-isel | FileCheck %s ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-keep-registers -fast-isel | FileCheck %s
; Test that f16 is expanded. ; Test that f16 is expanded.
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
; CHECK-LABEL: demote: ; CHECK-LABEL: demote:
; CHECK-NEXT: .param f32{{$}} ; CHECK-NEXT: .param f32{{$}}
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test/CodeGen/WebAssembly/f32.ll

; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt | FileCheck %s ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-keep-registers | FileCheck %s
; Test that basic 32-bit floating-point operations assemble as expected. ; Test that basic 32-bit floating-point operations assemble as expected.
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
declare float @llvm.fabs.f32(float) declare float @llvm.fabs.f32(float)
declare float @llvm.copysign.f32(float, float) declare float @llvm.copysign.f32(float, float)
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test/CodeGen/WebAssembly/f64.ll

; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt | FileCheck %s ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-keep-registers | FileCheck %s
; Test that basic 64-bit floating-point operations assemble as expected. ; Test that basic 64-bit floating-point operations assemble as expected.
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
declare double @llvm.fabs.f64(double) declare double @llvm.fabs.f64(double)
declare double @llvm.copysign.f64(double, double) declare double @llvm.copysign.f64(double, double)
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test/CodeGen/WebAssembly/fast-isel-br-i1.ll

; RUN: llc < %s -fast-isel -asm-verbose=false | FileCheck %s ; RUN: llc < %s -fast-isel -asm-verbose=false -wasm-keep-registers | FileCheck %s
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
; Fast-isel uses a 32-bit xor with -1 to negate i1 values, because it doesn't ; Fast-isel uses a 32-bit xor with -1 to negate i1 values, because it doesn't
; make any guarantees about the contents of the high bits of a register holding ; make any guarantees about the contents of the high bits of a register holding
; an i1 value. Test that when we do a `br_if` or `br_unless` with what what an ; an i1 value. Test that when we do a `br_if` or `br_unless` with what what an
; i1 value in LLVM IR, that we only test the low bit. ; i1 value in LLVM IR, that we only test the low bit.
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test/CodeGen/WebAssembly/fast-isel-i24.ll

; RUN: llc < %s -O0 ; RUN: llc < %s -O0 -wasm-keep-registers
; PR36564 ; PR36564
; PR37546 ; PR37546
; Test that fast-isel properly copes with i24 arguments and return types. ; Test that fast-isel properly copes with i24 arguments and return types.
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
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test/CodeGen/WebAssembly/fast-isel-i256.ll

; RUN: llc < %s -O0 ; RUN: llc < %s -O0 -wasm-keep-registers
; PR36564 ; PR36564
; PR37546 ; PR37546
; Test that fast-isel properly copes with i256 arguments and return types. ; Test that fast-isel properly copes with i256 arguments and return types.
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
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test/CodeGen/WebAssembly/fast-isel-noreg.ll

; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -verify-machineinstrs | FileCheck %s ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-keep-registers -verify-machineinstrs | FileCheck %s
; RUN: llc < %s -asm-verbose=false -fast-isel -verify-machineinstrs | FileCheck %s ; RUN: llc < %s -asm-verbose=false -wasm-keep-registers -fast-isel -verify-machineinstrs | FileCheck %s
; Test that FastISel does not generate instructions with NoReg ; Test that FastISel does not generate instructions with NoReg
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
; CHECK: i32.const $push0=, 0 ; CHECK: i32.const $push0=, 0
define hidden i32 @a() #0 { define hidden i32 @a() #0 {
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test/CodeGen/WebAssembly/fast-isel.ll

; RUN: llc < %s -asm-verbose=false \ ; RUN: llc < %s -asm-verbose=false \
; RUN: -fast-isel -fast-isel-abort=1 -verify-machineinstrs \ ; RUN: -fast-isel -fast-isel-abort=1 -verify-machineinstrs \
; RUN: -disable-wasm-explicit-locals \ ; RUN: -wasm-disable-explicit-locals -wasm-keep-registers \
; RUN: | FileCheck %s ; RUN: | FileCheck %s
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
; This tests very minimal fast-isel functionality. ; This tests very minimal fast-isel functionality.
; CHECK-LABEL: immediate_f32: ; CHECK-LABEL: immediate_f32:
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test/CodeGen/WebAssembly/frem.ll

; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals | FileCheck %s ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers | FileCheck %s
; Test that the frem instruction works. ; Test that the frem instruction works.
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
; CHECK-LABEL: frem32: ; CHECK-LABEL: frem32:
; CHECK-NEXT: .param f32, f32{{$}} ; CHECK-NEXT: .param f32, f32{{$}}
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test/CodeGen/WebAssembly/func.ll

; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals | FileCheck %s ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers | FileCheck %s
; Test that basic functions assemble as expected. ; Test that basic functions assemble as expected.
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
; CHECK-LABEL: f0: ; CHECK-LABEL: f0:
; CHECK: return{{$}} ; CHECK: return{{$}}
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test/CodeGen/WebAssembly/function-bitcasts-varargs.ll

; RUN: llc < %s -asm-verbose=false -wasm-temporary-workarounds=false | FileCheck %s ; RUN: llc < %s -asm-verbose=false -wasm-temporary-workarounds=false -wasm-keep-registers | FileCheck %s
; Test that function pointer casts casting away varargs are replaced with ; Test that function pointer casts casting away varargs are replaced with
; wrappers. ; wrappers.
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
define void @callWithArgs() { define void @callWithArgs() {
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test/CodeGen/WebAssembly/function-bitcasts.ll

; RUN: llc < %s -asm-verbose=false -disable-wasm-explicit-locals -enable-emscripten-cxx-exceptions -wasm-temporary-workarounds=false | FileCheck %s ; RUN: llc < %s -asm-verbose=false -wasm-disable-explicit-locals -wasm-keep-registers -enable-emscripten-cxx-exceptions -wasm-temporary-workarounds=false | FileCheck %s
; Test that function pointer casts are replaced with wrappers. ; Test that function pointer casts are replaced with wrappers.
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
declare void @has_i32_arg(i32) declare void @has_i32_arg(i32)
declare i32 @has_i32_ret() declare i32 @has_i32_ret()
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test/CodeGen/WebAssembly/global.ll

; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals | FileCheck %s ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers | FileCheck %s
; Test that globals assemble as expected. ; Test that globals assemble as expected.
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
; CHECK-NOT: llvm.used ; CHECK-NOT: llvm.used
; CHECK-NOT: llvm.metadata ; CHECK-NOT: llvm.metadata
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test/CodeGen/WebAssembly/i128.ll

; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt | FileCheck %s ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-keep-registers | FileCheck %s
; Test that basic 128-bit integer operations assemble as expected. ; Test that basic 128-bit integer operations assemble as expected.
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
declare i128 @llvm.ctlz.i128(i128, i1) declare i128 @llvm.ctlz.i128(i128, i1)
declare i128 @llvm.cttz.i128(i128, i1) declare i128 @llvm.cttz.i128(i128, i1)
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test/CodeGen/WebAssembly/i32-load-store-alignment.ll

; RUN: llc < %s -mattr=+atomics -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals | FileCheck %s ; RUN: llc < %s -mattr=+atomics -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers | FileCheck %s
; Test loads and stores with custom alignment values. ; Test loads and stores with custom alignment values.
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
;===---------------------------------------------------------------------------- ;===----------------------------------------------------------------------------
; Loads ; Loads
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test/CodeGen/WebAssembly/i32.ll

; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt | FileCheck %s ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-keep-registers | FileCheck %s
; Test that basic 32-bit integer operations assemble as expected. ; Test that basic 32-bit integer operations assemble as expected.
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
declare i32 @llvm.ctlz.i32(i32, i1) declare i32 @llvm.ctlz.i32(i32, i1)
declare i32 @llvm.cttz.i32(i32, i1) declare i32 @llvm.cttz.i32(i32, i1)
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test/CodeGen/WebAssembly/i64-load-store-alignment.ll

; RUN: llc < %s -mattr=+atomics -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals | FileCheck %s ; RUN: llc < %s -mattr=+atomics -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers | FileCheck %s
; Test loads and stores with custom alignment values. ; Test loads and stores with custom alignment values.
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
;===---------------------------------------------------------------------------- ;===----------------------------------------------------------------------------
; Loads ; Loads
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test/CodeGen/WebAssembly/i64.ll

; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt | FileCheck %s ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-keep-registers | FileCheck %s
; Test that basic 64-bit integer operations assemble as expected. ; Test that basic 64-bit integer operations assemble as expected.
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
declare i64 @llvm.ctlz.i64(i64, i1) declare i64 @llvm.ctlz.i64(i64, i1)
declare i64 @llvm.cttz.i64(i64, i1) declare i64 @llvm.cttz.i64(i64, i1)
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test/CodeGen/WebAssembly/ident.ll

; RUN: llc < %s -asm-verbose=false | FileCheck %s ; RUN: llc < %s -asm-verbose=false -wasm-keep-registers | FileCheck %s
; Test llvm.ident. ; Test llvm.ident.
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
; CHECK: .ident "hello world" ; CHECK: .ident "hello world"
!llvm.ident = !{!0} !llvm.ident = !{!0}
!0 = !{!"hello world"} !0 = !{!"hello world"}

test/CodeGen/WebAssembly/immediates.ll

; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt | FileCheck %s ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-keep-registers | FileCheck %s
; Test that basic immediates assemble as expected. ; Test that basic immediates assemble as expected.
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
; CHECK-LABEL: zero_i32: ; CHECK-LABEL: zero_i32:
; CHECK-NEXT: .result i32{{$}} ; CHECK-NEXT: .result i32{{$}}
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test/CodeGen/WebAssembly/implicit-def.ll

; RUN: llc -o - %s -asm-verbose=false | FileCheck %s ; RUN: llc -o - %s -asm-verbose=false -wasm-keep-registers | FileCheck %s
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
; Test that stackified IMPLICIT_DEF instructions are converted into ; Test that stackified IMPLICIT_DEF instructions are converted into
; CONST_I32 to provide an explicit push. ; CONST_I32 to provide an explicit push.
; CHECK: br_if 2, ; CHECK: br_if 2,
; CHECK: i32.const $push[[L0:[0-9]+]]=, 0{{$}} ; CHECK: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
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test/CodeGen/WebAssembly/import-module.ll

; RUN: llc < %s -asm-verbose=false | FileCheck %s ; RUN: llc < %s -asm-verbose=false -wasm-keep-registers | FileCheck %s
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
define void @test() { define void @test() {
call void @foo() call void @foo()
call void @plain() call void @plain()
ret void ret void
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test/CodeGen/WebAssembly/indirect-import.ll

; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -verify-machineinstrs | FileCheck %s ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-keep-registers -verify-machineinstrs | FileCheck %s
; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -verify-machineinstrs -fast-isel | FileCheck %s ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-keep-registers -verify-machineinstrs -fast-isel | FileCheck %s
; ModuleID = 'test/dot_s/indirect-import.c' ; ModuleID = 'test/dot_s/indirect-import.c'
source_filename = "test/dot_s/indirect-import.c" source_filename = "test/dot_s/indirect-import.c"
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32" target triple = "wasm32"
%struct.big = type { float, double, i32 } %struct.big = type { float, double, i32 }
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test/CodeGen/WebAssembly/inline-asm-m.ll

; RUN: not llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -no-integrated-as ; RUN: not llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -no-integrated-as
; Test basic inline assembly "m" operands, which are unsupported. Pass ; Test basic inline assembly "m" operands, which are unsupported. Pass
; -no-integrated-as since these aren't actually valid assembly syntax. ; -no-integrated-as since these aren't actually valid assembly syntax.
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
define void @bar(i32* %r, i32* %s) { define void @bar(i32* %r, i32* %s) {
entry: entry:
tail call void asm sideeffect "# $0 = bbb($1)", "=*m,*m"(i32* %s, i32* %r) #0, !srcloc !1 tail call void asm sideeffect "# $0 = bbb($1)", "=*m,*m"(i32* %s, i32* %r) #0, !srcloc !1
ret void ret void
} }

test/CodeGen/WebAssembly/inline-asm.ll

; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -no-integrated-as | FileCheck %s ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-keep-registers -no-integrated-as | FileCheck %s
; Test basic inline assembly. Pass -no-integrated-as since these aren't ; Test basic inline assembly. Pass -no-integrated-as since these aren't
; actually valid assembly syntax. ; actually valid assembly syntax.
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
; CHECK-LABEL: foo: ; CHECK-LABEL: foo:
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test/CodeGen/WebAssembly/irreducible-cfg.ll

; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-block-placement -disable-wasm-explicit-locals | FileCheck %s ; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-block-placement -wasm-disable-explicit-locals -wasm-keep-registers | FileCheck %s
; Test irreducible CFG handling. ; Test irreducible CFG handling.
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
; A simple loop with two entries. ; A simple loop with two entries.
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test/CodeGen/WebAssembly/legalize.ll

; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals | FileCheck %s ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers | FileCheck %s
; Test various types and operators that need to be legalized. ; Test various types and operators that need to be legalized.
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
; CHECK-LABEL: shl_i3: ; CHECK-LABEL: shl_i3:
; CHECK: i32.const $push0=, 7{{$}} ; CHECK: i32.const $push0=, 7{{$}}
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test/CodeGen/WebAssembly/libcalls.ll

; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt | FileCheck %s ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-keep-registers | FileCheck %s
; Test a subset of compiler-rt/libm libcalls expected to be emitted by the wasm backend ; Test a subset of compiler-rt/libm libcalls expected to be emitted by the wasm backend
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
declare fp128 @llvm.sqrt.f128(fp128) declare fp128 @llvm.sqrt.f128(fp128)
declare fp128 @llvm.floor.f128(fp128) declare fp128 @llvm.floor.f128(fp128)
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test/CodeGen/WebAssembly/load-ext-atomic.ll

; RUN: llc < %s -mattr=+atomics,+sign-ext -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals | FileCheck %s ; RUN: llc < %s -mattr=+atomics,+sign-ext -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers | FileCheck %s
; Test that extending loads are assembled properly. ; Test that extending loads are assembled properly.
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
; CHECK-LABEL: sext_i8_i32: ; CHECK-LABEL: sext_i8_i32:
; CHECK: i32.atomic.load8_u $push0=, 0($0){{$}} ; CHECK: i32.atomic.load8_u $push0=, 0($0){{$}}
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test/CodeGen/WebAssembly/load-ext.ll

; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals | FileCheck %s ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers | FileCheck %s
; Test that extending loads are assembled properly. ; Test that extending loads are assembled properly.
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
; CHECK-LABEL: sext_i8_i32: ; CHECK-LABEL: sext_i8_i32:
; CHECK: i32.load8_s $push0=, 0($0){{$}} ; CHECK: i32.load8_s $push0=, 0($0){{$}}
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test/CodeGen/WebAssembly/load-store-i1.ll

; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals | FileCheck %s ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers | FileCheck %s
; Test that i1 extending loads and truncating stores are assembled properly. ; Test that i1 extending loads and truncating stores are assembled properly.
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
; CHECK-LABEL: load_u_i1_i32: ; CHECK-LABEL: load_u_i1_i32:
; CHECK: i32.load8_u $push[[NUM0:[0-9]+]]=, 0($0){{$}} ; CHECK: i32.load8_u $push[[NUM0:[0-9]+]]=, 0($0){{$}}
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test/CodeGen/WebAssembly/load.ll

; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt | FileCheck %s ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-keep-registers | FileCheck %s
; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -fast-isel -fast-isel-abort=1 | FileCheck %s ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-keep-registers -fast-isel -fast-isel-abort=1 | FileCheck %s
; Test that basic loads are assembled properly. ; Test that basic loads are assembled properly.
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
; CHECK-LABEL: ldi32: ; CHECK-LABEL: ldi32:
; CHECK-NEXT: .param i32{{$}} ; CHECK-NEXT: .param i32{{$}}
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test/CodeGen/WebAssembly/lower-em-ehsjlj-options.ll

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; NONE-LABEL: type setjmp_longjmp,@function ; NONE-LABEL: type setjmp_longjmp,@function
entry: entry:
%buf = alloca [1 x %struct.__jmp_buf_tag], align 16 %buf = alloca [1 x %struct.__jmp_buf_tag], align 16
%arraydecay = getelementptr inbounds [1 x %struct.__jmp_buf_tag], [1 x %struct.__jmp_buf_tag]* %buf, i32 0, i32 0 %arraydecay = getelementptr inbounds [1 x %struct.__jmp_buf_tag], [1 x %struct.__jmp_buf_tag]* %buf, i32 0, i32 0
%call = call i32 @setjmp(%struct.__jmp_buf_tag* %arraydecay) #0 %call = call i32 @setjmp(%struct.__jmp_buf_tag* %arraydecay) #0
%arraydecay1 = getelementptr inbounds [1 x %struct.__jmp_buf_tag], [1 x %struct.__jmp_buf_tag]* %buf, i32 0, i32 0 %arraydecay1 = getelementptr inbounds [1 x %struct.__jmp_buf_tag], [1 x %struct.__jmp_buf_tag]* %buf, i32 0, i32 0
call void @longjmp(%struct.__jmp_buf_tag* %arraydecay1, i32 1) #1 call void @longjmp(%struct.__jmp_buf_tag* %arraydecay1, i32 1) #1
unreachable unreachable
; SJLJ: i32.call ${{[a-zA-Z0-9]+}}=, saveSetjmp@FUNCTION ; SJLJ: i32.call saveSetjmp@FUNCTION
; SJLJ: i32.call ${{[a-zA-Z0-9]+}}=, testSetjmp@FUNCTION ; SJLJ: i32.call testSetjmp@FUNCTION
; NONE: i32.call ${{[a-zA-Z0-9]+}}=, setjmp@FUNCTION ; NONE: i32.call setjmp@FUNCTION
; NONE: call longjmp@FUNCTION ; NONE: call longjmp@FUNCTION
} }
declare void @foo() declare void @foo()
declare i32 @__gxx_personality_v0(...) declare i32 @__gxx_personality_v0(...)
declare i8* @__cxa_begin_catch(i8*) declare i8* @__cxa_begin_catch(i8*)
declare void @__cxa_end_catch() declare void @__cxa_end_catch()
; Function Attrs: returns_twice ; Function Attrs: returns_twice
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test/CodeGen/WebAssembly/lower-global-dtors.ll

; RUN: llc < %s -asm-verbose=false | FileCheck --check-prefix=CHECK --check-prefix=FINI --check-prefix=NULL %s ; RUN: llc < %s -asm-verbose=false -wasm-keep-registers | FileCheck --check-prefix=CHECK --check-prefix=FINI --check-prefix=NULL %s
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
; Test that @llvm.global_dtors is properly lowered into @llvm.global_ctors, ; Test that @llvm.global_dtors is properly lowered into @llvm.global_ctors,
; grouping dtor calls by priority and associated symbol. ; grouping dtor calls by priority and associated symbol.
declare void @orig_ctor() declare void @orig_ctor()
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test/CodeGen/WebAssembly/mem-intrinsics.ll

; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -tail-dup-placement=0 | FileCheck %s ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -tail-dup-placement=0 | FileCheck %s
; Test memcpy, memmove, and memset intrinsics. ; Test memcpy, memmove, and memset intrinsics.
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture readonly, i32, i1) declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture readonly, i32, i1)
declare void @llvm.memmove.p0i8.p0i8.i32(i8* nocapture, i8* nocapture readonly, i32, i1) declare void @llvm.memmove.p0i8.p0i8.i32(i8* nocapture, i8* nocapture readonly, i32, i1)
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test/CodeGen/WebAssembly/memory-addr32.ll

; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals | FileCheck %s ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers | FileCheck %s
; Test that basic memory operations assemble as expected with 32-bit addresses. ; Test that basic memory operations assemble as expected with 32-bit addresses.
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
declare i32 @llvm.wasm.memory.size.i32(i32) nounwind readonly declare i32 @llvm.wasm.memory.size.i32(i32) nounwind readonly
declare i32 @llvm.wasm.memory.grow.i32(i32, i32) nounwind declare i32 @llvm.wasm.memory.grow.i32(i32, i32) nounwind
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test/CodeGen/WebAssembly/muloti4.ll

; RUN: llc -asm-verbose=false < %s | FileCheck %s ; RUN: llc -asm-verbose=false < %s -wasm-keep-registers | FileCheck %s
; Test that 128-bit smul.with.overflow assembles as expected. ; Test that 128-bit smul.with.overflow assembles as expected.
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
define i128 @call_muloti4(i128 %a, i128 %b) nounwind { define i128 @call_muloti4(i128 %a, i128 %b) nounwind {
entry: entry:
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test/CodeGen/WebAssembly/negative-base-reg.ll

; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt | FileCheck %s ; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-keep-registers | FileCheck %s
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
@args = hidden local_unnamed_addr global [32 x i32] zeroinitializer, align 16 @args = hidden local_unnamed_addr global [32 x i32] zeroinitializer, align 16
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define hidden i32 @main() local_unnamed_addr #0 { define hidden i32 @main() local_unnamed_addr #0 {
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test/CodeGen/WebAssembly/offset-atomics.ll

; RUN: not llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt ; RUN: not llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt
; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -mattr=+atomics,+sign-ext | FileCheck %s ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+atomics,+sign-ext | FileCheck %s
; Test that atomic loads are assembled properly. ; Test that atomic loads are assembled properly.
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
;===---------------------------------------------------------------------------- ;===----------------------------------------------------------------------------
; Atomic loads: 32-bit ; Atomic loads: 32-bit
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test/CodeGen/WebAssembly/offset-fastisel.ll

; RUN: llc < %s -asm-verbose=false -disable-wasm-explicit-locals -fast-isel -fast-isel-abort=1 | FileCheck %s ; RUN: llc < %s -asm-verbose=false -wasm-disable-explicit-locals -wasm-keep-registers -fast-isel -fast-isel-abort=1 | FileCheck %s
; TODO: Merge this with offset.ll when fast-isel matches better. ; TODO: Merge this with offset.ll when fast-isel matches better.
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
; CHECK-LABEL: store_i8_with_variable_gep_offset: ; CHECK-LABEL: store_i8_with_variable_gep_offset:
; CHECK: i32.add $push[[L0:[0-9]+]]=, $0, $1{{$}} ; CHECK: i32.add $push[[L0:[0-9]+]]=, $0, $1{{$}}
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test/CodeGen/WebAssembly/offset-folding.ll

; RUN: llc < %s -asm-verbose=false | FileCheck %s ; RUN: llc < %s -asm-verbose=false -wasm-keep-registers | FileCheck %s
; Test that constant offsets can be folded into global addresses. ; Test that constant offsets can be folded into global addresses.
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
@x = external global [0 x i32] @x = external global [0 x i32]
@y = global [50 x i32] zeroinitializer @y = global [50 x i32] zeroinitializer
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test/CodeGen/WebAssembly/offset.ll

; RUN: llc < %s -asm-verbose=false -disable-wasm-explicit-locals -disable-wasm-fallthrough-return-opt | FileCheck %s ; RUN: llc < %s -asm-verbose=false -wasm-disable-explicit-locals -wasm-keep-registers -disable-wasm-fallthrough-return-opt | FileCheck %s
; Test constant load and store address offsets. ; Test constant load and store address offsets.
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
;===---------------------------------------------------------------------------- ;===----------------------------------------------------------------------------
; Loads: 32-bit ; Loads: 32-bit
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test/CodeGen/WebAssembly/phi.ll

; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -verify-machineinstrs | FileCheck %s ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -verify-machineinstrs | FileCheck %s
; Test that phis are lowered. ; Test that phis are lowered.
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
; Basic phi triangle. ; Basic phi triangle.
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test/CodeGen/WebAssembly/reg-stackify.ll

; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -verify-machineinstrs | FileCheck %s ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -verify-machineinstrs | FileCheck %s
; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -verify-machineinstrs | FileCheck %s --check-prefix=NOREGS
; Test the register stackifier pass. ; Test the register stackifier pass.
; We have two sets of tests, one with registers and implicit locals, and
; a stack / explicit locals based version (NOREGS).
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
; No because of pointer aliasing. ; No because of pointer aliasing.
; CHECK-LABEL: no0: ; CHECK-LABEL: no0:
; CHECK: return $1{{$}} ; CHECK: return $1{{$}}
; NOREGS-LABEL: no0:
; NOREGS: return{{$}}
define i32 @no0(i32* %p, i32* %q) { define i32 @no0(i32* %p, i32* %q) {
%t = load i32, i32* %q %t = load i32, i32* %q
store i32 0, i32* %p store i32 0, i32* %p
ret i32 %t ret i32 %t
} }
; No because of side effects. ; No because of side effects.
; CHECK-LABEL: no1: ; CHECK-LABEL: no1:
; CHECK: return $1{{$}} ; CHECK: return $1{{$}}
; NOREGS-LABEL: no1:
; NOREGS: return{{$}}
define i32 @no1(i32* %p, i32* dereferenceable(4) %q) { define i32 @no1(i32* %p, i32* dereferenceable(4) %q) {
%t = load volatile i32, i32* %q, !invariant.load !0 %t = load volatile i32, i32* %q, !invariant.load !0
store volatile i32 0, i32* %p store volatile i32 0, i32* %p
ret i32 %t ret i32 %t
} }
; Yes because of invariant load and no side effects. ; Yes because of invariant load and no side effects.
; CHECK-LABEL: yes0: ; CHECK-LABEL: yes0:
; CHECK: return $pop{{[0-9]+}}{{$}} ; CHECK: return $pop{{[0-9]+}}{{$}}
; NOREGS-LABEL: yes0:
; NOREGS: return{{$}}
define i32 @yes0(i32* %p, i32* dereferenceable(4) %q) { define i32 @yes0(i32* %p, i32* dereferenceable(4) %q) {
%t = load i32, i32* %q, !invariant.load !0 %t = load i32, i32* %q, !invariant.load !0
store i32 0, i32* %p store i32 0, i32* %p
ret i32 %t ret i32 %t
} }
; Yes because of no intervening side effects. ; Yes because of no intervening side effects.
; CHECK-LABEL: yes1: ; CHECK-LABEL: yes1:
; CHECK: return $pop0{{$}} ; CHECK: return $pop0{{$}}
; NOREGS-LABEL: yes1:
; NOREGS: return{{$}}
define i32 @yes1(i32* %q) { define i32 @yes1(i32* %q) {
%t = load volatile i32, i32* %q %t = load volatile i32, i32* %q
ret i32 %t ret i32 %t
} }
; Yes because undefined behavior can be sunk past a store. ; Yes because undefined behavior can be sunk past a store.
; CHECK-LABEL: sink_trap: ; CHECK-LABEL: sink_trap:
; CHECK: return $pop{{[0-9]+}}{{$}} ; CHECK: return $pop{{[0-9]+}}{{$}}
; NOREGS-LABEL: sink_trap:
; NOREGS: return{{$}}
define i32 @sink_trap(i32 %x, i32 %y, i32* %p) { define i32 @sink_trap(i32 %x, i32 %y, i32* %p) {
%t = sdiv i32 %x, %y %t = sdiv i32 %x, %y
store volatile i32 0, i32* %p store volatile i32 0, i32* %p
ret i32 %t ret i32 %t
} }
; Yes because the call is readnone. ; Yes because the call is readnone.
; CHECK-LABEL: sink_readnone_call: ; CHECK-LABEL: sink_readnone_call:
; CHECK: return $pop0{{$}} ; CHECK: return $pop0{{$}}
; NOREGS-LABEL: sink_readnone_call:
; NOREGS: return{{$}}
declare i32 @readnone_callee() readnone nounwind declare i32 @readnone_callee() readnone nounwind
define i32 @sink_readnone_call(i32 %x, i32 %y, i32* %p) { define i32 @sink_readnone_call(i32 %x, i32 %y, i32* %p) {
%t = call i32 @readnone_callee() %t = call i32 @readnone_callee()
store volatile i32 0, i32* %p store volatile i32 0, i32* %p
ret i32 %t ret i32 %t
} }
; No because the call is readonly and there's an intervening store. ; No because the call is readonly and there's an intervening store.
; CHECK-LABEL: no_sink_readonly_call: ; CHECK-LABEL: no_sink_readonly_call:
; CHECK: return ${{[0-9]+}}{{$}} ; CHECK: return ${{[0-9]+}}{{$}}
; NOREGS-LABEL: no_sink_readonly_call:
; NOREGS: return{{$}}
declare i32 @readonly_callee() readonly nounwind declare i32 @readonly_callee() readonly nounwind
define i32 @no_sink_readonly_call(i32 %x, i32 %y, i32* %p) { define i32 @no_sink_readonly_call(i32 %x, i32 %y, i32* %p) {
%t = call i32 @readonly_callee() %t = call i32 @readonly_callee()
store i32 0, i32* %p store i32 0, i32* %p
ret i32 %t ret i32 %t
} }
; Don't schedule stack uses into the stack. To reduce register pressure, the ; Don't schedule stack uses into the stack. To reduce register pressure, the
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; CHECK-NEXT: i32.ne $push8=, $pop7, $pop10{{$}} ; CHECK-NEXT: i32.ne $push8=, $pop7, $pop10{{$}}
; CHECK-NEXT: br_if 0, $pop8{{$}} ; CHECK-NEXT: br_if 0, $pop8{{$}}
; CHECK-NEXT: i32.const $push9=, 0{{$}} ; CHECK-NEXT: i32.const $push9=, 0{{$}}
; CHECK-NEXT: return $pop9{{$}} ; CHECK-NEXT: return $pop9{{$}}
; CHECK-NEXT: .LBB7_2: ; CHECK-NEXT: .LBB7_2:
; CHECK-NEXT: end_block{{$}} ; CHECK-NEXT: end_block{{$}}
; CHECK-NEXT: i32.const $push14=, 1{{$}} ; CHECK-NEXT: i32.const $push14=, 1{{$}}
; CHECK-NEXT: return $pop14{{$}} ; CHECK-NEXT: return $pop14{{$}}
; NOREGS-LABEL: stack_uses:
; NOREGS: .param i32, i32, i32, i32{{$}}
; NOREGS-NEXT: .result i32{{$}}
; NOREGS-NEXT: block {{$}}
; NOREGS-NEXT: get_local 0{{$}}
; NOREGS-NEXT: i32.const 1{{$}}
; NOREGS-NEXT: i32.lt_s
; NOREGS-NEXT: get_local 1{{$}}
; NOREGS-NEXT: i32.const 2{{$}}
; NOREGS-NEXT: i32.lt_s
; NOREGS-NEXT: i32.xor {{$}}
; NOREGS-NEXT: get_local 2{{$}}
; NOREGS-NEXT: i32.const 1{{$}}
; NOREGS-NEXT: i32.lt_s
; NOREGS-NEXT: get_local 3{{$}}
; NOREGS-NEXT: i32.const 2{{$}}
; NOREGS-NEXT: i32.lt_s
; NOREGS-NEXT: i32.xor {{$}}
; NOREGS-NEXT: i32.xor {{$}}
; NOREGS-NEXT: i32.const 1{{$}}
; NOREGS-NEXT: i32.ne {{$}}
; NOREGS-NEXT: br_if 0{{$}}
; NOREGS-NEXT: i32.const 0{{$}}
; NOREGS-NEXT: return{{$}}
; NOREGS-NEXT: .LBB7_2:
; NOREGS-NEXT: end_block{{$}}
; NOREGS-NEXT: i32.const 1{{$}}
; NOREGS-NEXT: return{{$}}
define i32 @stack_uses(i32 %x, i32 %y, i32 %z, i32 %w) { define i32 @stack_uses(i32 %x, i32 %y, i32 %z, i32 %w) {
entry: entry:
%c = icmp sle i32 %x, 0 %c = icmp sle i32 %x, 0
%d = icmp sle i32 %y, 1 %d = icmp sle i32 %y, 1
%e = icmp sle i32 %z, 0 %e = icmp sle i32 %z, 0
%f = icmp sle i32 %w, 1 %f = icmp sle i32 %w, 1
%g = xor i1 %c, %d %g = xor i1 %c, %d
%h = xor i1 %e, %f %h = xor i1 %e, %f
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; CHECK-NEXT: i32.ge_u $push[[NUM2:[0-9]+]]=, $pop[[NUM1]], $1{{$}} ; CHECK-NEXT: i32.ge_u $push[[NUM2:[0-9]+]]=, $pop[[NUM1]], $1{{$}}
; CHECK-NEXT: br_if 0, $pop[[NUM2]]{{$}} ; CHECK-NEXT: br_if 0, $pop[[NUM2]]{{$}}
; CHECK-NEXT: i32.lt_u $push[[NUM3:[0-9]+]]=, $3, $0{{$}} ; CHECK-NEXT: i32.lt_u $push[[NUM3:[0-9]+]]=, $3, $0{{$}}
; CHECK-NEXT: br_if 0, $pop[[NUM3]]{{$}} ; CHECK-NEXT: br_if 0, $pop[[NUM3]]{{$}}
; CHECK-NEXT: i32.store 0($2), $3{{$}} ; CHECK-NEXT: i32.store 0($2), $3{{$}}
; CHECK-NEXT: .LBB8_3: ; CHECK-NEXT: .LBB8_3:
; CHECK-NEXT: end_block{{$}} ; CHECK-NEXT: end_block{{$}}
; CHECK-NEXT: return{{$}} ; CHECK-NEXT: return{{$}}
; NOREGS-LABEL: multiple_uses:
; NOREGS: .param i32, i32, i32{{$}}
; NOREGS: .local i32{{$}}
; NOREGS-NEXT: block {{$}}
; NOREGS-NEXT: get_local 2{{$}}
; NOREGS-NEXT: i32.load 0{{$}}
; NOREGS-NEXT: tee_local 3{{$}}
; NOREGS-NEXT: get_local 1{{$}}
; NOREGS-NEXT: i32.ge_u
; NOREGS-NEXT: br_if 0{{$}}
; NOREGS-NEXT: get_local 3{{$}}
; NOREGS-NEXT: get_local 0{{$}}
; NOREGS-NEXT: i32.lt_u
; NOREGS-NEXT: br_if 0{{$}}
; NOREGS-NEXT: get_local 2{{$}}
; NOREGS-NEXT: get_local 3{{$}}
; NOREGS-NEXT: i32.store 0{{$}}
; NOREGS-NEXT: .LBB8_3:
; NOREGS-NEXT: end_block{{$}}
; NOREGS-NEXT: return{{$}}
define void @multiple_uses(i32* %arg0, i32* %arg1, i32* %arg2) nounwind { define void @multiple_uses(i32* %arg0, i32* %arg1, i32* %arg2) nounwind {
bb: bb:
br label %loop br label %loop
loop: loop:
%tmp7 = load i32, i32* %arg2 %tmp7 = load i32, i32* %arg2
%tmp8 = inttoptr i32 %tmp7 to i32* %tmp8 = inttoptr i32 %tmp7 to i32*
%tmp9 = icmp uge i32* %tmp8, %arg1 %tmp9 = icmp uge i32* %tmp8, %arg1
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; Don't stackify stores effects across other instructions with side effects. ; Don't stackify stores effects across other instructions with side effects.
; CHECK: side_effects: ; CHECK: side_effects:
; CHECK: store ; CHECK: store
; CHECK-NEXT: call ; CHECK-NEXT: call
; CHECK: store ; CHECK: store
; CHECK-NEXT: call ; CHECK-NEXT: call
; NOREGS: side_effects:
; NOREGS: store
; NOREGS-NEXT: call
; NOREGS: store
; NOREGS-NEXT: call
declare void @evoke_side_effects() declare void @evoke_side_effects()
define hidden void @stackify_store_across_side_effects(double* nocapture %d) { define hidden void @stackify_store_across_side_effects(double* nocapture %d) {
entry: entry:
store double 2.0, double* %d store double 2.0, double* %d
call void @evoke_side_effects() call void @evoke_side_effects()
store double 2.0, double* %d store double 2.0, double* %d
call void @evoke_side_effects() call void @evoke_side_effects()
ret void ret void
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; CHECK-NEXT: i32.div_s $push[[L8:[0-9]+]]=, $10, $11{{$}} ; CHECK-NEXT: i32.div_s $push[[L8:[0-9]+]]=, $10, $11{{$}}
; CHECK-NEXT: i32.div_s $push[[L9:[0-9]+]]=, $pop[[L7]], $pop[[L8]]{{$}} ; CHECK-NEXT: i32.div_s $push[[L9:[0-9]+]]=, $pop[[L7]], $pop[[L8]]{{$}}
; CHECK-NEXT: i32.div_s $push[[L10:[0-9]+]]=, $12, $13{{$}} ; CHECK-NEXT: i32.div_s $push[[L10:[0-9]+]]=, $12, $13{{$}}
; CHECK-NEXT: i32.div_s $push[[L11:[0-9]+]]=, $14, $15{{$}} ; CHECK-NEXT: i32.div_s $push[[L11:[0-9]+]]=, $14, $15{{$}}
; CHECK-NEXT: i32.div_s $push[[L12:[0-9]+]]=, $pop[[L10]], $pop[[L11]]{{$}} ; CHECK-NEXT: i32.div_s $push[[L12:[0-9]+]]=, $pop[[L10]], $pop[[L11]]{{$}}
; CHECK-NEXT: i32.div_s $push[[L13:[0-9]+]]=, $pop[[L9]], $pop[[L12]]{{$}} ; CHECK-NEXT: i32.div_s $push[[L13:[0-9]+]]=, $pop[[L9]], $pop[[L12]]{{$}}
; CHECK-NEXT: i32.div_s $push[[L14:[0-9]+]]=, $pop[[L6]], $pop[[L13]]{{$}} ; CHECK-NEXT: i32.div_s $push[[L14:[0-9]+]]=, $pop[[L6]], $pop[[L13]]{{$}}
; CHECK-NEXT: return $pop[[L14]]{{$}} ; CHECK-NEXT: return $pop[[L14]]{{$}}
; NOREGS-LABEL: div_tree:
; NOREGS: .param i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32{{$}}
; NOREGS-NEXT: .result i32{{$}}
; NOREGS-NEXT: get_local 0{{$}}
; NOREGS-NEXT: get_local 1{{$}}
; NOREGS-NEXT: i32.div_s{{$}}
; NOREGS-NEXT: get_local 2{{$}}
; NOREGS-NEXT: get_local 3{{$}}
; NOREGS-NEXT: i32.div_s{{$}}
; NOREGS-NEXT: i32.div_s{{$}}
; NOREGS-NEXT: get_local 4{{$}}
; NOREGS-NEXT: get_local 5{{$}}
; NOREGS-NEXT: i32.div_s{{$}}
; NOREGS-NEXT: get_local 6{{$}}
; NOREGS-NEXT: get_local 7{{$}}
; NOREGS-NEXT: i32.div_s{{$}}
; NOREGS-NEXT: i32.div_s{{$}}
; NOREGS-NEXT: i32.div_s{{$}}
; NOREGS-NEXT: get_local 8{{$}}
; NOREGS-NEXT: get_local 9{{$}}
; NOREGS-NEXT: i32.div_s{{$}}
; NOREGS-NEXT: get_local 10{{$}}
; NOREGS-NEXT: get_local 11{{$}}
; NOREGS-NEXT: i32.div_s{{$}}
; NOREGS-NEXT: i32.div_s{{$}}
; NOREGS-NEXT: get_local 12{{$}}
; NOREGS-NEXT: get_local 13{{$}}
; NOREGS-NEXT: i32.div_s{{$}}
; NOREGS-NEXT: get_local 14{{$}}
; NOREGS-NEXT: get_local 15{{$}}
; NOREGS-NEXT: i32.div_s{{$}}
; NOREGS-NEXT: i32.div_s{{$}}
; NOREGS-NEXT: i32.div_s{{$}}
; NOREGS-NEXT: i32.div_s{{$}}
; NOREGS-NEXT: return{{$}}
define i32 @div_tree(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h, i32 %i, i32 %j, i32 %k, i32 %l, i32 %m, i32 %n, i32 %o, i32 %p) { define i32 @div_tree(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h, i32 %i, i32 %j, i32 %k, i32 %l, i32 %m, i32 %n, i32 %o, i32 %p) {
entry: entry:
%div = sdiv i32 %a, %b %div = sdiv i32 %a, %b
%div1 = sdiv i32 %c, %d %div1 = sdiv i32 %c, %d
%div2 = sdiv i32 %div, %div1 %div2 = sdiv i32 %div, %div1
%div3 = sdiv i32 %e, %f %div3 = sdiv i32 %e, %f
%div4 = sdiv i32 %g, %h %div4 = sdiv i32 %g, %h
%div5 = sdiv i32 %div3, %div4 %div5 = sdiv i32 %div3, %div4
Show All 13 Lines
; CHECK-LABEL: simple_multiple_use: ; CHECK-LABEL: simple_multiple_use:
; CHECK: .param i32, i32{{$}} ; CHECK: .param i32, i32{{$}}
; CHECK-NEXT: i32.mul $push[[NUM0:[0-9]+]]=, $1, $0{{$}} ; CHECK-NEXT: i32.mul $push[[NUM0:[0-9]+]]=, $1, $0{{$}}
; CHECK-NEXT: tee_local $push[[NUM1:[0-9]+]]=, $[[NUM2:[0-9]+]]=, $pop[[NUM0]]{{$}} ; CHECK-NEXT: tee_local $push[[NUM1:[0-9]+]]=, $[[NUM2:[0-9]+]]=, $pop[[NUM0]]{{$}}
; CHECK-NEXT: call use_a@FUNCTION, $pop[[NUM1]]{{$}} ; CHECK-NEXT: call use_a@FUNCTION, $pop[[NUM1]]{{$}}
; CHECK-NEXT: call use_b@FUNCTION, $[[NUM2]]{{$}} ; CHECK-NEXT: call use_b@FUNCTION, $[[NUM2]]{{$}}
; CHECK-NEXT: return{{$}} ; CHECK-NEXT: return{{$}}
; NOREGS-LABEL: simple_multiple_use:
; NOREGS: .param i32, i32{{$}}
; NOREGS-NEXT: get_local 1{{$}}
; NOREGS-NEXT: get_local 0{{$}}
; NOREGS-NEXT: i32.mul
; NOREGS-NEXT: tee_local 1{{$}}
; NOREGS-NEXT: call use_a@FUNCTION{{$}}
; NOREGS-NEXT: get_local 1{{$}}
; NOREGS-NEXT: call use_b@FUNCTION{{$}}
; NOREGS-NEXT: return{{$}}
declare void @use_a(i32) declare void @use_a(i32)
declare void @use_b(i32) declare void @use_b(i32)
define void @simple_multiple_use(i32 %x, i32 %y) { define void @simple_multiple_use(i32 %x, i32 %y) {
%mul = mul i32 %y, %x %mul = mul i32 %y, %x
call void @use_a(i32 %mul) call void @use_a(i32 %mul)
call void @use_b(i32 %mul) call void @use_b(i32 %mul)
ret void ret void
} }
; Multiple uses of the same value in one instruction. ; Multiple uses of the same value in one instruction.
; CHECK-LABEL: multiple_uses_in_same_insn: ; CHECK-LABEL: multiple_uses_in_same_insn:
; CHECK: .param i32, i32{{$}} ; CHECK: .param i32, i32{{$}}
; CHECK-NEXT: i32.mul $push[[NUM0:[0-9]+]]=, $1, $0{{$}} ; CHECK-NEXT: i32.mul $push[[NUM0:[0-9]+]]=, $1, $0{{$}}
; CHECK-NEXT: tee_local $push[[NUM1:[0-9]+]]=, $[[NUM2:[0-9]+]]=, $pop[[NUM0]]{{$}} ; CHECK-NEXT: tee_local $push[[NUM1:[0-9]+]]=, $[[NUM2:[0-9]+]]=, $pop[[NUM0]]{{$}}
; CHECK-NEXT: call use_2@FUNCTION, $pop[[NUM1]], $[[NUM2]]{{$}} ; CHECK-NEXT: call use_2@FUNCTION, $pop[[NUM1]], $[[NUM2]]{{$}}
; CHECK-NEXT: return{{$}} ; CHECK-NEXT: return{{$}}
; NOREGS-LABEL: multiple_uses_in_same_insn:
; NOREGS: .param i32, i32{{$}}
; NOREGS-NEXT: get_local 1{{$}}
; NOREGS-NEXT: get_local 0{{$}}
; NOREGS-NEXT: i32.mul
; NOREGS-NEXT: tee_local 1{{$}}
; NOREGS-NEXT: get_local 1{{$}}
; NOREGS-NEXT: call use_2@FUNCTION{{$}}
; NOREGS-NEXT: return{{$}}
declare void @use_2(i32, i32) declare void @use_2(i32, i32)
define void @multiple_uses_in_same_insn(i32 %x, i32 %y) { define void @multiple_uses_in_same_insn(i32 %x, i32 %y) {
%mul = mul i32 %y, %x %mul = mul i32 %y, %x
call void @use_2(i32 %mul, i32 %mul) call void @use_2(i32 %mul, i32 %mul)
ret void ret void
} }
; Commute operands to achieve better stackifying. ; Commute operands to achieve better stackifying.
; CHECK-LABEL: commute: ; CHECK-LABEL: commute:
; CHECK-NOT: param ; CHECK-NOT: param
; CHECK: .result i32{{$}} ; CHECK: .result i32{{$}}
; CHECK-NEXT: i32.call $push0=, red@FUNCTION{{$}} ; CHECK-NEXT: i32.call $push0=, red@FUNCTION{{$}}
; CHECK-NEXT: i32.call $push1=, green@FUNCTION{{$}} ; CHECK-NEXT: i32.call $push1=, green@FUNCTION{{$}}
; CHECK-NEXT: i32.add $push2=, $pop0, $pop1{{$}} ; CHECK-NEXT: i32.add $push2=, $pop0, $pop1{{$}}
; CHECK-NEXT: i32.call $push3=, blue@FUNCTION{{$}} ; CHECK-NEXT: i32.call $push3=, blue@FUNCTION{{$}}
; CHECK-NEXT: i32.add $push4=, $pop2, $pop3{{$}} ; CHECK-NEXT: i32.add $push4=, $pop2, $pop3{{$}}
; CHECK-NEXT: return $pop4{{$}} ; CHECK-NEXT: return $pop4{{$}}
; NOREGS-LABEL: commute:
; NOREGS-NOT: param
; NOREGS: .result i32{{$}}
; NOREGS-NEXT: i32.call red@FUNCTION{{$}}
; NOREGS-NEXT: i32.call green@FUNCTION{{$}}
; NOREGS-NEXT: i32.add {{$}}
; NOREGS-NEXT: i32.call blue@FUNCTION{{$}}
; NOREGS-NEXT: i32.add {{$}}
; NOREGS-NEXT: return{{$}}
declare i32 @red() declare i32 @red()
declare i32 @green() declare i32 @green()
declare i32 @blue() declare i32 @blue()
define i32 @commute() { define i32 @commute() {
%call = call i32 @red() %call = call i32 @red()
%call1 = call i32 @green() %call1 = call i32 @green()
%add = add i32 %call1, %call %add = add i32 %call1, %call
%call2 = call i32 @blue() %call2 = call i32 @blue()
%add3 = add i32 %add, %call2 %add3 = add i32 %add, %call2
ret i32 %add3 ret i32 %add3
} }
; Don't stackify a register when it would move a the def of the register past ; Don't stackify a register when it would move a the def of the register past
; an implicit get_local for the register. ; an implicit get_local for the register.
; CHECK-LABEL: no_stackify_past_use: ; CHECK-LABEL: no_stackify_past_use:
; CHECK: i32.call $1=, callee@FUNCTION, $0 ; CHECK: i32.call $1=, callee@FUNCTION, $0
; CHECK-NEXT: i32.const $push0=, 1 ; CHECK-NEXT: i32.const $push0=, 1
; CHECK-NEXT: i32.add $push1=, $0, $pop0 ; CHECK-NEXT: i32.add $push1=, $0, $pop0
; CHECK-NEXT: i32.call $push2=, callee@FUNCTION, $pop1 ; CHECK-NEXT: i32.call $push2=, callee@FUNCTION, $pop1
; CHECK-NEXT: i32.sub $push3=, $pop2, $1 ; CHECK-NEXT: i32.sub $push3=, $pop2, $1
; CHECK-NEXT: i32.div_s $push4=, $pop3, $1 ; CHECK-NEXT: i32.div_s $push4=, $pop3, $1
; CHECK-NEXT: return $pop4 ; CHECK-NEXT: return $pop4
; NOREGS-LABEL: no_stackify_past_use:
; NOREGS: get_local 0{{$}}
; NOREGS-NEXT: i32.call callee@FUNCTION
; NOREGS-NEXT: set_local 1{{$}}
; NOREGS-NEXT: get_local 0{{$}}
; NOREGS-NEXT: i32.const 1
; NOREGS-NEXT: i32.add
; NOREGS-NEXT: i32.call callee@FUNCTION
; NOREGS-NEXT: get_local 1{{$}}
; NOREGS-NEXT: i32.sub
; NOREGS-NEXT: get_local 1{{$}}
; NOREGS-NEXT: i32.div_s
; NOREGS-NEXT: return
declare i32 @callee(i32) declare i32 @callee(i32)
define i32 @no_stackify_past_use(i32 %arg) { define i32 @no_stackify_past_use(i32 %arg) {
%tmp1 = call i32 @callee(i32 %arg) %tmp1 = call i32 @callee(i32 %arg)
%tmp2 = add i32 %arg, 1 %tmp2 = add i32 %arg, 1
%tmp3 = call i32 @callee(i32 %tmp2) %tmp3 = call i32 @callee(i32 %tmp2)
%tmp5 = sub i32 %tmp3, %tmp1 %tmp5 = sub i32 %tmp3, %tmp1
%tmp6 = sdiv i32 %tmp5, %tmp1 %tmp6 = sdiv i32 %tmp5, %tmp1
ret i32 %tmp6 ret i32 %tmp6
} }
; This is the same as no_stackify_past_use, except using a commutative operator, ; This is the same as no_stackify_past_use, except using a commutative operator,
; so we can reorder the operands and stackify. ; so we can reorder the operands and stackify.
; CHECK-LABEL: commute_to_fix_ordering: ; CHECK-LABEL: commute_to_fix_ordering:
; CHECK: i32.call $push[[L0:.+]]=, callee@FUNCTION, $0 ; CHECK: i32.call $push[[L0:.+]]=, callee@FUNCTION, $0
; CHECK: tee_local $push[[L1:.+]]=, $1=, $pop[[L0]] ; CHECK: tee_local $push[[L1:.+]]=, $1=, $pop[[L0]]
; CHECK: i32.const $push0=, 1 ; CHECK: i32.const $push0=, 1
; CHECK: i32.add $push1=, $0, $pop0 ; CHECK: i32.add $push1=, $0, $pop0
; CHECK: i32.call $push2=, callee@FUNCTION, $pop1 ; CHECK: i32.call $push2=, callee@FUNCTION, $pop1
; CHECK: i32.add $push3=, $1, $pop2 ; CHECK: i32.add $push3=, $1, $pop2
; CHECK: i32.mul $push4=, $pop[[L1]], $pop3 ; CHECK: i32.mul $push4=, $pop[[L1]], $pop3
; CHECK: return $pop4 ; CHECK: return $pop4
; NOREGS-LABEL: commute_to_fix_ordering:
; NOREGS: get_local 0{{$}}
; NOREGS: i32.call callee@FUNCTION
; NOREGS: tee_local 1
; NOREGS: get_local 1{{$}}
; NOREGS: get_local 0{{$}}
; NOREGS: i32.const 1
; NOREGS: i32.add
; NOREGS: i32.call callee@FUNCTION
; NOREGS: i32.add
; NOREGS: i32.mul
; NOREGS: return
define i32 @commute_to_fix_ordering(i32 %arg) { define i32 @commute_to_fix_ordering(i32 %arg) {
%tmp1 = call i32 @callee(i32 %arg) %tmp1 = call i32 @callee(i32 %arg)
%tmp2 = add i32 %arg, 1 %tmp2 = add i32 %arg, 1
%tmp3 = call i32 @callee(i32 %tmp2) %tmp3 = call i32 @callee(i32 %tmp2)
%tmp5 = add i32 %tmp3, %tmp1 %tmp5 = add i32 %tmp3, %tmp1
%tmp6 = mul i32 %tmp5, %tmp1 %tmp6 = mul i32 %tmp5, %tmp1
ret i32 %tmp6 ret i32 %tmp6
} }
; Stackify individual defs of virtual registers with multiple defs. ; Stackify individual defs of virtual registers with multiple defs.
; CHECK-LABEL: multiple_defs: ; CHECK-LABEL: multiple_defs:
; CHECK: f64.add $push[[NUM0:[0-9]+]]=, ${{[0-9]+}}, $pop{{[0-9]+}}{{$}} ; CHECK: f64.add $push[[NUM0:[0-9]+]]=, ${{[0-9]+}}, $pop{{[0-9]+}}{{$}}
; CHECK-NEXT: tee_local $push[[NUM1:[0-9]+]]=, $[[NUM2:[0-9]+]]=, $pop[[NUM0]]{{$}} ; CHECK-NEXT: tee_local $push[[NUM1:[0-9]+]]=, $[[NUM2:[0-9]+]]=, $pop[[NUM0]]{{$}}
; CHECK-NEXT: f64.select $push{{[0-9]+}}=, $pop{{[0-9]+}}, $pop[[NUM1]], ${{[0-9]+}}{{$}} ; CHECK-NEXT: f64.select $push{{[0-9]+}}=, $pop{{[0-9]+}}, $pop[[NUM1]], ${{[0-9]+}}{{$}}
; CHECK: $[[NUM2]]=, ; CHECK: $[[NUM2]]=,
; NOREGS-LABEL: multiple_defs:
; NOREGS: f64.add
; NOREGS: tee_local
; NOREGS: f64.select
define void @multiple_defs(i32 %arg, i32 %arg1, i1 %arg2, i1 %arg3, i1 %arg4) { define void @multiple_defs(i32 %arg, i32 %arg1, i1 %arg2, i1 %arg3, i1 %arg4) {
bb: bb:
br label %bb5 br label %bb5
bb5: ; preds = %bb21, %bb bb5: ; preds = %bb21, %bb
%tmp = phi double [ 0.000000e+00, %bb ], [ %tmp22, %bb21 ] %tmp = phi double [ 0.000000e+00, %bb ], [ %tmp22, %bb21 ]
%tmp6 = phi double [ 0.000000e+00, %bb ], [ %tmp23, %bb21 ] %tmp6 = phi double [ 0.000000e+00, %bb ], [ %tmp23, %bb21 ]
%tmp7 = fcmp olt double %tmp6, 2.323450e+01 %tmp7 = fcmp olt double %tmp6, 2.323450e+01
Show All 26 Linesexit:
ret void ret void
} }
; Don't move calls past loads ; Don't move calls past loads
; CHECK-LABEL: no_stackify_call_past_load: ; CHECK-LABEL: no_stackify_call_past_load:
; CHECK: i32.call $0=, red ; CHECK: i32.call $0=, red
; CHECK: i32.const $push0=, 0 ; CHECK: i32.const $push0=, 0
; CHECK: i32.load $1=, count($pop0) ; CHECK: i32.load $1=, count($pop0)
; NOREGS-LABEL: no_stackify_call_past_load:
; NOREGS: i32.call red
; NOREGS: i32.const 0
; NOREGS: i32.load count
@count = hidden global i32 0, align 4 @count = hidden global i32 0, align 4
define i32 @no_stackify_call_past_load() { define i32 @no_stackify_call_past_load() {
%a = call i32 @red() %a = call i32 @red()
%b = load i32, i32* @count, align 4 %b = load i32, i32* @count, align 4
call i32 @callee(i32 %a) call i32 @callee(i32 %a)
ret i32 %b ret i32 %b
; use of a ; use of a
} }
; Don't move stores past loads if there may be aliasing ; Don't move stores past loads if there may be aliasing
; CHECK-LABEL: no_stackify_store_past_load ; CHECK-LABEL: no_stackify_store_past_load
; CHECK: i32.store 0($1), $0 ; CHECK: i32.store 0($1), $0
; CHECK: i32.load {{.*}}, 0($2) ; CHECK: i32.load {{.*}}, 0($2)
; CHECK: i32.call {{.*}}, callee@FUNCTION, $0{{$}} ; CHECK: i32.call {{.*}}, callee@FUNCTION, $0{{$}}
; NOREGS-LABEL: no_stackify_store_past_load
; NOREGS: i32.store 0
; NOREGS: i32.load 0
; NOREGS: i32.call callee@FUNCTION{{$}}
define i32 @no_stackify_store_past_load(i32 %a, i32* %p1, i32* %p2) { define i32 @no_stackify_store_past_load(i32 %a, i32* %p1, i32* %p2) {
store i32 %a, i32* %p1 store i32 %a, i32* %p1
%b = load i32, i32* %p2, align 4 %b = load i32, i32* %p2, align 4
call i32 @callee(i32 %a) call i32 @callee(i32 %a)
ret i32 %b ret i32 %b
} }
; Can still stackify past invariant loads. ; Can still stackify past invariant loads.
; CHECK-LABEL: store_past_invar_load ; CHECK-LABEL: store_past_invar_load
; CHECK: i32.store 0($1), $0 ; CHECK: i32.store 0($1), $0
; CHECK: i32.call {{.*}}, callee@FUNCTION, $0 ; CHECK: i32.call {{.*}}, callee@FUNCTION, $0
; CHECK: i32.load $push{{.*}}, 0($2) ; CHECK: i32.load $push{{.*}}, 0($2)
; CHECK: return $pop ; CHECK: return $pop
; NOREGS-LABEL: store_past_invar_load
; NOREGS: i32.store 0
; NOREGS: i32.call callee@FUNCTION
; NOREGS: i32.load 0
; NOREGS: return
define i32 @store_past_invar_load(i32 %a, i32* %p1, i32* dereferenceable(4) %p2) { define i32 @store_past_invar_load(i32 %a, i32* %p1, i32* dereferenceable(4) %p2) {
store i32 %a, i32* %p1 store i32 %a, i32* %p1
%b = load i32, i32* %p2, !invariant.load !0 %b = load i32, i32* %p2, !invariant.load !0
call i32 @callee(i32 %a) call i32 @callee(i32 %a)
ret i32 %b ret i32 %b
} }
; CHECK-LABEL: ignore_dbg_value: ; CHECK-LABEL: ignore_dbg_value:
; CHECK-NEXT: .Lfunc_begin ; CHECK-NEXT: .Lfunc_begin
; CHECK-NEXT: unreachable ; CHECK-NEXT: unreachable
; NOREGS-LABEL: ignore_dbg_value:
; NOREGS-NEXT: .Lfunc_begin
; NOREGS-NEXT: unreachable
declare void @llvm.dbg.value(metadata, i64, metadata, metadata) declare void @llvm.dbg.value(metadata, i64, metadata, metadata)
define void @ignore_dbg_value() { define void @ignore_dbg_value() {
call void @llvm.dbg.value(metadata i32 0, i64 0, metadata !7, metadata !9), !dbg !10 call void @llvm.dbg.value(metadata i32 0, i64 0, metadata !7, metadata !9), !dbg !10
unreachable unreachable
} }
; Don't stackify an expression that might use the stack into a return, since we ; Don't stackify an expression that might use the stack into a return, since we
; might insert a prologue before the return. ; might insert a prologue before the return.
; CHECK-LABEL: no_stackify_past_epilogue: ; CHECK-LABEL: no_stackify_past_epilogue:
; CHECK: return ${{[0-9]+}}{{$}} ; CHECK: return ${{[0-9]+}}{{$}}
; NOREGS-LABEL: no_stackify_past_epilogue:
; NOREGS: return{{$}}
declare i32 @use_memory(i32*) declare i32 @use_memory(i32*)
define i32 @no_stackify_past_epilogue() { define i32 @no_stackify_past_epilogue() {
%x = alloca i32 %x = alloca i32
%call = call i32 @use_memory(i32* %x) %call = call i32 @use_memory(i32* %x)
ret i32 %call ret i32 %call
} }
; Stackify a loop induction variable into a loop comparison. ; Stackify a loop induction variable into a loop comparison.
; CHECK-LABEL: stackify_indvar: ; CHECK-LABEL: stackify_indvar:
; CHECK: i32.const $push[[L5:.+]]=, 1{{$}} ; CHECK: i32.const $push[[L5:.+]]=, 1{{$}}
; CHECK-NEXT: i32.add $push[[L4:.+]]=, $[[R0:.+]], $pop[[L5]]{{$}} ; CHECK-NEXT: i32.add $push[[L4:.+]]=, $[[R0:.+]], $pop[[L5]]{{$}}
; CHECK-NEXT: tee_local $push[[L3:.+]]=, $[[R0]]=, $pop[[L4]]{{$}} ; CHECK-NEXT: tee_local $push[[L3:.+]]=, $[[R0]]=, $pop[[L4]]{{$}}
; CHECK-NEXT: i32.ne $push[[L2:.+]]=, $0, $pop[[L3]]{{$}} ; CHECK-NEXT: i32.ne $push[[L2:.+]]=, $0, $pop[[L3]]{{$}}
; NOREGS-LABEL: stackify_indvar:
; NOREGS: i32.const 1{{$}}
; NOREGS-NEXT: i32.add
; NOREGS-NEXT: tee_local 2{{$}}
; NOREGS-NEXT: i32.ne
define void @stackify_indvar(i32 %tmp, i32* %v) #0 { define void @stackify_indvar(i32 %tmp, i32* %v) #0 {
bb: bb:
br label %bb3 br label %bb3
bb3: ; preds = %bb3, %bb2 bb3: ; preds = %bb3, %bb2
%tmp4 = phi i32 [ %tmp7, %bb3 ], [ 0, %bb ] %tmp4 = phi i32 [ %tmp7, %bb3 ], [ 0, %bb ]
%tmp5 = load volatile i32, i32* %v, align 4 %tmp5 = load volatile i32, i32* %v, align 4
%tmp6 = add nsw i32 %tmp5, %tmp4 %tmp6 = add nsw i32 %tmp5, %tmp4
store volatile i32 %tmp6, i32* %v, align 4 store volatile i32 %tmp6, i32* %v, align 4
%tmp7 = add nuw nsw i32 %tmp4, 1 %tmp7 = add nuw nsw i32 %tmp4, 1
%tmp8 = icmp eq i32 %tmp7, %tmp %tmp8 = icmp eq i32 %tmp7, %tmp
br i1 %tmp8, label %bb10, label %bb3 br i1 %tmp8, label %bb10, label %bb3
bb10: ; preds = %bb9, %bb bb10: ; preds = %bb9, %bb
ret void ret void
} }
; Don't stackify a call past a __stack_pointer store. ; Don't stackify a call past a __stack_pointer store.
; CHECK-LABEL: stackpointer_dependency: ; CHECK-LABEL: stackpointer_dependency:
; CHECK: call {{.+}}, stackpointer_callee@FUNCTION, ; CHECK: call {{.+}}, stackpointer_callee@FUNCTION,
; CHECK-NEXT: set_global __stack_pointer@GLOBAL, ; CHECK-NEXT: set_global __stack_pointer@GLOBAL,
; NOREGS-LABEL: stackpointer_dependency:
; NOREGS: call stackpointer_callee@FUNCTION
; NOREGS: set_global __stack_pointer
declare i32 @stackpointer_callee(i8* readnone, i8* readnone) declare i32 @stackpointer_callee(i8* readnone, i8* readnone)
declare i8* @llvm.frameaddress(i32) declare i8* @llvm.frameaddress(i32)
define i32 @stackpointer_dependency(i8* readnone) { define i32 @stackpointer_dependency(i8* readnone) {
%2 = tail call i8* @llvm.frameaddress(i32 0) %2 = tail call i8* @llvm.frameaddress(i32 0)
%3 = tail call i32 @stackpointer_callee(i8* %0, i8* %2) %3 = tail call i32 @stackpointer_callee(i8* %0, i8* %2)
ret i32 %3 ret i32 %3
} }
; Stackify a call_indirect with respect to its ordering ; Stackify a call_indirect with respect to its ordering
; CHECK-LABEL: call_indirect_stackify: ; CHECK-LABEL: call_indirect_stackify:
; CHECK: i32.load $push[[L4:.+]]=, 0($0) ; CHECK: i32.load $push[[L4:.+]]=, 0($0)
; CHECK-NEXT: tee_local $push[[L3:.+]]=, $0=, $pop[[L4]] ; CHECK-NEXT: tee_local $push[[L3:.+]]=, $0=, $pop[[L4]]
; CHECK-NEXT: i32.load $push[[L0:.+]]=, 0($0) ; CHECK-NEXT: i32.load $push[[L0:.+]]=, 0($0)
; CHECK-NEXT: i32.load $push[[L1:.+]]=, 0($pop[[L0]]) ; CHECK-NEXT: i32.load $push[[L1:.+]]=, 0($pop[[L0]])
; CHECK-NEXT: i32.call_indirect $push{{.+}}=, $pop[[L3]], $1, $pop[[L1]] ; CHECK-NEXT: i32.call_indirect $push{{.+}}=, $pop[[L3]], $1, $pop[[L1]]
; NOREGS-LABEL: call_indirect_stackify:
; NOREGS: i32.load 0
; NOREGS-NEXT: tee_local 0
; NOREGS: i32.load 0
; NOREGS-NEXT: i32.load 0
; NOREGS-NEXT: i32.call_indirect
%class.call_indirect = type { i32 (...)** } %class.call_indirect = type { i32 (...)** }
define i32 @call_indirect_stackify(%class.call_indirect** %objptr, i32 %arg) { define i32 @call_indirect_stackify(%class.call_indirect** %objptr, i32 %arg) {
%obj = load %class.call_indirect*, %class.call_indirect** %objptr %obj = load %class.call_indirect*, %class.call_indirect** %objptr
%addr = bitcast %class.call_indirect* %obj to i32(%class.call_indirect*, i32)*** %addr = bitcast %class.call_indirect* %obj to i32(%class.call_indirect*, i32)***
%vtable = load i32(%class.call_indirect*, i32)**, i32(%class.call_indirect*, i32)*** %addr %vtable = load i32(%class.call_indirect*, i32)**, i32(%class.call_indirect*, i32)*** %addr
%vfn = getelementptr inbounds i32(%class.call_indirect*, i32)*, i32(%class.call_indirect*, i32)** %vtable, i32 0 %vfn = getelementptr inbounds i32(%class.call_indirect*, i32)*, i32(%class.call_indirect*, i32)** %vtable, i32 0
%f = load i32(%class.call_indirect*, i32)*, i32(%class.call_indirect*, i32)** %vfn %f = load i32(%class.call_indirect*, i32)*, i32(%class.call_indirect*, i32)** %vfn
%ret = call i32 %f(%class.call_indirect* %obj, i32 %arg) %ret = call i32 %f(%class.call_indirect* %obj, i32 %arg)
ret i32 %ret ret i32 %ret
} }
!llvm.module.flags = !{!0} !llvm.module.flags = !{!0}
!llvm.dbg.cu = !{!1} !llvm.dbg.cu = !{!1}
!0 = !{i32 2, !"Debug Info Version", i32 3} !0 = !{i32 2, !"Debug Info Version", i32 3}
!1 = distinct !DICompileUnit(language: DW_LANG_C99, file: !2, producer: "clang version 3.9.0 (trunk 266005) (llvm/trunk 266105)", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: !3) !1 = distinct !DICompileUnit(language: DW_LANG_C99, file: !2, producer: "clang version 3.9.0 (trunk 266005) (llvm/trunk 266105)", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: !3)
!2 = !DIFile(filename: "test.c", directory: "/") !2 = !DIFile(filename: "test.c", directory: "/")
!3 = !{} !3 = !{}
!5 = distinct !DISubprogram(name: "test", scope: !2, file: !2, line: 10, type: !6, isLocal: false, isDefinition: true, scopeLine: 11, flags: DIFlagPrototyped, isOptimized: true, unit: !1, retainedNodes: !3) !5 = distinct !DISubprogram(name: "test", scope: !2, file: !2, line: 10, type: !6, isLocal: false, isDefinition: true, scopeLine: 11, flags: DIFlagPrototyped, isOptimized: true, unit: !1, retainedNodes: !3)
!6 = !DISubroutineType(types: !3) !6 = !DISubroutineType(types: !3)
!7 = !DILocalVariable(name: "nzcnt", scope: !5, file: !2, line: 15, type: !8) !7 = !DILocalVariable(name: "nzcnt", scope: !5, file: !2, line: 15, type: !8)
!8 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed) !8 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
!9 = !DIExpression() !9 = !DIExpression()
!10 = !DILocation(line: 15, column: 6, scope: !5) !10 = !DILocation(line: 15, column: 6, scope: !5)

test/CodeGen/WebAssembly/return-int32.ll

; RUN: llc < %s -asm-verbose=false | FileCheck %s ; RUN: llc < %s -asm-verbose=false -wasm-keep-registers | FileCheck %s
; RUN: llc < %s -asm-verbose=false -fast-isel -fast-isel-abort=1 | FileCheck %s ; RUN: llc < %s -asm-verbose=false -wasm-keep-registers -fast-isel -fast-isel-abort=1 | FileCheck %s
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
; CHECK-LABEL: return_i32: ; CHECK-LABEL: return_i32:
; CHECK-NEXT: .param i32{{$}} ; CHECK-NEXT: .param i32{{$}}
; CHECK-NEXT: .result i32{{$}} ; CHECK-NEXT: .result i32{{$}}
; CHECK-NEXT: get_local $push0=, 0 ; CHECK-NEXT: get_local $push0=, 0
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; CHECK-NEXT: i32.const $push{{[^,]+}}=, 3{{$}} ; CHECK-NEXT: i32.const $push{{[^,]+}}=, 3{{$}}
; CHECK-NEXT: end_function{{$}} ; CHECK-NEXT: end_function{{$}}
define i32 @return_i32_twice(i32 %a) { define i32 @return_i32_twice(i32 %a) {
%b = icmp ne i32 %a, 0 %b = icmp ne i32 %a, 0
br i1 %b, label %true, label %false br i1 %b, label %true, label %false
true: true:
store i32 0, i32* null store i32 0, i32* null
ret i32 1 ret i32 1
false: false:
store i32 2, i32* null store i32 2, i32* null
ret i32 3 ret i32 3
} }

test/CodeGen/WebAssembly/returned.ll

; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals | FileCheck %s ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers | FileCheck %s
; Test that the "returned" attribute is optimized effectively. ; Test that the "returned" attribute is optimized effectively.
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
; CHECK-LABEL: _Z3foov: ; CHECK-LABEL: _Z3foov:
; CHECK-NEXT: .result i32{{$}} ; CHECK-NEXT: .result i32{{$}}
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test/CodeGen/WebAssembly/select.ll

; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals | FileCheck %s ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers | FileCheck %s
; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -fast-isel -fast-isel-abort=1 | FileCheck %s ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -fast-isel -fast-isel-abort=1 | FileCheck %s
; Test that wasm select instruction is selected from LLVM select instruction. ; Test that wasm select instruction is selected from LLVM select instruction.
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
; CHECK-LABEL: select_i32_bool: ; CHECK-LABEL: select_i32_bool:
; CHECK-NEXT: .param i32, i32, i32{{$}} ; CHECK-NEXT: .param i32, i32, i32{{$}}
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test/CodeGen/WebAssembly/signext-arg.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -asm-verbose=false -disable-wasm-explicit-locals | FileCheck %s ; RUN: llc < %s -asm-verbose=false -wasm-disable-explicit-locals -wasm-keep-registers | FileCheck %s
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
declare i32 @get_int(i16 %arg) declare i32 @get_int(i16 %arg)
define i32 @func_1(i16 %arg1 , i32 %arg2) #0 { define i32 @func_1(i16 %arg1 , i32 %arg2) #0 {
; CHECK-LABEL: func_1: ; CHECK-LABEL: func_1:
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test/CodeGen/WebAssembly/signext-inreg.ll

; RUN: llc < %s -mattr=+sign-ext -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals | FileCheck %s ; RUN: llc < %s -mattr=+sign-ext -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers | FileCheck %s
; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals | FileCheck %s --check-prefix=NOSIGNEXT ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers | FileCheck %s --check-prefix=NOSIGNEXT
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
; CHECK-LABEL: i32_extend8_s: ; CHECK-LABEL: i32_extend8_s:
; CHECK-NEXT: .param i32{{$}} ; CHECK-NEXT: .param i32{{$}}
; CHECK-NEXT: .result i32{{$}} ; CHECK-NEXT: .result i32{{$}}
; CHECK-NEXT: i32.extend8_s $push[[NUM:[0-9]+]]=, $0{{$}} ; CHECK-NEXT: i32.extend8_s $push[[NUM:[0-9]+]]=, $0{{$}}
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test/CodeGen/WebAssembly/signext-zeroext.ll

; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals | FileCheck %s ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers | FileCheck %s
; Test zeroext and signext ABI keywords ; Test zeroext and signext ABI keywords
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
; CHECK-LABEL: z2s_func: ; CHECK-LABEL: z2s_func:
; CHECK-NEXT: .param i32{{$}} ; CHECK-NEXT: .param i32{{$}}
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test/CodeGen/WebAssembly/simd-arith.ll

; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -wasm-enable-unimplemented-simd -mattr=+simd128 | FileCheck %s --check-prefixes CHECK,SIMD128 ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -wasm-enable-unimplemented-simd -mattr=+simd128 | FileCheck %s --check-prefixes CHECK,SIMD128
; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -wasm-enable-unimplemented-simd -mattr=+simd128 -fast-isel | FileCheck %s --check-prefixes CHECK,SIMD128 ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -wasm-enable-unimplemented-simd -mattr=+simd128 -fast-isel | FileCheck %s --check-prefixes CHECK,SIMD128
; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -mattr=+simd128 | FileCheck %s --check-prefixes CHECK,SIMD128-VM ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128 | FileCheck %s --check-prefixes CHECK,SIMD128-VM
; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -mattr=+simd128 -fast-isel | FileCheck %s --check-prefixes CHECK,SIMD128-VM ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128 -fast-isel | FileCheck %s --check-prefixes CHECK,SIMD128-VM
; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -mattr=-simd128 | FileCheck %s --check-prefixes CHECK,NO-SIMD128 ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=-simd128 | FileCheck %s --check-prefixes CHECK,NO-SIMD128
; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -mattr=-simd128 -fast-isel | FileCheck %s --check-prefixes CHECK,NO-SIMD128 ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=-simd128 -fast-isel | FileCheck %s --check-prefixes CHECK,NO-SIMD128
; Test that basic SIMD128 arithmetic operations assemble as expected. ; Test that basic SIMD128 arithmetic operations assemble as expected.
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
; ============================================================================== ; ==============================================================================
; 16 x i8 ; 16 x i8
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test/CodeGen/WebAssembly/stack-alignment.ll

; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt | FileCheck %s ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-keep-registers | FileCheck %s
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
declare void @somefunc(i32*) declare void @somefunc(i32*)
; CHECK-LABEL: underalign: ; CHECK-LABEL: underalign:
; CHECK: get_global $push[[L1:.+]]=, __stack_pointer@GLOBAL{{$}} ; CHECK: get_global $push[[L1:.+]]=, __stack_pointer@GLOBAL{{$}}
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test/CodeGen/WebAssembly/store-trunc-atomic.ll

; RUN: llc < %s -mattr=+atomics,+sign-ext -asm-verbose=false -disable-wasm-explicit-locals | FileCheck %s ; RUN: llc < %s -mattr=+atomics,+sign-ext -asm-verbose=false -wasm-disable-explicit-locals -wasm-keep-registers | FileCheck %s
; Test that truncating stores are assembled properly. ; Test that truncating stores are assembled properly.
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
; CHECK-LABEL: trunc_i8_i32: ; CHECK-LABEL: trunc_i8_i32:
; CHECK: i32.atomic.store8 0($0), $1{{$}} ; CHECK: i32.atomic.store8 0($0), $1{{$}}
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test/CodeGen/WebAssembly/store-trunc.ll

; RUN: llc < %s -asm-verbose=false -disable-wasm-explicit-locals | FileCheck %s ; RUN: llc < %s -asm-verbose=false -wasm-disable-explicit-locals -wasm-keep-registers | FileCheck %s
; Test that truncating stores are assembled properly. ; Test that truncating stores are assembled properly.
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
; CHECK-LABEL: trunc_i8_i32: ; CHECK-LABEL: trunc_i8_i32:
; CHECK: i32.store8 0($0), $1{{$}} ; CHECK: i32.store8 0($0), $1{{$}}
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test/CodeGen/WebAssembly/store.ll

; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt | FileCheck %s ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-keep-registers | FileCheck %s
; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -fast-isel -fast-isel-abort=1 | FileCheck %s ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-keep-registers -fast-isel -fast-isel-abort=1 | FileCheck %s
; Test that basic stores are assembled properly. ; Test that basic stores are assembled properly.
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
; CHECK-LABEL: sti32: ; CHECK-LABEL: sti32:
; CHECK-NEXT: .param i32, i32{{$}} ; CHECK-NEXT: .param i32, i32{{$}}
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test/CodeGen/WebAssembly/switch.ll

; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-block-placement -verify-machineinstrs | FileCheck %s ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -disable-block-placement -verify-machineinstrs | FileCheck %s
; Test switch instructions. Block placement is disabled because it reorders ; Test switch instructions. Block placement is disabled because it reorders
; the blocks in a way that isn't interesting here. ; the blocks in a way that isn't interesting here.
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
declare void @foo0() declare void @foo0()
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test/CodeGen/WebAssembly/tls.ll

; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -thread-model=single | FileCheck --check-prefix=SINGLE %s ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -thread-model=single | FileCheck --check-prefix=SINGLE %s
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
; SINGLE-LABEL: address_of_tls: ; SINGLE-LABEL: address_of_tls:
define i32 @address_of_tls() { define i32 @address_of_tls() {
; SINGLE: i32.const $push0=, tls ; SINGLE: i32.const $push0=, tls
; SINGLE-NEXT: return $pop0 ; SINGLE-NEXT: return $pop0
ret i32 ptrtoint(i32* @tls to i32) ret i32 ptrtoint(i32* @tls to i32)
} }
; SINGLE: .type tls,@object ; SINGLE: .type tls,@object
; SINGLE-NEXT: .section .bss.tls,"",@ ; SINGLE-NEXT: .section .bss.tls,"",@
; SINGLE-NEXT: .p2align 2 ; SINGLE-NEXT: .p2align 2
; SINGLE-NEXT: tls: ; SINGLE-NEXT: tls:
; SINGLE-NEXT: .int32 0 ; SINGLE-NEXT: .int32 0
@tls = internal thread_local global i32 0 @tls = internal thread_local global i32 0

test/CodeGen/WebAssembly/umulo-i64.ll

; RUN: llc < %s -asm-verbose=false -disable-wasm-explicit-locals | FileCheck %s ; RUN: llc < %s -asm-verbose=false -wasm-disable-explicit-locals -wasm-keep-registers | FileCheck %s
; Test that UMULO works correctly on 64-bit operands. ; Test that UMULO works correctly on 64-bit operands.
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
; CHECK-LABEL: _ZN4core3num21_$LT$impl$u20$u64$GT$15overflowing_mul17h07be88b4cbac028fE: ; CHECK-LABEL: _ZN4core3num21_$LT$impl$u20$u64$GT$15overflowing_mul17h07be88b4cbac028fE:
; CHECK: __multi3 ; CHECK: __multi3
; Function Attrs: inlinehint ; Function Attrs: inlinehint
define void @"_ZN4core3num21_$LT$impl$u20$u64$GT$15overflowing_mul17h07be88b4cbac028fE"(i64, i64) unnamed_addr #0 { define void @"_ZN4core3num21_$LT$impl$u20$u64$GT$15overflowing_mul17h07be88b4cbac028fE"(i64, i64) unnamed_addr #0 {
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test/CodeGen/WebAssembly/unsupported-function-bitcasts.ll

; RUN: llc < %s -asm-verbose=false | FileCheck %s ; RUN: llc < %s -asm-verbose=false -wasm-keep-registers | FileCheck %s
; Test that function pointer casts that require conversions of arguments or ; Test that function pointer casts that require conversions of arguments or
; return types are converted to unreachable. ; return types are converted to unreachable.
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
declare i32 @has_i64_arg(i64) declare i32 @has_i64_arg(i64)
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test/CodeGen/WebAssembly/unused-argument.ll

; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals | FileCheck %s ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers | FileCheck %s
; Make sure that argument offsets are correct even if some arguments are unused. ; Make sure that argument offsets are correct even if some arguments are unused.
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
; CHECK-LABEL: unused_first: ; CHECK-LABEL: unused_first:
; CHECK-NEXT: .param i32, i32{{$}} ; CHECK-NEXT: .param i32, i32{{$}}
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test/CodeGen/WebAssembly/userstack.ll

; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt | FileCheck %s ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-keep-registers | FileCheck %s
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
declare void @ext_func(i64* %ptr) declare void @ext_func(i64* %ptr)
declare void @ext_func_i32(i32* %ptr) declare void @ext_func_i32(i32* %ptr)
; CHECK-LABEL: alloca32: ; CHECK-LABEL: alloca32:
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test/CodeGen/WebAssembly/varargs.ll

; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -verify-machineinstrs | FileCheck %s ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -verify-machineinstrs | FileCheck %s
; Test varargs constructs. ; Test varargs constructs.
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
; Test va_start. ; Test va_start.
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test/CodeGen/WebAssembly/vtable.ll

; RUN: llc < %s -asm-verbose=false -disable-wasm-explicit-locals | FileCheck %s --check-prefix=TYPEINFONAME ; RUN: llc < %s -asm-verbose=false -wasm-disable-explicit-locals -wasm-keep-registers | FileCheck %s --check-prefix=TYPEINFONAME
; RUN: llc < %s -asm-verbose=false -disable-wasm-explicit-locals | FileCheck %s --check-prefix=VTABLE ; RUN: llc < %s -asm-verbose=false -wasm-disable-explicit-locals -wasm-keep-registers | FileCheck %s --check-prefix=VTABLE
; RUN: llc < %s -asm-verbose=false -disable-wasm-explicit-locals | FileCheck %s --check-prefix=TYPEINFO ; RUN: llc < %s -asm-verbose=false -wasm-disable-explicit-locals -wasm-keep-registers | FileCheck %s --check-prefix=TYPEINFO
; Test that simple vtables assemble as expected. ; Test that simple vtables assemble as expected.
; ;
; The class hierarchy is: ; The class hierarchy is:
; struct A; ; struct A;
; struct B : public A; ; struct B : public A;
; struct C : public A; ; struct C : public A;
; struct D : public B; ; struct D : public B;
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test/MC/Disassembler/WebAssembly/wasm.txt

# RUN: llvm-mc --disassemble %s -triple=wasm32-unknown-unknown | FileCheck %s # RUN: llvm-mc --disassemble %s -triple=wasm32-unknown-unknown | FileCheck %s
# CHECK: .text # CHECK: .text
# CHECK: nop # CHECK: nop
0x01 0x01
# CHECK: i32.add # CHECK: i32.add
0x6a 0x6a
# CHECK: i64.const -1 # CHECK: i64.const -1
0x42 0x7F 0x42 0x7F
# CHECK: i64.load32_u 16, :p2align=1 # CHECK: i64.load32_u 16:p2align=1
# FIXME: fix p2align output in WebAssemblyInstPrinter
0x35 0x01 0x10 0x35 0x01 0x10
# CHECK: block # CHECK: block
# 3 # 3
# FIXME: WebAssemblyInstPrinter does not currently print block number. # FIXME: WebAssemblyInstPrinter does not currently print block number.
0x02 0x03 0x02 0x03
# CHECK: call_indirect # CHECK: call_indirect
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test/MC/WebAssembly/basic-assembly.s

# RUN: llvm-mc -triple=wasm32-unknown-unknown < %s | FileCheck %s # RUN: llvm-mc -triple=wasm32-unknown-unknown < %s | FileCheck %s
.text .text
.type test0,@function .type test0,@function
test0: test0:
# Test all types: # Test all types:
.param i32, i64 .param i32, i64
.local f32, f64 #, i8x16, i16x8, i32x4, f32x4 .local f32, f64 #, i8x16, i16x8, i32x4, f32x4
# Explicit getlocal/setlocal: # Explicit getlocal/setlocal:
get_local $push0=, 2 get_local 2
set_local 2, $pop0= set_local 2
# Implicit locals & immediates: # Immediates:
i32.const $0=, -1 i32.const -1
f64.const $3=, 0x1.999999999999ap1 f64.const 0x1.999999999999ap1
# Indirect addressing: # Indirect addressing:
get_local $push1=, 0 get_local 0
f64.store 0($pop1), $3 f64.store 0
# Loops, conditionals, binary ops, calls etc: # Loops, conditionals, binary ops, calls etc:
block block
i32.const $push2=, 1 i32.const 1
get_local $push7=, 0 get_local 0
i32.ge_s $push0=, $pop2, $pop7 i32.ge_s
br_if 0, $pop0 # 0: down to label0 br_if 0 # 0: down to label0
.LBB0_1: .LBB0_1:
loop # label1: loop # label1:
call $drop=, something1@FUNCTION call something1@FUNCTION
i64.const $push10=, 1234 i64.const 1234
i32.call $push8=, something2@FUNCTION, $pop10 i32.call something2@FUNCTION
i32.const $push11=, 0 i32.const 0
call_indirect $pop11 call_indirect
i32.const $push5=, 1 i32.const 1
i32.add $push4=, $pop8, $pop5 i32.add
tee_local $push3=, 0, $pop4 tee_local 0
get_local $push9=, 0 get_local 0
i32.lt_s $push1=, $pop3, $pop9 i32.lt_s
br_if 0, $pop1 # 0: up to label1 br_if 0 # 0: up to label1
.LBB0_2: .LBB0_2:
end_loop end_loop
end_block # label0: end_block # label0:
end_function end_function
# CHECK: .text # CHECK: .text
# CHECK-LABEL: test0: # CHECK-LABEL: test0:
# CHECK-NEXT: .param i32, i64 # CHECK-NEXT: .param i32, i64
# CHECK-NEXT: .local f32, f64 # CHECK-NEXT: .local f32, f64
# CHECK-NEXT: get_local $push0=, 2 # CHECK-NEXT: get_local 2
# CHECK-NEXT: set_local 2, $pop0 # CHECK-NEXT: set_local 2
# CHECK-NEXT: i32.const $0=, -1 # CHECK-NEXT: i32.const -1
# CHECK-NEXT: f64.const $3=, 0x1.999999999999ap1 # CHECK-NEXT: f64.const 0x1.999999999999ap1
# CHECK-NEXT: get_local $push1=, 0 # CHECK-NEXT: get_local 0
# CHECK-NEXT: f64.store 0($pop1):p2align=0, $3 # CHECK-NEXT: f64.store 0:p2align=0
# CHECK-NEXT: block # CHECK-NEXT: block
# CHECK-NEXT: i32.const $push2=, 1 # CHECK-NEXT: i32.const 1
# CHECK-NEXT: get_local $push7=, 0 # CHECK-NEXT: get_local 0
# CHECK-NEXT: i32.ge_s $push0=, $pop2, $pop7 # CHECK-NEXT: i32.ge_s
# CHECK-NEXT: br_if 0, $pop0 # 0: down to label0 # CHECK-NEXT: br_if 0 # 0: down to label0
# CHECK-NEXT: .LBB0_1: # CHECK-NEXT: .LBB0_1:
# CHECK-NEXT: loop # label1: # CHECK-NEXT: loop # label1:
# CHECK-NEXT: call something1@FUNCTION # CHECK-NEXT: call something1@FUNCTION
# CHECK-NEXT: i64.const $push10=, 1234 # CHECK-NEXT: i64.const 1234
# CHECK-NEXT: i32.call $push8=, something2@FUNCTION # CHECK-NEXT: i32.call something2@FUNCTION
# CHECK-NEXT: i32.const $push11=, 0 # CHECK-NEXT: i32.const 0
# CHECK-NEXT: call_indirect # CHECK-NEXT: call_indirect
# CHECK-NEXT: i32.const $push5=, 1 # CHECK-NEXT: i32.const 1
# CHECK-NEXT: i32.add $push4=, $pop8, $pop5 # CHECK-NEXT: i32.add
# CHECK-NEXT: tee_local $push3=, 0, $pop4 # CHECK-NEXT: tee_local 0
# CHECK-NEXT: get_local $push9=, 0 # CHECK-NEXT: get_local 0
# CHECK-NEXT: i32.lt_s $push1=, $pop3, $pop9 # CHECK-NEXT: i32.lt_s
# CHECK-NEXT: br_if 0, $pop1 # 0: up to label1 # CHECK-NEXT: br_if 0 # 0: up to label1
# CHECK-NEXT: .LBB0_2: # CHECK-NEXT: .LBB0_2:
# CHECK-NEXT: end_loop # CHECK-NEXT: end_loop
# CHECK-NEXT: end_block # label0: # CHECK-NEXT: end_block # label0:
# CHECK-NEXT: end_function # CHECK-NEXT: end_function

test/MC/WebAssembly/reloc-code.ll

; RUN: llc -filetype=obj %s -o - | llvm-readobj -r -expand-relocs | FileCheck %s ; RUN: llc -filetype=obj -wasm-keep-registers %s -o - | llvm-readobj -r -expand-relocs | FileCheck %s
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
; Pointers to functions of two different types ; Pointers to functions of two different types
@a = global i64 ()* inttoptr (i64 5 to i64 ()*), align 8 @a = global i64 ()* inttoptr (i64 5 to i64 ()*), align 8
@b = global i32 ()* inttoptr (i32 7 to i32 ()*), align 8 @b = global i32 ()* inttoptr (i32 7 to i32 ()*), align 8
; External functions ; External functions
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test/MC/WebAssembly/weak-alias.ll

; RUN: llc -filetype=obj %s -o %t.o ; RUN: llc -filetype=obj -wasm-keep-registers %s -o %t.o
; RUN: obj2yaml %t.o | FileCheck %s ; RUN: obj2yaml %t.o | FileCheck %s
; RUN: llvm-objdump -t %t.o | FileCheck --check-prefix=CHECK-SYMS %s ; RUN: llvm-objdump -t %t.o | FileCheck --check-prefix=CHECK-SYMS %s
target triple = "wasm32-unknown-unknown" target triple = "wasm32-unknown-unknown"
; 'foo_alias()' is weak alias of function 'foo()' ; 'foo_alias()' is weak alias of function 'foo()'
; 'bar_alias' is weak alias of global variable 'bar' ; 'bar_alias' is weak alias of global variable 'bar'
; Generates two exports of the same function, one of them weak ; Generates two exports of the same function, one of them weak
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define hidden i32 @call_alias_ptr() #0 { define hidden i32 @call_alias_ptr() #0 {
entry: entry:
%0 = load i32 ()*, i32 ()** @alias_address, align 8 %0 = load i32 ()*, i32 ()** @alias_address, align 8
%call = call i32 %0() %call = call i32 %0()
ret i32 %call ret i32 %call
} }
; CHECK: - Type: TYPE ; CHECK: - Type: TYPE
; CHECK-NEXT: Signatures: ; CHECK-NEXT: Signatures:
; CHECK-NEXT: - Index: 0 ; CHECK-NEXT: - Index: 0
; CHECK-NEXT: ReturnType: I32 ; CHECK-NEXT: ReturnType: I32
; CHECK-NEXT: ParamTypes: ; CHECK-NEXT: ParamTypes:
; CHECK-NEXT: - Type: IMPORT ; CHECK-NEXT: - Type: IMPORT
; CHECK-NEXT: Imports: ; CHECK-NEXT: Imports:
; CHECK-NEXT: - Module: env ; CHECK-NEXT: - Module: env
; CHECK-NEXT: Field: __linear_memory ; CHECK-NEXT: Field: __linear_memory
; CHECK-NEXT: Kind: MEMORY ; CHECK-NEXT: Kind: MEMORY
; CHECK-NEXT: Memory: ; CHECK-NEXT: Memory:
; CHECK-NEXT: Initial: 0x00000001 ; CHECK-NEXT: Initial: 0x00000001
; CHECK-NEXT: - Module: env ; CHECK-NEXT: - Module: env
; CHECK-NEXT: Field: __indirect_function_table ; CHECK-NEXT: Field: __indirect_function_table
; CHECK-NEXT: Kind: TABLE ; CHECK-NEXT: Kind: TABLE
; CHECK-NEXT: Table: ; CHECK-NEXT: Table:
; CHECK-NEXT: ElemType: ANYFUNC ; CHECK-NEXT: ElemType: ANYFUNC
; CHECK-NEXT: Limits: ; CHECK-NEXT: Limits:
; CHECK-NEXT: Initial: 0x00000001 ; CHECK-NEXT: Initial: 0x00000001
; CHECK-NEXT: - Type: FUNCTION ; CHECK-NEXT: - Type: FUNCTION
; CHECK-NEXT: FunctionTypes: [ 0, 0, 0, 0, 0 ] ; CHECK-NEXT: FunctionTypes: [ 0, 0, 0, 0, 0 ]
; CHECK-NEXT: - Type: ELEM ; CHECK-NEXT: - Type: ELEM
; CHECK-NEXT: Segments: ; CHECK-NEXT: Segments:
; CHECK-NEXT: - Offset: ; CHECK-NEXT: - Offset:
; CHECK-NEXT: Opcode: I32_CONST ; CHECK-NEXT: Opcode: I32_CONST
; CHECK-NEXT: Value: 1 ; CHECK-NEXT: Value: 1
; CHECK-NEXT: Functions: [ 0 ] ; CHECK-NEXT: Functions: [ 0 ]
; CHECK-NEXT: - Type: CODE ; CHECK-NEXT: - Type: CODE
; CHECK-NEXT: Relocations: ; CHECK-NEXT: Relocations:
; CHECK-NEXT: - Type: R_WEBASSEMBLY_FUNCTION_INDEX_LEB ; CHECK-NEXT: - Type: R_WEBASSEMBLY_FUNCTION_INDEX_LEB
; CHECK-NEXT: Index: 0 ; CHECK-NEXT: Index: 0
; CHECK-NEXT: Offset: 0x00000009 ; CHECK-NEXT: Offset: 0x00000009
; CHECK-NEXT: - Type: R_WEBASSEMBLY_FUNCTION_INDEX_LEB ; CHECK-NEXT: - Type: R_WEBASSEMBLY_FUNCTION_INDEX_LEB
; CHECK-NEXT: Index: 3 ; CHECK-NEXT: Index: 3
; CHECK-NEXT: Offset: 0x00000012 ; CHECK-NEXT: Offset: 0x00000012
; CHECK-NEXT: - Type: R_WEBASSEMBLY_MEMORY_ADDR_LEB ; CHECK-NEXT: - Type: R_WEBASSEMBLY_MEMORY_ADDR_LEB
; CHECK-NEXT: Index: 5 ; CHECK-NEXT: Index: 5
; CHECK-NEXT: Offset: 0x0000001E ; CHECK-NEXT: Offset: 0x0000001E
; CHECK-NEXT: - Type: R_WEBASSEMBLY_TYPE_INDEX_LEB ; CHECK-NEXT: - Type: R_WEBASSEMBLY_TYPE_INDEX_LEB
; CHECK-NEXT: Index: 0 ; CHECK-NEXT: Index: 0
; CHECK-NEXT: Offset: 0x00000024 ; CHECK-NEXT: Offset: 0x00000024
; CHECK-NEXT: - Type: R_WEBASSEMBLY_MEMORY_ADDR_LEB ; CHECK-NEXT: - Type: R_WEBASSEMBLY_MEMORY_ADDR_LEB
; CHECK-NEXT: Index: 7 ; CHECK-NEXT: Index: 7
; CHECK-NEXT: Offset: 0x00000031 ; CHECK-NEXT: Offset: 0x00000031
; CHECK-NEXT: - Type: R_WEBASSEMBLY_TYPE_INDEX_LEB ; CHECK-NEXT: - Type: R_WEBASSEMBLY_TYPE_INDEX_LEB
; CHECK-NEXT: Index: 0 ; CHECK-NEXT: Index: 0
; CHECK-NEXT: Offset: 0x00000037 ; CHECK-NEXT: Offset: 0x00000037
; CHECK-NEXT: Functions: ; CHECK-NEXT: Functions:
; CHECK-NEXT: - Index: 0 ; CHECK-NEXT: - Index: 0
; CHECK-NEXT: Locals: ; CHECK-NEXT: Locals:
; CHECK-NEXT: Body: 41000B ; CHECK-NEXT: Body: 41000B
; CHECK-NEXT: - Index: 1 ; CHECK-NEXT: - Index: 1
; CHECK-NEXT: Locals: ; CHECK-NEXT: Locals:
; CHECK-NEXT: Body: 1080808080000B ; CHECK-NEXT: Body: 1080808080000B
; CHECK-NEXT: - Index: 2 ; CHECK-NEXT: - Index: 2
; CHECK-NEXT: Locals: ; CHECK-NEXT: Locals:
; CHECK-NEXT: Body: 1080808080000B ; CHECK-NEXT: Body: 1080808080000B
; CHECK-NEXT: - Index: 3 ; CHECK-NEXT: - Index: 3
; CHECK-NEXT: Locals: ; CHECK-NEXT: Locals:
; CHECK-NEXT: Body: 410028028880808000118080808000000B ; CHECK-NEXT: Body: 410028028880808000118080808000000B
; CHECK-NEXT: - Index: 4 ; CHECK-NEXT: - Index: 4
; CHECK-NEXT: Locals: ; CHECK-NEXT: Locals:
; CHECK-NEXT: Body: 410028029080808000118080808000000B ; CHECK-NEXT: Body: 410028029080808000118080808000000B
; CHECK-NEXT: - Type: DATA ; CHECK-NEXT: - Type: DATA
; CHECK-NEXT: Relocations: ; CHECK-NEXT: Relocations:
; CHECK-NEXT: - Type: R_WEBASSEMBLY_TABLE_INDEX_I32 ; CHECK-NEXT: - Type: R_WEBASSEMBLY_TABLE_INDEX_I32
; CHECK-NEXT: Index: 0 ; CHECK-NEXT: Index: 0
; CHECK-NEXT: Offset: 0x0000000F ; CHECK-NEXT: Offset: 0x0000000F
; CHECK-NEXT: - Type: R_WEBASSEMBLY_TABLE_INDEX_I32 ; CHECK-NEXT: - Type: R_WEBASSEMBLY_TABLE_INDEX_I32
; CHECK-NEXT: Index: 3 ; CHECK-NEXT: Index: 3
; CHECK-NEXT: Offset: 0x00000018 ; CHECK-NEXT: Offset: 0x00000018
; CHECK-NEXT: Segments: ; CHECK-NEXT: Segments:
; CHECK-NEXT: - SectionOffset: 6 ; CHECK-NEXT: - SectionOffset: 6
; CHECK-NEXT: MemoryIndex: 0 ; CHECK-NEXT: MemoryIndex: 0
; CHECK-NEXT: Offset: ; CHECK-NEXT: Offset:
; CHECK-NEXT: Opcode: I32_CONST ; CHECK-NEXT: Opcode: I32_CONST
; CHECK-NEXT: Value: 0 ; CHECK-NEXT: Value: 0
; CHECK-NEXT: Content: '07000000' ; CHECK-NEXT: Content: '07000000'
; CHECK-NEXT: - SectionOffset: 15 ; CHECK-NEXT: - SectionOffset: 15
; CHECK-NEXT: MemoryIndex: 0 ; CHECK-NEXT: MemoryIndex: 0
; CHECK-NEXT: Offset: ; CHECK-NEXT: Offset:
; CHECK-NEXT: Opcode: I32_CONST ; CHECK-NEXT: Opcode: I32_CONST
; CHECK-NEXT: Value: 8 ; CHECK-NEXT: Value: 8
; CHECK-NEXT: Content: '01000000' ; CHECK-NEXT: Content: '01000000'
; CHECK-NEXT: - SectionOffset: 24 ; CHECK-NEXT: - SectionOffset: 24
; CHECK-NEXT: MemoryIndex: 0 ; CHECK-NEXT: MemoryIndex: 0
; CHECK-NEXT: Offset: ; CHECK-NEXT: Offset:
; CHECK-NEXT: Opcode: I32_CONST ; CHECK-NEXT: Opcode: I32_CONST
; CHECK-NEXT: Value: 16 ; CHECK-NEXT: Value: 16
; CHECK-NEXT: Content: '01000000' ; CHECK-NEXT: Content: '01000000'
; CHECK-NEXT: - Type: CUSTOM ; CHECK-NEXT: - Type: CUSTOM
; CHECK-NEXT: Name: linking ; CHECK-NEXT: Name: linking
; CHECK-NEXT: Version: 1 ; CHECK-NEXT: Version: 1
; CHECK-NEXT: SymbolTable: ; CHECK-NEXT: SymbolTable:
; CHECK-NEXT: - Index: 0 ; CHECK-NEXT: - Index: 0
; CHECK-NEXT: Kind: FUNCTION ; CHECK-NEXT: Kind: FUNCTION
; CHECK-NEXT: Name: foo ; CHECK-NEXT: Name: foo
; CHECK-NEXT: Flags: [ VISIBILITY_HIDDEN ] ; CHECK-NEXT: Flags: [ VISIBILITY_HIDDEN ]
; CHECK-NEXT: Function: 0 ; CHECK-NEXT: Function: 0
; CHECK-NEXT: - Index: 1 ; CHECK-NEXT: - Index: 1
; CHECK-NEXT: Kind: FUNCTION ; CHECK-NEXT: Kind: FUNCTION
; CHECK-NEXT: Name: call_direct ; CHECK-NEXT: Name: call_direct
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; CHECK-NEXT: Segment: 0 ; CHECK-NEXT: Segment: 0
; CHECK-NEXT: Size: 4 ; CHECK-NEXT: Size: 4
; CHECK-NEXT: - Index: 9 ; CHECK-NEXT: - Index: 9
; CHECK-NEXT: Kind: DATA ; CHECK-NEXT: Kind: DATA
; CHECK-NEXT: Name: bar_alias ; CHECK-NEXT: Name: bar_alias
; CHECK-NEXT: Flags: [ BINDING_WEAK, VISIBILITY_HIDDEN ] ; CHECK-NEXT: Flags: [ BINDING_WEAK, VISIBILITY_HIDDEN ]
; CHECK-NEXT: Segment: 0 ; CHECK-NEXT: Segment: 0
; CHECK-NEXT: Size: 4 ; CHECK-NEXT: Size: 4
; CHECK-NEXT: SegmentInfo: ; CHECK-NEXT: SegmentInfo:
; CHECK-NEXT: - Index: 0 ; CHECK-NEXT: - Index: 0
; CHECK-NEXT: Name: .data.bar ; CHECK-NEXT: Name: .data.bar
; CHECK-NEXT: Alignment: 8 ; CHECK-NEXT: Alignment: 8
; CHECK-NEXT: Flags: [ ] ; CHECK-NEXT: Flags: [ ]
; CHECK-NEXT: - Index: 1 ; CHECK-NEXT: - Index: 1
; CHECK-NEXT: Name: .data.direct_address ; CHECK-NEXT: Name: .data.direct_address
; CHECK-NEXT: Alignment: 8 ; CHECK-NEXT: Alignment: 8
; CHECK-NEXT: Flags: [ ] ; CHECK-NEXT: Flags: [ ]
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unittests/MC/Disassembler.cpp

Show First 20 Lines • Show All 95 Lines • ▼ Show 20 LinesTEST(Disassembler, WebAssemblyTest) {
PC += InstSize; PC += InstSize;
BytesP += InstSize; BytesP += InstSize;
NumBytes -= InstSize; NumBytes -= InstSize;
InstSize = LLVMDisasmInstruction(DCR, BytesP, NumBytes, PC, OutString, InstSize = LLVMDisasmInstruction(DCR, BytesP, NumBytes, PC, OutString,
OutStringSize); OutStringSize);
EXPECT_EQ(InstSize, 3U); EXPECT_EQ(InstSize, 3U);
EXPECT_EQ(StringRef(OutString), "\ti64.load32_u\t16, :p2align=1"); EXPECT_EQ(StringRef(OutString), "\ti64.load32_u\t16:p2align=1");
LLVMDisasmDispose(DCR); LLVMDisasmDispose(DCR);
} }