[mips] Handle missing CondCodes

[smaksimovic]

Summary

Add patterns for unhandled CondCode enumerables:
SETEQ, SETGE, SETGT, SETLE, SETLT, SETNE.

Stated at the ISD::CondCode enum declaration:
All of these (except for the 'always folded ops') should be handled for floating point.

Since the introduction of D46854, a simple example

define  double @test(<2 x double>) unnamed_addr {
start:
  %1 = call double @llvm.experimental.vector.reduce.fmin.f64.v2f64(<2 x double> %0)
  ret double %1
}

fails due to
v2i64 = setcc t6, t19, setlt:ch
not being matchable, which previously held a setolt condition code node.

Add patterns which use these nodes, same as corresponding 'ordered' CondCode nodes.
Referring to Ordered means that neither operand is a QNAN we assume it is safe to match ex. SETLT node to the same
instruction as SETOLT.

[smaksimovic]

Add test file.

[atanasyan]

test/CodeGen/Mips/msa/cc_without_nan.ll

15

What do you think about extending this test case to cover more new patterns?

[smaksimovic]

Update test file to cover all of the patterns included in the change.

[smaksimovic]

test/CodeGen/Mips/msa/cc_without_nan.ll

15

Thanks for noticing, I had completely missed that part.
Updated.

[atanasyan]

LGTM

lib/Target/Mips/MipsMSAInstrInfo.td

 def insve_v2i64 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2),
     (v2i64 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>;
 
 class vfsetcc_type<ValueType ResTy, ValueType OpTy, CondCode CC> :
   PatFrag<(ops node:$lhs, node:$rhs),
           (ResTy (vfsetcc (OpTy node:$lhs), (OpTy node:$rhs), CC))>;
 
 // ISD::SETFALSE cannot occur
+def vfseteq_v4f32 : vfsetcc_type<v4i32, v4f32, SETEQ>;
+def vfseteq_v2f64 : vfsetcc_type<v2i64, v2f64, SETEQ>;
+def vfsetge_v4f32 : vfsetcc_type<v4i32, v4f32, SETGE>;
+def vfsetge_v2f64 : vfsetcc_type<v2i64, v2f64, SETGE>;
+def vfsetgt_v4f32 : vfsetcc_type<v4i32, v4f32, SETGT>;
+def vfsetgt_v2f64 : vfsetcc_type<v2i64, v2f64, SETGT>;
+def vfsetle_v4f32 : vfsetcc_type<v4i32, v4f32, SETLE>;
+def vfsetle_v2f64 : vfsetcc_type<v2i64, v2f64, SETLE>;
+def vfsetlt_v4f32 : vfsetcc_type<v4i32, v4f32, SETLT>;
+def vfsetlt_v2f64 : vfsetcc_type<v2i64, v2f64, SETLT>;
+def vfsetne_v4f32 : vfsetcc_type<v4i32, v4f32, SETNE>;
+def vfsetne_v2f64 : vfsetcc_type<v2i64, v2f64, SETNE>;
 def vfsetoeq_v4f32 : vfsetcc_type<v4i32, v4f32, SETOEQ>;
 def vfsetoeq_v2f64 : vfsetcc_type<v2i64, v2f64, SETOEQ>;
 def vfsetoge_v4f32 : vfsetcc_type<v4i32, v4f32, SETOGE>;
 def vfsetoge_v2f64 : vfsetcc_type<v2i64, v2f64, SETOGE>;
 def vfsetogt_v4f32 : vfsetcc_type<v4i32, v4f32, SETOGT>;
 def vfsetogt_v2f64 : vfsetcc_type<v2i64, v2f64, SETOGT>;
 def vfsetole_v4f32 : vfsetcc_type<v4i32, v4f32, SETOLE>;
 def vfsetole_v2f64 : vfsetcc_type<v2i64, v2f64, SETOLE>;
(f32 (EXTRACT_SUBREG
            (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
          sub_lo))>;
 def : MSAPat<
   (f64 (vector_extract v2f64:$ws, i64:$idx)),
   (f64 (EXTRACT_SUBREG
          (SPLAT_D v2f64:$ws,
            (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
          sub_64))>;
+
+def : MSAPat<(vfseteq_v4f32 MSA128WOpnd:$a, MSA128WOpnd:$b),
+             (FCEQ_W MSA128WOpnd:$a, MSA128WOpnd:$b)>;
+def : MSAPat<(vfseteq_v2f64 MSA128DOpnd:$a, MSA128DOpnd:$b),
+             (FCEQ_D MSA128DOpnd:$a, MSA128DOpnd:$b)>;
+def : MSAPat<(vfsetle_v4f32 MSA128WOpnd:$a, MSA128WOpnd:$b),
+             (FCLE_W MSA128WOpnd:$a, MSA128WOpnd:$b)>;
+def : MSAPat<(vfsetle_v2f64 MSA128DOpnd:$a, MSA128DOpnd:$b),
+             (FCLE_D MSA128DOpnd:$a, MSA128DOpnd:$b)>;
+def : MSAPat<(vfsetlt_v4f32 MSA128WOpnd:$a, MSA128WOpnd:$b),
+             (FCLT_W MSA128WOpnd:$a, MSA128WOpnd:$b)>;
+def : MSAPat<(vfsetlt_v2f64 MSA128DOpnd:$a, MSA128DOpnd:$b),
+             (FCLT_D MSA128DOpnd:$a, MSA128DOpnd:$b)>;
+def : MSAPat<(vfsetne_v4f32 MSA128WOpnd:$a, MSA128WOpnd:$b),
+             (FCNE_W MSA128WOpnd:$a, MSA128WOpnd:$b)>;
+def : MSAPat<(vfsetne_v2f64 MSA128DOpnd:$a, MSA128DOpnd:$b),
+             (FCNE_D MSA128DOpnd:$a, MSA128DOpnd:$b)>;

test/CodeGen/Mips/msa/cc_without_nan.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple mips64-unknown-linux -mcpu=mips64r5 -mattr=+msa < %s | FileCheck %s
+
+define  double @test(<2 x double>){
+; CHECK-LABEL: test:
+; CHECK:       # %bb.0: # %start
+; CHECK-NEXT:    ldi.b $w1, 0
+; CHECK-NEXT:    insert.d $w1[0], $4
+; CHECK-NEXT:    insert.d $w1[1], $5
+; CHECK-NEXT:    fill.d $w2, $5
+; CHECK-NEXT:    fclt.d $w0, $w1, $w2
+; CHECK-NEXT:    jr $ra
+; CHECK-NEXT:    bsel.v $w0, $w2, $w1
+start:
+  %1 = call double @llvm.experimental.vector.reduce.fmin.f64.v2f64(<2 x double> %0)
+  ret double %1
+}
+
+declare double @llvm.experimental.vector.reduce.fmin.f64.v2f64(<2 x double>)