[llvm-mca] Propagate fatal llvm-mca errors from library classes to driver.

[mattd]

Summary

This patch introduces error handling to propagate the errors from llvm-mca library classes (or what will become library classes) up to the driver. This patch also introduces an enum to make clearer the intention of the return value for Stage::execute.

This supports PR38101.

[mattd]

Updated:

• RegisterFile::isAvailable no longer fataly fails, instead if an instruction requires more registers than what a register file can hold, a warning is issued and the PRF is increased to hold the number of registers specified by the instruction.
• Unfortunately this requires isAvailable to no longer be const, and that the RegisterMappingTracker to no longer have a const NumPhysRegs field.
• Another option is check the register file lengths per instruction, but outside of isAvailable. As part of some sanity check. However, that will some what duplicate the for-loop in isAvailable.
• I'm going to go through the patch and see if there is any template code I can simplify via using directives, I don't want to increase complexity.

[mattd]

tools/llvm-mca/RegisterFile.h

163 ↗

(On Diff #160181)

I'd like to rename this to getPRFAvailabilityMask or getRegisterFileAvailability. To me, 'isAvailable' implies a boolean, which it is not in this case.

[mattd]

Added Stage::Status type alias to clean up the return value for Stage::execute. The previous iteration of this patch used an Expected<bool>, which I find confusing. This change makes the code more readable.

[andreadb]

In D50561#1196200, @mattd wrote:

Added Stage::Status type alias to clean up the return value for Stage::execute. The previous iteration of this patch used an Expected<bool>, which I find confusing. This change makes the code more readable.

Nice cleanup, thanks!

The code comments related to the Stage::Status should be improved.
In a follow-up patch, you should also improve the code comments in Stage.h and better describe the API.
I found our code comments in Stage.h extremely hard to read. In the end, I suspect that people have to resort at looking at the implementation to fully understand the meaning of "execute(IR)" for a stage.

I think we should do a better job at describing that API.

I have added some comments below.
If you integrate those changes, and share the patch upstream, then I will be happy to accept it.

P.s.: you should reference the llvm bugzilla related to this change, and update it accordingly.

tools/llvm-mca/InstrBuilder.cpp

350–356 ↗

(On Diff #160225)

Not sure why you removed the original code that printed the note.

You should add it back:

WithColor::note() << "instruction: " << ToString << '\n';

Then you should return:

return make_error<StringError>("Don't know how to analyze unsupported instructions.", inconvertibleErrorCode());

tools/llvm-mca/RegisterFile.cpp

280 ↗

(On Diff #160225)

Add const back. (see below)

305–314 ↗

(On Diff #160225)

Here is the idea:

Normalize NumRegs instead:
If NumRegs is bigger than RMT.NumPhysRegs, then silently make NumRegs equal to RMT.NumPhysRegs.

Motivation:
In reality, expression RMT.NumPhysRegs < NumRegs is never expected to be true.
If that check fails, then there is something fundamentally wrong with the scheduling model, or the option passed in input by the user.
In future, we may even decide to drop the driver option to control the size of a register file entirely.

Changing the API to account for a very rare case where things might go wrong is not worth it in my opinion.

I would keep this method "const", I would also add a FIXME comment explaining that the current normalization may hide an inconsistency, but because this is a rare (low priority) situation, we decided that it was not worth it to have it fixed by changing the API. This might be revisited in future.

tools/llvm-mca/RegisterFile.h

46 ↗

(On Diff #160225)

I have been thinking about this. I think it should be reverted to const.
See my comment below for an explanation.

163 ↗

(On Diff #160181)

I think it is fine to return an unsigned. If the mask is zero, then the register files are not available; any other value would be equivalent to "true" (i.e. there is at least one register file available).
So, an implicit conversion would still do the job.

tools/llvm-mca/Stage.h

34 ↗

(On Diff #160225)

I think this comment (as well as other comments in the Stage.h) are misleading.
Here we are talking about the execution of a single instruction (described by an InstRef).

That statement should say that a stage returns Continue if it has successfully processed the instruction in input (identified by an InstRef), and that instruction is ready to be moved to the next stage during this same cycle.

In retrospect, most of the comments in Stage.h should be changed/improved.
I tried to read those comments the other day, and it was unclear what "execution" meant in that context. I think we should be more precise and emphasize that we are talking about execution "from an instruction point of view". Or something like that (sorry for my English). Basically, I am a bit concerned about the quality of some code comments...

tools/llvm-mca/llvm-mca.cpp

509 ↗

(On Diff #160225)

You don't need to return. report_fatal_error calls exit() inside. It also returns 1 (not -1).
Please remove this return.

550 ↗

(On Diff #160225)

You don't need to return. report_fatal_error calls exit() inside. It also returns 1 (not -1).
Please remove this return.

[mattd]

Addressed comments.

[mattd]

tools/llvm-mca/RegisterFile.cpp

305–314 ↗

(On Diff #160225)

I understand we don't want to spam the user with warnings; however, I think we should be aware of this (rare) pathological case if it occurs. I've enabled a DEBUG message now, so that if this issue occurs, then someone investigating this in debug will be aware of the situation.

tools/llvm-mca/llvm-mca.cpp

509 ↗

(On Diff #160225)

The return is definitely redundant. My justification for adding that statement was to make it clear that the program/function ends there, a return catches the syntax highlight.

[andreadb]

tools/llvm-mca/InstrBuilder.cpp

218–221 ↗

(On Diff #160379)

Surround this statement with braces.

287–289 ↗

(On Diff #160379)

Same.

343–344 ↗

(On Diff #160379)

Same.

350 ↗

(On Diff #160379)

Revert this change. WithColor::note() already adds string prefix "note:".
Also, you are printing "instruction:" twice.

tools/llvm-mca/Pipeline.cpp

88 ↗

(On Diff #160379)

I wonder if it is more readable to use Val.get() here... It is up to you.

tools/llvm-mca/RegisterFile.h

160–162 ↗

(On Diff #160379)

There is no warning generated from that method (there is only a debug print).
I suggest to just drop this comment.

tools/llvm-mca/Stage.h

42 ↗

(On Diff #160379)

Add a newline after the semicolon.

[mattd]

• Addressed comments:
  • Added braces.
  • Removed a stale comment and initializer.
  • Using Expected::get in a few places instead of operator* in Pipeline.cpp.

[andreadb]

LGTM. Thanks!

llvm/trunk/tools/llvm-mca/DispatchStage.h

DispatchStage(const llvm::MCSubtargetInfo &Subtarget,
       : DispatchWidth(MaxDispatchWidth), AvailableEntries(MaxDispatchWidth),
         CarryOver(0U), STI(Subtarget), RCU(R), PRF(F), SC(Sched) {}
 
   // We can always try to dispatch, so returning false is okay in this case.
   // The retire stage, which controls the RCU, might have items to complete but
   // RetireStage::hasWorkToComplete will check for that case.
   virtual bool hasWorkToComplete() const override final { return false; }
   virtual void cycleStart() override final;
-  virtual bool execute(InstRef &IR) override final;
+  virtual Status execute(InstRef &IR) override final;
   void notifyDispatchStall(const InstRef &IR, unsigned EventType);
 
 #ifndef NDEBUG
   void dump() const;
 #endif
 };
 } // namespace mca
 
 #endif // LLVM_TOOLS_LLVM_MCA_DISPATCH_STAGE_H

llvm/trunk/tools/llvm-mca/DispatchStage.cpp

void DispatchStage::dispatch(InstRef IR) {
   notifyInstructionDispatched(IR, RegisterFiles);
 }
 
 void DispatchStage::cycleStart() {
   AvailableEntries = CarryOver >= DispatchWidth ? 0 : DispatchWidth - CarryOver;
   CarryOver = CarryOver >= DispatchWidth ? CarryOver - DispatchWidth : 0U;
 }
 
-bool DispatchStage::execute(InstRef &IR) {
+Stage::Status DispatchStage::execute(InstRef &IR) {
   const InstrDesc &Desc = IR.getInstruction()->getDesc();
   if (!isAvailable(Desc.NumMicroOps) || !canDispatch(IR))
-    return false;
+    return Stage::Stop;
   dispatch(IR);
-  return true;
+  return Stage::Continue;
 }
 
 #ifndef NDEBUG
 void DispatchStage::dump() const {
   PRF.dump();
   RCU.dump();
 }
 #endif
 } // namespace mca

llvm/trunk/tools/llvm-mca/ExecuteStage.h

public:
   ExecuteStage(const ExecuteStage &Other) = delete;
   ExecuteStage &operator=(const ExecuteStage &Other) = delete;
 
   // The ExecuteStage will always complete all of its work per call to
   // execute(), so it is never left in a 'to-be-processed' state.
   virtual bool hasWorkToComplete() const override final { return false; }
 
   virtual void cycleStart() override final;
-  virtual bool execute(InstRef &IR) override final;
+  virtual Status execute(InstRef &IR) override final;
 
   void
   notifyInstructionIssued(const InstRef &IR,
                           llvm::ArrayRef<std::pair<ResourceRef, double>> Used);
   void notifyInstructionExecuted(const InstRef &IR);
   void notifyInstructionReady(const InstRef &IR);
   void notifyResourceAvailable(const ResourceRef &RR);
 

llvm/trunk/tools/llvm-mca/ExecuteStage.cpp

 // ready or executed.
 void ExecuteStage::cycleStart() {
   reclaimSchedulerResources();
   updateSchedulerQueues();
   issueReadyInstructions();
 }
 
 // Schedule the instruction for execution on the hardware.
-bool ExecuteStage::execute(InstRef &IR) {
+Stage::Status ExecuteStage::execute(InstRef &IR) {
 #ifndef NDEBUG
   // Ensure that the HWS has not stored this instruction in its queues.
   HWS.sanityCheck(IR);
 #endif
   // Reserve a slot in each buffered resource. Also, mark units with
   // BufferSize=0 as reserved. Resources with a buffer size of zero will only
   // be released after MCIS is issued, and all the ResourceCycles for those
   // units have been consumed.
   const InstrDesc &Desc = IR.getInstruction()->getDesc();
   HWS.reserveBuffers(Desc.Buffers);
   notifyReservedBuffers(Desc.Buffers);
 
   // Obtain a slot in the LSU.  If we cannot reserve resources, return true, so
   // that succeeding stages can make progress.
   if (!HWS.reserveResources(IR))
-    return true;
+    return Stage::Continue;
 
   // If we did not return early, then the scheduler is ready for execution.
   notifyInstructionReady(IR);
 
   // Don't add a zero-latency instruction to the Wait or Ready queue.
   // A zero-latency instruction doesn't consume any scheduler resources. That is
   // because it doesn't need to be executed, and it is often removed at register
   // renaming stage. For example, register-register moves are often optimized at
   // register renaming stage by simply updating register aliases. On some
   // targets, zero-idiom instructions (for example: a xor that clears the value
   // of a register) are treated specially, and are often eliminated at register
   // renaming stage.
   //
   // Instructions that use an in-order dispatch/issue processor resource must be
   // issued immediately to the pipeline(s). Any other in-order buffered
   // resources (i.e. BufferSize=1) is consumed.
   //
   // If we cannot issue immediately, the HWS will add IR to its ready queue for
   // execution later, so we must return early here.
   if (!HWS.issueImmediately(IR))
-    return true;
+    return Stage::Continue;
 
   LLVM_DEBUG(dbgs() << "[SCHEDULER] Instruction #" << IR
                     << " issued immediately\n");
 
   // Issue IR.  The resources for this issuance will be placed in 'Used.'
   SmallVector<std::pair<ResourceRef, double>, 4> Used;
   HWS.issueInstruction(IR, Used);
 
   // Perform notifications.
   notifyReleasedBuffers(Desc.Buffers);
   notifyInstructionIssued(IR, Used);
   if (IR.getInstruction()->isExecuted())
     notifyInstructionExecuted(IR);
 
-  return true;
+  return Stage::Continue;
 }
 
 void ExecuteStage::notifyInstructionExecuted(const InstRef &IR) {
   HWS.onInstructionExecuted(IR);
   LLVM_DEBUG(dbgs() << "[E] Instruction Executed: #" << IR << '\n');
   notifyEvent<HWInstructionEvent>(
       HWInstructionEvent(HWInstructionEvent::Executed, IR));
   RCU.onInstructionExecuted(IR.getInstruction()->getRCUTokenID());

llvm/trunk/tools/llvm-mca/FetchStage.h

class FetchStage : public Stage {
   SourceMgr &SM;
 
 public:
   FetchStage(InstrBuilder &IB, SourceMgr &SM) : IB(IB), SM(SM) {}
   FetchStage(const FetchStage &Other) = delete;
   FetchStage &operator=(const FetchStage &Other) = delete;
 
   bool hasWorkToComplete() const override final;
-  bool execute(InstRef &IR) override final;
+  Status execute(InstRef &IR) override final;
   void postExecute() override final;
   void cycleEnd() override final;
 };
 
 } // namespace mca
 
 #endif // LLVM_TOOLS_LLVM_MCA_FETCH_STAGE_H

llvm/trunk/tools/llvm-mca/FetchStage.cpp

 //===----------------------------------------------------------------------===//
 
 #include "FetchStage.h"
 
 namespace mca {
 
 bool FetchStage::hasWorkToComplete() const { return SM.hasNext(); }
 
-bool FetchStage::execute(InstRef &IR) {
+Stage::Status FetchStage::execute(InstRef &IR) {
   if (!SM.hasNext())
-    return false;
+    return Stage::Stop;
   const SourceRef SR = SM.peekNext();
-  std::unique_ptr<Instruction> I = IB.createInstruction(*SR.second);
+  llvm::Expected<std::unique_ptr<Instruction>> InstOrErr =
+      IB.createInstruction(*SR.second);
+  if (!InstOrErr)
+    return InstOrErr.takeError();
+  std::unique_ptr<Instruction> I = std::move(*InstOrErr);
   IR = InstRef(SR.first, I.get());
   Instructions[IR.getSourceIndex()] = std::move(I);
-  return true;
+  return Stage::Continue;
 }
 
 void FetchStage::postExecute() { SM.updateNext(); }
 
 void FetchStage::cycleEnd() {
   // Find the first instruction which hasn't been retired.
   const InstMap::iterator It =
       llvm::find_if(Instructions, [](const InstMap::value_type &KeyValuePair) {

llvm/trunk/tools/llvm-mca/InstrBuilder.h

 
 #include "Instruction.h"
 #include "Support.h"
 #include "llvm/MC/MCInstPrinter.h"
 #include "llvm/MC/MCInstrAnalysis.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/Support/Error.h"
 
 namespace mca {
 
 class DispatchUnit;
 
 /// A builder class that knows how to construct Instruction objects.
 ///
 /// Every llvm-mca Instruction is described by an object of class InstrDesc.
class InstrBuilder {
   const llvm::MCInstrAnalysis &MCIA;
   llvm::MCInstPrinter &MCIP;
   llvm::SmallVector<uint64_t, 8> ProcResourceMasks;
 
   llvm::DenseMap<unsigned short, std::unique_ptr<const InstrDesc>> Descriptors;
   llvm::DenseMap<const llvm::MCInst *, std::unique_ptr<const InstrDesc>>
       VariantDescriptors;
 
-  const InstrDesc &createInstrDescImpl(const llvm::MCInst &MCI);
-  const InstrDesc &getOrCreateInstrDesc(const llvm::MCInst &MCI);
+  llvm::Expected<const InstrDesc &>
+  createInstrDescImpl(const llvm::MCInst &MCI);
+  llvm::Expected<const InstrDesc &>
+  getOrCreateInstrDesc(const llvm::MCInst &MCI);
 
   InstrBuilder(const InstrBuilder &) = delete;
   InstrBuilder &operator=(const InstrBuilder &) = delete;
 
-  void populateWrites(InstrDesc &ID, const llvm::MCInst &MCI,
+  llvm::Error populateWrites(InstrDesc &ID, const llvm::MCInst &MCI,
                              unsigned SchedClassID);
-  void populateReads(InstrDesc &ID, const llvm::MCInst &MCI,
+  llvm::Error populateReads(InstrDesc &ID, const llvm::MCInst &MCI,
                             unsigned SchedClassID);
 
 public:
   InstrBuilder(const llvm::MCSubtargetInfo &sti, const llvm::MCInstrInfo &mcii,
                const llvm::MCRegisterInfo &mri,
                const llvm::MCInstrAnalysis &mcia, llvm::MCInstPrinter &mcip)
       : STI(sti), MCII(mcii), MRI(mri), MCIA(mcia), MCIP(mcip),
         ProcResourceMasks(STI.getSchedModel().getNumProcResourceKinds()) {
     computeProcResourceMasks(STI.getSchedModel(), ProcResourceMasks);
   }
 
   // Returns an array of processor resource masks.
   // Masks are computed by function mca::computeProcResourceMasks. see
   // Support.h for a description of how masks are computed and how masks can be
   // used to solve set membership problems.
   llvm::ArrayRef<uint64_t> getProcResourceMasks() const {
     return ProcResourceMasks;
   }
 
   void clear() { VariantDescriptors.shrink_and_clear(); }
 
-  std::unique_ptr<Instruction> createInstruction(const llvm::MCInst &MCI);
+  llvm::Expected<std::unique_ptr<Instruction>>
+  createInstruction(const llvm::MCInst &MCI);
 };
 } // namespace mca
 
 #endif

llvm/trunk/tools/llvm-mca/InstrBuilder.cpp

if (MCDesc.isCall()) {
     return;
   }
 
   int Latency = MCSchedModel::computeInstrLatency(STI, SCDesc);
   // If latency is unknown, then conservatively assume a MaxLatency of 100cy.
   ID.MaxLatency = Latency < 0 ? 100U : static_cast<unsigned>(Latency);
 }
 
-void InstrBuilder::populateWrites(InstrDesc &ID, const MCInst &MCI,
+Error InstrBuilder::populateWrites(InstrDesc &ID, const MCInst &MCI,
                                    unsigned SchedClassID) {
   const MCInstrDesc &MCDesc = MCII.get(MCI.getOpcode());
   const MCSchedModel &SM = STI.getSchedModel();
   const MCSchedClassDesc &SCDesc = *SM.getSchedClassDesc(SchedClassID);
 
   // These are for now the (strong) assumptions made by this algorithm:
   //  * The number of explicit and implicit register definitions in a MCInst
   //    matches the number of explicit and implicit definitions according to
   //    the opcode descriptor (MCInstrDesc).
for (; i < MCI.getNumOperands() && CurrentDef < NumExplicitDefs; ++i) {
     LLVM_DEBUG({
       dbgs() << "\t\t[Def] OpIdx=" << Write.OpIndex
              << ", Latency=" << Write.Latency
              << ", WriteResourceID=" << Write.SClassOrWriteResourceID << '\n';
     });
     CurrentDef++;
   }
 
-  if (CurrentDef != NumExplicitDefs)
-    llvm::report_fatal_error(
-        "error: Expected more register operand definitions. ");
+  if (CurrentDef != NumExplicitDefs) {
+    return make_error<StringError>(
+        "error: Expected more register operand definitions.",
+        inconvertibleErrorCode());
+  }
 
   CurrentDef = 0;
   for (CurrentDef = 0; CurrentDef < NumImplicitDefs; ++CurrentDef) {
     unsigned Index = NumExplicitDefs + CurrentDef;
     WriteDescriptor &Write = ID.Writes[Index];
     Write.OpIndex = ~CurrentDef;
     Write.RegisterID = MCDesc.getImplicitDefs()[CurrentDef];
     if (Index < NumWriteLatencyEntries) {
for (CurrentDef = 0; CurrentDef < NumImplicitDefs; ++CurrentDef) {
     });
   }
 
   if (MCDesc.hasOptionalDef()) {
     // Always assume that the optional definition is the last operand of the
     // MCInst sequence.
     const MCOperand &Op = MCI.getOperand(MCI.getNumOperands() - 1);
     if (i == MCI.getNumOperands() || !Op.isReg())
-      llvm::report_fatal_error(
+      return make_error<StringError>(
           "error: expected a register operand for an optional "
-          "definition. Instruction has not be correctly analyzed.\n",
-          false);
+          "definition. Instruction has not be correctly analyzed.",
+          inconvertibleErrorCode());
 
     WriteDescriptor &Write = ID.Writes[TotalDefs - 1];
     Write.OpIndex = MCI.getNumOperands() - 1;
     // Assign a default latency for this write.
     Write.Latency = ID.MaxLatency;
     Write.SClassOrWriteResourceID = 0;
     Write.IsOptionalDef = true;
   }
+
+  return ErrorSuccess();
 }
 
-void InstrBuilder::populateReads(InstrDesc &ID, const MCInst &MCI,
+Error InstrBuilder::populateReads(InstrDesc &ID, const MCInst &MCI,
                                   unsigned SchedClassID) {
   const MCInstrDesc &MCDesc = MCII.get(MCI.getOpcode());
   unsigned NumExplicitDefs = MCDesc.getNumDefs();
 
   // Skip explicit definitions.
   unsigned i = 0;
   for (; i < MCI.getNumOperands() && NumExplicitDefs; ++i) {
     const MCOperand &Op = MCI.getOperand(i);
     if (Op.isReg())
       NumExplicitDefs--;
   }
 
-  if (NumExplicitDefs)
-    llvm::report_fatal_error(
-        "error: Expected more register operand definitions. ", false);
+  if (NumExplicitDefs) {
+    return make_error<StringError>(
+        "error: Expected more register operand definitions. ",
+        inconvertibleErrorCode());
+  }
 
   unsigned NumExplicitUses = MCI.getNumOperands() - i;
   unsigned NumImplicitUses = MCDesc.getNumImplicitUses();
   if (MCDesc.hasOptionalDef()) {
     assert(NumExplicitUses);
     NumExplicitUses--;
   }
   unsigned TotalUses = NumExplicitUses + NumImplicitUses;
   if (!TotalUses)
-    return;
+    return ErrorSuccess();
 
   ID.Reads.resize(TotalUses);
   for (unsigned CurrentUse = 0; CurrentUse < NumExplicitUses; ++CurrentUse) {
     ReadDescriptor &Read = ID.Reads[CurrentUse];
     Read.OpIndex = i + CurrentUse;
     Read.UseIndex = CurrentUse;
     Read.SchedClassID = SchedClassID;
     LLVM_DEBUG(dbgs() << "\t\t[Use] OpIdx=" << Read.OpIndex
                       << ", UseIndex=" << Read.UseIndex << '\n');
   }
 
   for (unsigned CurrentUse = 0; CurrentUse < NumImplicitUses; ++CurrentUse) {
     ReadDescriptor &Read = ID.Reads[NumExplicitUses + CurrentUse];
     Read.OpIndex = ~CurrentUse;
     Read.UseIndex = NumExplicitUses + CurrentUse;
     Read.RegisterID = MCDesc.getImplicitUses()[CurrentUse];
     Read.SchedClassID = SchedClassID;
     LLVM_DEBUG(dbgs() << "\t\t[Use] OpIdx=" << Read.OpIndex << ", RegisterID="
                       << MRI.getName(Read.RegisterID) << '\n');
   }
+  return ErrorSuccess();
 }
 
-const InstrDesc &InstrBuilder::createInstrDescImpl(const MCInst &MCI) {
+Expected<const InstrDesc &>
+InstrBuilder::createInstrDescImpl(const MCInst &MCI) {
   assert(STI.getSchedModel().hasInstrSchedModel() &&
          "Itineraries are not yet supported!");
 
   // Obtain the instruction descriptor from the opcode.
   unsigned short Opcode = MCI.getOpcode();
   const MCInstrDesc &MCDesc = MCII.get(Opcode);
   const MCSchedModel &SM = STI.getSchedModel();
 
   // Then obtain the scheduling class information from the instruction.
   unsigned SchedClassID = MCDesc.getSchedClass();
   unsigned CPUID = SM.getProcessorID();
 
   // Try to solve variant scheduling classes.
   if (SchedClassID) {
     while (SchedClassID && SM.getSchedClassDesc(SchedClassID)->isVariant())
       SchedClassID = STI.resolveVariantSchedClass(SchedClassID, &MCI, CPUID);
 
-    if (!SchedClassID)
-      llvm::report_fatal_error("unable to resolve this variant class.");
+    if (!SchedClassID) {
+      return make_error<StringError>("unable to resolve this variant class.",
+                                     inconvertibleErrorCode());
+    }
   }
 
-  // Check if this instruction is supported. Otherwise, report a fatal error.
+  // Check if this instruction is supported. Otherwise, report an error.
   const MCSchedClassDesc &SCDesc = *SM.getSchedClassDesc(SchedClassID);
   if (SCDesc.NumMicroOps == MCSchedClassDesc::InvalidNumMicroOps) {
     std::string ToString;
     llvm::raw_string_ostream OS(ToString);
     WithColor::error() << "found an unsupported instruction in the input"
                        << " assembly sequence.\n";
     MCIP.printInst(&MCI, OS, "", STI);
     OS.flush();
-
     WithColor::note() << "instruction: " << ToString << '\n';
-    llvm::report_fatal_error(
-        "Don't know how to analyze unsupported instructions.");
+    return make_error<StringError>(
+        "Don't know how to analyze unsupported instructions",
+        inconvertibleErrorCode());
   }
 
   // Create a new empty descriptor.
   std::unique_ptr<InstrDesc> ID = llvm::make_unique<InstrDesc>();
   ID->NumMicroOps = SCDesc.NumMicroOps;
 
   if (MCDesc.isCall()) {
     // We don't correctly model calls.
InstrBuilder::createInstrDescImpl(const MCInst &MCI) {
   }
 
   ID->MayLoad = MCDesc.mayLoad();
   ID->MayStore = MCDesc.mayStore();
   ID->HasSideEffects = MCDesc.hasUnmodeledSideEffects();
 
   initializeUsedResources(*ID, SCDesc, STI, ProcResourceMasks);
   computeMaxLatency(*ID, MCDesc, SCDesc, STI);
-  populateWrites(*ID, MCI, SchedClassID);
-  populateReads(*ID, MCI, SchedClassID);
+  if (auto Err = populateWrites(*ID, MCI, SchedClassID))
+    return std::move(Err);
+  if (auto Err = populateReads(*ID, MCI, SchedClassID))
+    return std::move(Err);
 
   LLVM_DEBUG(dbgs() << "\t\tMaxLatency=" << ID->MaxLatency << '\n');
   LLVM_DEBUG(dbgs() << "\t\tNumMicroOps=" << ID->NumMicroOps << '\n');
 
   // Now add the new descriptor.
   SchedClassID = MCDesc.getSchedClass();
   if (!SM.getSchedClassDesc(SchedClassID)->isVariant()) {
     Descriptors[MCI.getOpcode()] = std::move(ID);
     return *Descriptors[MCI.getOpcode()];
   }
 
   VariantDescriptors[&MCI] = std::move(ID);
   return *VariantDescriptors[&MCI];
 }
 
-const InstrDesc &InstrBuilder::getOrCreateInstrDesc(const MCInst &MCI) {
+Expected<const InstrDesc &>
+InstrBuilder::getOrCreateInstrDesc(const MCInst &MCI) {
   if (Descriptors.find_as(MCI.getOpcode()) != Descriptors.end())
     return *Descriptors[MCI.getOpcode()];
 
   if (VariantDescriptors.find(&MCI) != VariantDescriptors.end())
     return *VariantDescriptors[&MCI];
 
   return createInstrDescImpl(MCI);
 }
 
-std::unique_ptr<Instruction>
+Expected<std::unique_ptr<Instruction>>
 InstrBuilder::createInstruction(const MCInst &MCI) {
-  const InstrDesc &D = getOrCreateInstrDesc(MCI);
+  Expected<const InstrDesc &> DescOrErr = getOrCreateInstrDesc(MCI);
+  if (!DescOrErr)
+    return DescOrErr.takeError();
+  const InstrDesc &D = *DescOrErr;
   std::unique_ptr<Instruction> NewIS = llvm::make_unique<Instruction>(D);
 
   // Initialize Reads first.
   for (const ReadDescriptor &RD : D.Reads) {
     int RegID = -1;
     if (!RD.isImplicitRead()) {
       // explicit read.
       const MCOperand &Op = MCI.getOperand(RD.OpIndex);
for (const ReadDescriptor &RD : D.Reads) {
 
     // Okay, this is a register operand. Create a ReadState for it.
     assert(RegID > 0 && "Invalid register ID found!");
     NewIS->getUses().emplace_back(llvm::make_unique<ReadState>(RD, RegID));
   }
 
   // Early exit if there are no writes.
   if (D.Writes.empty())
-    return NewIS;
+    return std::move(NewIS);
 
   // Track register writes that implicitly clear the upper portion of the
   // underlying super-registers using an APInt.
   APInt WriteMask(D.Writes.size(), 0);
 
   // Now query the MCInstrAnalysis object to obtain information about which
   // register writes implicitly clear the upper portion of a super-register.
   MCIA.clearsSuperRegisters(MRI, MCI, WriteMask);
for (const WriteDescriptor &WD : D.Writes) {
     }
 
     assert(RegID && "Expected a valid register ID!");
     NewIS->getDefs().emplace_back(llvm::make_unique<WriteState>(
         WD, RegID, /* ClearsSuperRegs */ WriteMask[WriteIndex]));
     ++WriteIndex;
   }
 
-  return NewIS;
+  return std::move(NewIS);
 }
 } // namespace mca

llvm/trunk/tools/llvm-mca/InstructionTables.h

class InstructionTables : public Stage {
   InstrBuilder &IB;
   llvm::SmallVector<std::pair<ResourceRef, double>, 4> UsedResources;
 
 public:
   InstructionTables(const llvm::MCSchedModel &Model, InstrBuilder &Builder)
       : Stage(), SM(Model), IB(Builder) {}
 
   bool hasWorkToComplete() const override final { return false; }
-  bool execute(InstRef &IR) override final;
+  Status execute(InstRef &IR) override final;
 };
 } // namespace mca
 
 #endif

llvm/trunk/tools/llvm-mca/InstructionTables.cpp

 //===----------------------------------------------------------------------===//
 
 #include "InstructionTables.h"
 
 namespace mca {
 
 using namespace llvm;
 
-bool InstructionTables::execute(InstRef &IR) {
+Stage::Status InstructionTables::execute(InstRef &IR) {
   ArrayRef<uint64_t> Masks = IB.getProcResourceMasks();
   const InstrDesc &Desc = IR.getInstruction()->getDesc();
   UsedResources.clear();
 
   // Identify the resources consumed by this instruction.
   for (const std::pair<uint64_t, ResourceUsage> Resource : Desc.Resources) {
     // Skip zero-cycle resources (i.e., unused resources).
     if (!Resource.second.size())
for (unsigned I1 = 0; I1 < NumUnits; ++I1) {
         UsedResources.emplace_back(std::make_pair(ResourceUnit, RUCycles));
       }
     }
   }
 
   // Send a fake instruction issued event to all the views.
   HWInstructionIssuedEvent Event(IR, UsedResources);
   notifyEvent<HWInstructionIssuedEvent>(Event);
-  return true;
+  return Stage::Continue;
 }
 
 } // namespace mca

llvm/trunk/tools/llvm-mca/Pipeline.h

 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_TOOLS_LLVM_MCA_PIPELINE_H
 #define LLVM_TOOLS_LLVM_MCA_PIPELINE_H
 
 #include "Scheduler.h"
 #include "Stage.h"
 #include "llvm/ADT/SmallVector.h"
+#include "llvm/Support/Error.h"
 
 namespace mca {
 
 class HWEventListener;
 class HWInstructionEvent;
 class HWStallEvent;
 
 /// A pipeline for a specific subtarget.
class Pipeline {
   Pipeline &operator=(const Pipeline &P) = delete;
 
   /// An ordered list of stages that define this instruction pipeline.
   llvm::SmallVector<std::unique_ptr<Stage>, 8> Stages;
   std::set<HWEventListener *> Listeners;
   unsigned Cycles;
 
   void preExecuteStages();
-  bool executeStages(InstRef &IR);
+  Stage::Status executeStages(InstRef &IR);
   void postExecuteStages();
-  void runCycle();
+  llvm::Error runCycle();
 
   bool hasWorkToProcess();
   void notifyCycleBegin();
   void notifyCycleEnd();
 
 public:
   Pipeline() : Cycles(0) {}
   void appendStage(std::unique_ptr<Stage> S) { Stages.push_back(std::move(S)); }
-  void run();
+  llvm::Error run();
   void addEventListener(HWEventListener *Listener);
 };
 } // namespace mca
 
 #endif // LLVM_TOOLS_LLVM_MCA_PIPELINE_H

llvm/trunk/tools/llvm-mca/Pipeline.cpp

bool Pipeline::hasWorkToProcess() {
   const auto It = llvm::find_if(Stages, [](const std::unique_ptr<Stage> &S) {
     return S->hasWorkToComplete();
   });
   return It != Stages.end();
 }
 
 // This routine returns early if any stage returns 'false' after execute() is
 // called on it.
-bool Pipeline::executeStages(InstRef &IR) {
-  for (const std::unique_ptr<Stage> &S : Stages)
-    if (!S->execute(IR))
-      return false;
-  return true;
+Stage::Status Pipeline::executeStages(InstRef &IR) {
+  for (const std::unique_ptr<Stage> &S : Stages) {
+    Stage::Status StatusOrErr = S->execute(IR);
+    if (!StatusOrErr)
+      return StatusOrErr.takeError();
+    else if (StatusOrErr.get() == Stage::Stop)
+      return Stage::Stop;
+  }
+  return Stage::Continue;
 }
 
 void Pipeline::preExecuteStages() {
   for (const std::unique_ptr<Stage> &S : Stages)
     S->preExecute();
 }
 
 void Pipeline::postExecuteStages() {
   for (const std::unique_ptr<Stage> &S : Stages)
     S->postExecute();
 }
 
-void Pipeline::run() {
+llvm::Error Pipeline::run() {
   while (hasWorkToProcess()) {
     notifyCycleBegin();
-    runCycle();
+    if (llvm::Error Err = runCycle())
+      return Err;
     notifyCycleEnd();
     ++Cycles;
   }
+  return llvm::ErrorSuccess();
 }
 
-void Pipeline::runCycle() {
+llvm::Error Pipeline::runCycle() {
   // Update the stages before we do any processing for this cycle.
   InstRef IR;
   for (auto &S : Stages)
     S->cycleStart();
 
   // Continue executing this cycle until any stage claims it cannot make
   // progress.
   while (true) {
     preExecuteStages();
-    if (!executeStages(IR))
+    Stage::Status Val = executeStages(IR);
+    if (!Val)
+      return Val.takeError();
+    if (Val.get() == Stage::Stop)
       break;
     postExecuteStages();
   }
 
   for (auto &S : Stages)
     S->cycleEnd();
+  return llvm::ErrorSuccess();
 }
 
 void Pipeline::notifyCycleBegin() {
   LLVM_DEBUG(dbgs() << "[E] Cycle begin: " << Cycles << '\n');
   for (HWEventListener *Listener : Listeners)
     Listener->onCycleBegin();
 }
 
 void Pipeline::notifyCycleEnd() {
   LLVM_DEBUG(dbgs() << "[E] Cycle end: " << Cycles << "\n\n");
   for (HWEventListener *Listener : Listeners)
     Listener->onCycleEnd();
 }
 } // namespace mca.

llvm/trunk/tools/llvm-mca/RegisterFile.h

 
 #ifndef LLVM_TOOLS_LLVM_MCA_REGISTER_FILE_H
 #define LLVM_TOOLS_LLVM_MCA_REGISTER_FILE_H
 
 #include "HardwareUnit.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCSchedule.h"
+#include "llvm/Support/Error.h"
 
 namespace mca {
 
 class ReadState;
 class WriteState;
 class WriteRef;
 
 /// Manages hardware register files, and tracks register definitions for

llvm/trunk/tools/llvm-mca/RegisterFile.cpp

if (!RMT.NumPhysRegs) {
       continue;
     }
 
     if (RMT.NumPhysRegs < NumRegs) {
       // The current register file is too small. This may occur if the number of
       // microarchitectural registers in register file #0 was changed by the
       // users via flag -reg-file-size. Alternatively, the scheduling model
       // specified a too small number of registers for this register file.
-      report_fatal_error(
-          "Not enough microarchitectural registers in the register file");
+      LLVM_DEBUG(dbgs() << "Not enough registers in the register file.\n");
+
+      // FIXME: Normalize the instruction register count to match the
+      // NumPhysRegs value.  This is a highly unusual case, and is not expected
+      // to occur.  This normalization is hiding an inconsistency in either the
+      // scheduling model or in the value that the user might have specified
+      // for NumPhysRegs.
+      NumRegs = RMT.NumPhysRegs;
     }
 
     if (RMT.NumPhysRegs < (RMT.NumUsedPhysRegs + NumRegs))
       Response |= (1U << I);
   }
 
   return Response;
 }

llvm/trunk/tools/llvm-mca/RetireStage.h

RetireStage(RetireControlUnit &R, RegisterFile &F)
       : Stage(), RCU(R), PRF(F) {}
   RetireStage(const RetireStage &Other) = delete;
   RetireStage &operator=(const RetireStage &Other) = delete;
 
   virtual bool hasWorkToComplete() const override final {
     return !RCU.isEmpty();
   }
   virtual void cycleStart() override final;
-  virtual bool execute(InstRef &IR) override final { return true; }
+  virtual Status execute(InstRef &IR) override final { return Stage::Continue; }
   void notifyInstructionRetired(const InstRef &IR);
   void onInstructionExecuted(unsigned TokenID);
 };
 
 } // namespace mca
 
 #endif // LLVM_TOOLS_LLVM_MCA_RETIRE_STAGE_H

llvm/trunk/tools/llvm-mca/Stage.h

 /// A chain of stages compose an instruction pipeline.
 ///
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_TOOLS_LLVM_MCA_STAGE_H
 #define LLVM_TOOLS_LLVM_MCA_STAGE_H
 
 #include "HWEventListener.h"
+#include "llvm/Support/Error.h"
 #include <set>
 
 namespace mca {
 
 class InstRef;
 
 class Stage {
   Stage(const Stage &Other) = delete;
   Stage &operator=(const Stage &Other) = delete;
   std::set<HWEventListener *> Listeners;
 
+public:
+  /// A Stage's execute() returns Continue, Stop, or an error.  Returning
+  /// Continue means that the stage successfully completed its 'execute'
+  /// action, and that the instruction being processed can be moved to the next
+  /// pipeline stage during this cycle.  Continue allows the pipeline to
+  /// continue calling 'execute' on subsequent stages.  Returning Stop
+  /// signifies that the stage ran into an error, and tells the pipeline to stop
+  /// passing the instruction to subsequent stages during this cycle.  Any
+  /// failures that occur during 'execute' are represented by the error variant
+  /// that is provided by the Expected template.
+  enum State { Stop, Continue };
+  using Status = llvm::Expected<State>;
+
 protected:
   const std::set<HWEventListener *> &getListeners() const { return Listeners; }
 
 public:
   Stage();
   virtual ~Stage() = default;
 
   /// Called prior to preExecute to ensure that the stage has items that it
public:
   /// Called as a cleanup and finalization phase after each execution.
   /// This will only be called if all stages return a success from their
   /// execute callback.  This can be called multiple times per cycle.
   virtual void postExecute() {}
 
   /// The primary action that this stage performs.
   /// Returning false prevents successor stages from having their 'execute'
   /// routine called.  This can be called multiple times during a single cycle.
-  virtual bool execute(InstRef &IR) = 0;
+  virtual Status execute(InstRef &IR) = 0;
 
   /// Add a listener to receive callbacks during the execution of this stage.
   void addListener(HWEventListener *Listener);
 
   /// Notify listeners of a particular hardware event.
   template <typename EventT> void notifyEvent(const EventT &Event) {
     for (HWEventListener *Listener : Listeners)
       Listener->onEvent(Event);
   }
 };
 
 } // namespace mca
 #endif // LLVM_TOOLS_LLVM_MCA_STAGE_H

llvm/trunk/tools/llvm-mca/llvm-mca.cpp

 #include "TimelineView.h"
 #include "llvm/MC/MCAsmInfo.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCObjectFileInfo.h"
 #include "llvm/MC/MCParser/MCTargetAsmParser.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/Support/CommandLine.h"
+#include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/ErrorOr.h"
 #include "llvm/Support/FileSystem.h"
 #include "llvm/Support/Host.h"
 #include "llvm/Support/InitLLVM.h"
 #include "llvm/Support/MemoryBuffer.h"
 #include "llvm/Support/SourceMgr.h"
 #include "llvm/Support/TargetRegistry.h"
 #include "llvm/Support/TargetSelect.h"
if (PrintInstructionTables) {
 
       // Create the views for this pipeline, execute, and emit a report.
       if (PrintInstructionInfoView) {
         Printer.addView(
             llvm::make_unique<mca::InstructionInfoView>(*STI, *MCII, S, *IP));
       }
       Printer.addView(
           llvm::make_unique<mca::ResourcePressureView>(*STI, *IP, S));
-      P->run();
+      auto Err = P->run();
+      if (Err)
+        report_fatal_error(toString(std::move(Err)));
       Printer.printReport(TOF->os());
       continue;
     }
 
     // Create a basic pipeline simulating an out-of-order backend.
     auto P = MCA.createDefaultPipeline(PO, IB, S);
     mca::PipelinePrinter Printer(*P);
 
if (PrintResourcePressureView)
       Printer.addView(
           llvm::make_unique<mca::ResourcePressureView>(*STI, *IP, S));
 
     if (PrintTimelineView) {
       Printer.addView(llvm::make_unique<mca::TimelineView>(
           *STI, *IP, S, TimelineMaxIterations, TimelineMaxCycles));
     }
 
-    P->run();
+    auto Err = P->run();
+    if (Err)
+      report_fatal_error(toString(std::move(Err)));
     Printer.printReport(TOF->os());
 
     // Clear the InstrBuilder internal state in preparation for another round.
     IB.clear();
   }
 
   TOF->keep();
   return 0;
 }