[llvm-mca] Introduce a simple (error/warning) status framework for mca.

[mattd]

Summary

The following framework provides a status notification system for handling
errors/warnings/notes produced within the pieces of llvm-mca that will
eventually become a library.

This patch is just an idea and only implements the fatal error handler. I'm
happy to build on it, if it appears to be the right approach.

The original prototype for the status framework, decorated a subset of llvm-mca
routines with llvm::Error, llvm::Expected. However, I became fearful that
such an approach was adding both overhead and complexity to the code, when all we really
want to do is offload some fatal errors to an error handler.

If this idea appears to be the correct approach, then I am happy to break
this idea into two separate patches. One patch to introduce Status.h and
another to make use of the items in Status.h

In the future we might still want llvm::Error/Expected to handle the
case of recoverable errors, but for fatal errors the solution in this patch seems
to be the least intrusive. And, of course, we'll want some tests for the
other handlers. The unsupported-instruction.s test is testing the fatal handler.

I made mca::Context inherit from StatusManager. I'm not sure that is the right
approach in the long-run, but for prototyping this idea out, it provides a
seamless interface between the mca::Context and the callers to the
status framework.

[mattd]

Abandoning in favor of https://reviews.llvm.org/D50561

test/tools/llvm-mca/X86/BtVer2/unsupported-instruction.s

 # RUN: not llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 %s 2>&1 | FileCheck %s
 
 bzhi %eax, %ebx, %ecx
 
-# CHECK: error: found an unsupported instruction in the input assembly sequence.
-# CHECK-NEXT: note: instruction:  bzhil %eax, %ebx, %ecx
+# CHECK: LLVM ERROR: Found an unsupported instruction in the input assembly sequence: bzhil %eax, %ebx, %ecx

tools/llvm-mca/Context.h

 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_TOOLS_LLVM_MCA_CONTEXT_H
 #define LLVM_TOOLS_LLVM_MCA_CONTEXT_H
 #include "HardwareUnit.h"
 #include "InstrBuilder.h"
 #include "Pipeline.h"
 #include "SourceMgr.h"
+#include "Status.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCSchedule.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include <memory>
 
 namespace mca {
 
 /// This is a convenience struct to hold the parameters necessary for creating
 /// the pre-built "default" out-of-order pipeline.
 struct PipelineOptions {
   PipelineOptions(unsigned DW, unsigned RFS, unsigned LQS, unsigned SQS,
                   bool NoAlias)
       : DispatchWidth(DW), RegisterFileSize(RFS), LoadQueueSize(LQS),
         StoreQueueSize(SQS), AssumeNoAlias(NoAlias) {}
   unsigned DispatchWidth;
   unsigned RegisterFileSize;
   unsigned LoadQueueSize;
   unsigned StoreQueueSize;
   bool AssumeNoAlias;
 };
 
-class Context {
+class Context : public StatusManager {
   llvm::SmallVector<std::unique_ptr<HardwareUnit>, 4> Hardware;
   const llvm::MCRegisterInfo &MRI;
   const llvm::MCSubtargetInfo &STI;
 
 public:
   Context(const llvm::MCRegisterInfo &R, const llvm::MCSubtargetInfo &S)
       : MRI(R), STI(S) {}
   Context(const Context &C) = delete;

tools/llvm-mca/Context.cpp

 
 std::unique_ptr<Pipeline>
 Context::createDefaultPipeline(const PipelineOptions &Opts, InstrBuilder &IB,
                                SourceMgr &SrcMgr) {
   const MCSchedModel &SM = STI.getSchedModel();
 
   // Create the hardware units defining the backend.
   auto RCU = llvm::make_unique<RetireControlUnit>(SM);
-  auto PRF = llvm::make_unique<RegisterFile>(SM, MRI, Opts.RegisterFileSize);
+  auto PRF =
+      llvm::make_unique<RegisterFile>(SM, MRI, *this, Opts.RegisterFileSize);
   auto HWS = llvm::make_unique<Scheduler>(
       SM, Opts.LoadQueueSize, Opts.StoreQueueSize, Opts.AssumeNoAlias);
 
   // Create the pipeline and its stages.
   auto P = llvm::make_unique<Pipeline>();
   auto F = llvm::make_unique<FetchStage>(IB, SrcMgr);
   auto D = llvm::make_unique<DispatchStage>(
       STI, MRI, Opts.RegisterFileSize, Opts.DispatchWidth, *RCU, *PRF, *HWS);

tools/llvm-mca/InstrBuilder.h

 #include "llvm/MC/MCInstPrinter.h"
 #include "llvm/MC/MCInstrAnalysis.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 
 namespace mca {
 
+class Context;
 class DispatchUnit;
 
 /// A builder class that knows how to construct Instruction objects.
 ///
 /// Every llvm-mca Instruction is described by an object of class InstrDesc.
 /// An InstrDesc describes which registers are read/written by the instruction,
 /// as well as the instruction latency and hardware resources consumed.
 ///
 /// This class is used by the tool to construct Instructions and instruction
 /// descriptors (i.e. InstrDesc objects).
 /// Information from the machine scheduling model is used to identify processor
 /// resources that are consumed by an instruction.
 class InstrBuilder {
   const llvm::MCSubtargetInfo &STI;
   const llvm::MCInstrInfo &MCII;
   const llvm::MCRegisterInfo &MRI;
   const llvm::MCInstrAnalysis &MCIA;
   llvm::MCInstPrinter &MCIP;
+  mca::Context &Ctx;
   llvm::SmallVector<uint64_t, 8> ProcResourceMasks;
 
   llvm::DenseMap<unsigned short, std::unique_ptr<const InstrDesc>> Descriptors;
   llvm::DenseMap<const llvm::MCInst *, std::unique_ptr<const InstrDesc>>
       VariantDescriptors;
 
   const InstrDesc &createInstrDescImpl(const llvm::MCInst &MCI);
   InstrBuilder(const InstrBuilder &) = delete;
   InstrBuilder &operator=(const InstrBuilder &) = delete;
 
   void populateWrites(InstrDesc &ID, const llvm::MCInst &MCI,
                       unsigned SchedClassID);
   void populateReads(InstrDesc &ID, const llvm::MCInst &MCI,
                      unsigned SchedClassID);
 
 public:
   InstrBuilder(const llvm::MCSubtargetInfo &sti, const llvm::MCInstrInfo &mcii,
                const llvm::MCRegisterInfo &mri,
-               const llvm::MCInstrAnalysis &mcia, llvm::MCInstPrinter &mcip)
-      : STI(sti), MCII(mcii), MRI(mri), MCIA(mcia), MCIP(mcip),
+               const llvm::MCInstrAnalysis &mcia, llvm::MCInstPrinter &mcip,
+               mca::Context &ctx)
+      : STI(sti), MCII(mcii), MRI(mri), MCIA(mcia), MCIP(mcip), Ctx(ctx),
         ProcResourceMasks(STI.getSchedModel().getNumProcResourceKinds()) {
     computeProcResourceMasks(STI.getSchedModel(), ProcResourceMasks);
   }
 
   const InstrDesc &getOrCreateInstrDesc(const llvm::MCInst &MCI);
   // Returns an array of processor resource masks.
   // Masks are computed by function mca::computeProcResourceMasks. see
   // Support.h for a description of how masks are computed and how masks can be

tools/llvm-mca/InstrBuilder.cpp

 //===--------------------- InstrBuilder.cpp ---------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \file
 ///
 /// This file implements the InstrBuilder interface.
 ///
 //===----------------------------------------------------------------------===//
 
 #include "InstrBuilder.h"
+#include "Context.h"
 #include "llvm/ADT/APInt.h"
 #include "llvm/ADT/DenseMap.h"
 #include "llvm/MC/MCInst.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/WithColor.h"
 #include "llvm/Support/raw_ostream.h"
 
 #define DEBUG_TYPE "llvm-mca"
LLVM_DEBUG({
       dbgs() << "\t\t[Def] OpIdx=" << Write.OpIndex
              << ", Latency=" << Write.Latency
              << ", WriteResourceID=" << Write.SClassOrWriteResourceID << '\n';
     });
     CurrentDef++;
   }
 
   if (CurrentDef != NumExplicitDefs)
-    llvm::report_fatal_error(
-        "error: Expected more register operand definitions. ");
+    Ctx.notifyFatalError("Expected more register operand definitions.");
 
   CurrentDef = 0;
   for (CurrentDef = 0; CurrentDef < NumImplicitDefs; ++CurrentDef) {
     unsigned Index = NumExplicitDefs + CurrentDef;
     WriteDescriptor &Write = ID.Writes[Index];
     Write.OpIndex = ~CurrentDef;
     Write.RegisterID = MCDesc.getImplicitDefs()[CurrentDef];
     if (Index < NumWriteLatencyEntries) {
for (CurrentDef = 0; CurrentDef < NumImplicitDefs; ++CurrentDef) {
     });
   }
 
   if (MCDesc.hasOptionalDef()) {
     // Always assume that the optional definition is the last operand of the
     // MCInst sequence.
     const MCOperand &Op = MCI.getOperand(MCI.getNumOperands() - 1);
     if (i == MCI.getNumOperands() || !Op.isReg())
-      llvm::report_fatal_error(
-          "error: expected a register operand for an optional "
-          "definition. Instruction has not be correctly analyzed.\n",
-          false);
+      Ctx.notifyFatalError(
+          "Expected a register operand for an optional "
+          "definition. Instruction has not be correctly analyzed.");
 
     WriteDescriptor &Write = ID.Writes[TotalDefs - 1];
     Write.OpIndex = MCI.getNumOperands() - 1;
     // Assign a default latency for this write.
     Write.Latency = ID.MaxLatency;
     Write.SClassOrWriteResourceID = 0;
     Write.IsOptionalDef = true;
   }
 }
 
 void InstrBuilder::populateReads(InstrDesc &ID, const MCInst &MCI,
                                  unsigned SchedClassID) {
   const MCInstrDesc &MCDesc = MCII.get(MCI.getOpcode());
   unsigned NumExplicitDefs = MCDesc.getNumDefs();
 
   // Skip explicit definitions.
   unsigned i = 0;
   for (; i < MCI.getNumOperands() && NumExplicitDefs; ++i) {
     const MCOperand &Op = MCI.getOperand(i);
     if (Op.isReg())
       NumExplicitDefs--;
   }
 
   if (NumExplicitDefs)
-    llvm::report_fatal_error(
-        "error: Expected more register operand definitions. ", false);
+    Ctx.notifyFatalError("Expected more register operand definitions.");
 
   unsigned NumExplicitUses = MCI.getNumOperands() - i;
   unsigned NumImplicitUses = MCDesc.getNumImplicitUses();
   if (MCDesc.hasOptionalDef()) {
     assert(NumExplicitUses);
     NumExplicitUses--;
   }
   unsigned TotalUses = NumExplicitUses + NumImplicitUses;
const InstrDesc &InstrBuilder::createInstrDescImpl(const MCInst &MCI) {
   unsigned CPUID = SM.getProcessorID();
 
   // Try to solve variant scheduling classes.
   if (SchedClassID) {
     while (SchedClassID && SM.getSchedClassDesc(SchedClassID)->isVariant())
       SchedClassID = STI.resolveVariantSchedClass(SchedClassID, &MCI, CPUID);
 
     if (!SchedClassID)
-      llvm::report_fatal_error("unable to resolve this variant class.");
+      Ctx.notifyFatalError("Unable to resolve this variant class.");
   }
 
   // Check if this instruction is supported. Otherwise, report a fatal error.
   const MCSchedClassDesc &SCDesc = *SM.getSchedClassDesc(SchedClassID);
   if (SCDesc.NumMicroOps == MCSchedClassDesc::InvalidNumMicroOps) {
     std::string ToString;
     llvm::raw_string_ostream OS(ToString);
-    WithColor::error() << "found an unsupported instruction in the input"
-                       << " assembly sequence.\n";
     MCIP.printInst(&MCI, OS, "", STI);
     OS.flush();
-
-    WithColor::note() << "instruction: " << ToString << '\n';
-    llvm::report_fatal_error(
-        "Don't know how to analyze unsupported instructions.");
+    Ctx.notifyFatalError(
+        "Found an unsupported instruction in the input assembly sequence: " +
+        ToString);
   }
 
   // Create a new empty descriptor.
   std::unique_ptr<InstrDesc> ID = llvm::make_unique<InstrDesc>();
   ID->NumMicroOps = SCDesc.NumMicroOps;
 
   if (MCDesc.isCall()) {
     // We don't correctly model calls.

tools/llvm-mca/RegisterFile.h

 
 #include "HardwareUnit.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCSchedule.h"
 
 namespace mca {
 
+class Context;
 class ReadState;
 class WriteState;
 class WriteRef;
 
 /// Manages hardware register files, and tracks register definitions for
 /// register renaming purposes.
 class RegisterFile : public HardwareUnit {
   const llvm::MCRegisterInfo &MRI;
+  Context &Ctx;
 
   // Each register file is associated with an instance of
   // RegisterMappingTracker.
   // A RegisterMappingTracker keeps track of the number of physical registers
   // which have been dynamically allocated by the simulator.
   struct RegisterMappingTracker {
     // The total number of physical registers that are available in this
     // register file for register renaming purpouses.  A value of zero for this
class RegisterFile : public HardwareUnit {
   // Create an instance of RegisterMappingTracker for every register file
   // specified by the processor model.
   // If no register file is specified, then this method creates a default
   // register file with an unbounded number of physical registers.
   void initialize(const llvm::MCSchedModel &SM, unsigned NumRegs);
 
 public:
   RegisterFile(const llvm::MCSchedModel &SM, const llvm::MCRegisterInfo &mri,
-               unsigned NumRegs = 0);
+               Context &C, unsigned NumRegs = 0);
 
   // This method updates the register mappings inserting a new register
   // definition. This method is also responsible for updating the number of
   // allocated physical registers in each register file modified by the write.
   // No physical regiser is allocated when flag ShouldAllocatePhysRegs is set.
   void addRegisterWrite(WriteRef Write,
                         llvm::MutableArrayRef<unsigned> UsedPhysRegs,
                         bool ShouldAllocatePhysRegs = true);

tools/llvm-mca/RegisterFile.cpp

 ///
 /// This file defines a register mapping file class.  This class is responsible
 /// for managing hardware register files and the tracking of data dependencies
 /// between registers.
 ///
 //===----------------------------------------------------------------------===//
 
 #include "RegisterFile.h"
+#include "Context.h"
 #include "Instruction.h"
 #include "llvm/Support/Debug.h"
 
 using namespace llvm;
 
 #define DEBUG_TYPE "llvm-mca"
 
 namespace mca {
 
 RegisterFile::RegisterFile(const llvm::MCSchedModel &SM,
-                           const llvm::MCRegisterInfo &mri, unsigned NumRegs)
-    : MRI(mri), RegisterMappings(mri.getNumRegs(),
-                                 {WriteRef(), {IndexPlusCostPairTy(0, 1), 0}}) {
+                           const llvm::MCRegisterInfo &mri, Context &C,
+                           unsigned NumRegs)
+    : MRI(mri), Ctx(C),
+      RegisterMappings(mri.getNumRegs(),
   initialize(SM, NumRegs);
 }
 
 void RegisterFile::initialize(const MCSchedModel &SM, unsigned NumRegs) {
   // Create a default register file that "sees" all the machine registers
   // declared by the target. The number of physical registers in the default
   // register file is set equal to `NumRegs`. A value of zero for `NumRegs`
   // means: this register file has an unbounded number of physical registers.
if (!RMT.NumPhysRegs) {
       continue;
     }
 
     if (RMT.NumPhysRegs < NumRegs) {
       // The current register file is too small. This may occur if the number of
       // microarchitectural registers in register file #0 was changed by the
       // users via flag -reg-file-size. Alternatively, the scheduling model
       // specified a too small number of registers for this register file.
-      report_fatal_error(
+      Ctx.notifyFatalError(
           "Not enough microarchitectural registers in the register file");
     }
 
     if (RMT.NumPhysRegs < (RMT.NumUsedPhysRegs + NumRegs))
       Response |= (1U << I);
   }
 
   return Response;

tools/llvm-mca/Status.h

+//===----------------------------- Status.h ---------------------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+/// \file
+///
+/// This file provides the status handling functionality of llvm-mca.
+/// Included here are the handlers and message type for reporting warnings and
+/// errors within llvm-mca.
+///
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_TOOLS_LLVM_MCA_STATUS_H
+#define LLVM_TOOLS_LLVM_MCA_STATUS_H
+
+#include "llvm/ADT/StringRef.h"
+#include <functional>
+#include <memory>
+#include <string>
+#include <vector>
+
+namespace mca {
+
+/// The following class defines the most basic level of messages
+/// communicated across the llvm-mca status handling framework.  The handlers
+/// can choose how to display these message and if additional action should be
+/// taken (e.g., calling exit or aborting).
+class StatusMessage {
+  std::string M;
+
+public:
+  StatusMessage(const char *Message) : M(Message) {}
+  StatusMessage(std::string Message) : M(Message) {}
+  llvm::StringRef getMessage() const { return M; }
+};
+
+using StatusCallback = std::function<void(const StatusMessage &M)>;
+
+/// Each status type (error, warning, etc.) has an associated handler.
+/// This class contains the callback routine that is triggered when
+/// a status event of type 'HandlerType' occurs.
+enum HandlerType { Error, FatalError, Note, Warning };
+class StatusHandler {
+  StatusCallback CB;
+  HandlerType Type;
+
+public:
+  StatusHandler(StatusCallback &Fn, HandlerType T) : CB(Fn), Type(T) {}
+  void operator()(const StatusMessage &SM) { CB(SM); }
+  HandlerType getType() const { return Type; }
+};
+
+/// This class contains the handlers used for communicating error messages.
+/// The notifyX methods are to be used to notify the handlers of a particular
+/// status change within the framework.
+class StatusManager {
+  std::vector<std::unique_ptr<StatusHandler>> Handlers;
+
+  void notify(const StatusMessage &M, HandlerType T) {
+    bool IssuedCallback = false;
+    for (auto &H : Handlers) {
+      if (H->getType() == T) {
+        (*H)(M);
+        IssuedCallback = true;
+      }
+    }
+    // If a notification was requested but no registered handler
+    // for that type of status notification exists, then assert.
+    assert(IssuedCallback && "No handlers found for notification type.");
+  }
+
+public:
+  void notifyFatalError(const StatusMessage &M) {
+    notify(M, HandlerType::FatalError);
+  }
+
+  void registerHandler(std::unique_ptr<StatusHandler> S) {
+    Handlers.push_back(std::move(S));
+  }
+
+  void registerHandler(StatusHandler S) {
+    registerHandler(llvm::make_unique<StatusHandler>(S));
+  }
+
+  void registerErrorHandler(StatusCallback CB) {
+    registerHandler(StatusHandler(CB, HandlerType::Error));
+  }
+
+  void registerFatalErrorHandler(StatusCallback CB) {
+    registerHandler(StatusHandler(CB, HandlerType::FatalError));
+  }
+
+  void registerNoteHandler(StatusCallback CB) {
+    registerHandler(StatusHandler(CB, HandlerType::Note));
+  }
+
+  void registerWarningHandler(StatusCallback CB) {
+    registerHandler(StatusHandler(CB, HandlerType::Warning));
+  }
+};
+
+} // namespace mca
+
+#endif // LLVM_TOOLS_LLVM_MCA_STATUS_H

tools/llvm-mca/llvm-mca.cpp

 #include "InstructionInfoView.h"
 #include "InstructionTables.h"
 #include "Pipeline.h"
 #include "PipelinePrinter.h"
 #include "RegisterFileStatistics.h"
 #include "ResourcePressureView.h"
 #include "RetireControlUnitStatistics.h"
 #include "SchedulerStatistics.h"
+#include "Status.h"
 #include "SummaryView.h"
 #include "TimelineView.h"
 #include "llvm/MC/MCAsmInfo.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCObjectFileInfo.h"
 #include "llvm/MC/MCParser/MCTargetAsmParser.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCStreamer.h"
int main(int argc, char **argv) {
   std::unique_ptr<llvm::ToolOutputFile> TOF = std::move(*OF);
 
   const MCSchedModel &SM = STI->getSchedModel();
 
   unsigned Width = SM.IssueWidth;
   if (DispatchWidth)
     Width = DispatchWidth;
 
-  // Create an instruction builder.
-  mca::InstrBuilder IB(*STI, *MCII, *MRI, *MCIA, *IP);
-
   // Create a context to control ownership of the pipeline hardware.
   mca::Context MCA(*MRI, *STI);
 
+  // Register a callback routine for handling fatal errors.
+  MCA.registerFatalErrorHandler([](const mca::StatusMessage &M) {
+    llvm::report_fatal_error(M.getMessage());
+  });
+
+  // Register a callback routine for handling warnings.
+  MCA.registerWarningHandler([](const mca::StatusMessage &M){
+    llvm::WithColor::warning() << M.getMessage() << '\n';
+  });
+
   mca::PipelineOptions PO(Width, RegisterFileSize, LoadQueueSize,
                           StoreQueueSize, AssumeNoAlias);
   
+  // Create an instruction builder.
+  mca::InstrBuilder IB(*STI, *MCII, *MRI, *MCIA, *IP, MCA);
+
   // Number each region in the sequence.
   unsigned RegionIdx = 0;
   for (const std::unique_ptr<mca::CodeRegion> &Region : Regions) {
     // Skip empty code regions.
     if (Region->empty())
       continue;
 
     // Don't print the header of this region if it is the default region, and