[mips][microMIPS] Implement ADDIUS5 instruction

[jkolek]

Summary

Implement 16-bit microMIPS add immediate unsigned word 5-bit register select instruction - ADDIUS5.

[sstankovic]

lib/Target/Mips/MicroMipsInstrInfo.td

13

I think that you don't need to define EncoderMethod, because this method (getSImm5Addius5Value) only truncates operand to 4 bits. The pattern for this operand (which I suppose will be added in one of the future patches) will ensure that operand is 4 bits.

test/MC/Mips/micromips-16-bit-instructions.s

12

You should also check whether the error messages are issued when the operand is out of range.

[jkolek]

Removed encoder method and added check for invalid instruction operand.

[sstankovic]

LGTM

Closed by commit rL219495 (authored by zjovanovic).

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

for (unsigned i = 0; i < MCID.getNumOperands(); i++) {
             expandMemInst(Inst, IDLoc, Instructions, MCID.mayLoad(), false);
             return false;
           }
         }
       }
     } // for
   }   // if load/store
 
+  if (inMicroMipsMode()) {
+    MCOperand Opnd;
+    int Imm;
+
+    switch (Inst.getOpcode()) {
+      default:
+        break;
+      case Mips::ADDIUS5_MM:
+        Opnd = Inst.getOperand(2);
+        if (!Opnd.isImm())
+          return Error(IDLoc, "expected immediate operand kind");
+        Imm = Opnd.getImm();
+        if (Imm < -8 || Imm > 7)
+          return Error(IDLoc, "immediate operand value out of range");
+        break;
+    }
+  }
+
   if (needsExpansion(Inst))
     return expandInstruction(Inst, IDLoc, Instructions);
   else
     Instructions.push_back(Inst);
 
   return false;
 }
 

lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h

unsigned getJumpTargetOpValueMM(const MCInst &MI, unsigned OpNo,
                                   const MCSubtargetInfo &STI) const;
 
   // getUImm5Lsl2Encoding - Return binary encoding of the microMIPS jump
   // target operand.
   unsigned getUImm5Lsl2Encoding(const MCInst &MI, unsigned OpNo,
                                 SmallVectorImpl<MCFixup> &Fixups,
                                 const MCSubtargetInfo &STI) const;
 
+  // getAddius5Value - Return binary encoding of the microMIPS addius5
+  // instruction immediate operand.
+  unsigned getSImm5Addius5Value(const MCInst &MI, unsigned OpNo,
+                                SmallVectorImpl<MCFixup> &Fixups,
+                                const MCSubtargetInfo &STI) const;
+
   // getBranchTargetOpValue - Return binary encoding of the branch
   // target operand. If the machine operand requires relocation,
   // record the relocation and return zero.
   unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
                                   SmallVectorImpl<MCFixup> &Fixups,
                                   const MCSubtargetInfo &STI) const;
 
   // getBranchTargetOpValue - Return binary encoding of the microMIPS branch

lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp

getUImm5Lsl2Encoding(const MCInst &MI, unsigned OpNo,
 
   assert(MO.isExpr() &&
          "getUImm5Lsl2Encoding expects only expressions or an immediate");
 
   return 0;
 }
 
 unsigned MipsMCCodeEmitter::
+getSImm5Addius5Value(const MCInst &MI, unsigned OpNo,
+                     SmallVectorImpl<MCFixup> &Fixups,
+                     const MCSubtargetInfo &STI) const {
+
+  const MCOperand &MO = MI.getOperand(OpNo);
+  if (MO.isImm()) return MO.getImm() & 0xf;
+
+  return 0;
+}
+
+unsigned MipsMCCodeEmitter::
 getExprOpValue(const MCExpr *Expr,SmallVectorImpl<MCFixup> &Fixups,
                const MCSubtargetInfo &STI) const {
   int64_t Res;
 
   if (Expr->EvaluateAsAbsolute(Res))
     return Res;
 
   MCExpr::ExprKind Kind = Expr->getKind();

lib/Target/Mips/MicroMipsInstrFormats.td

class MicroMipsInst16<dag outs, dag ins, string asmstr, list<dag> pattern,
   field bits<16> SoftFail = 0;
   bits<6> Opcode = 0x0;
 }
 
 //===----------------------------------------------------------------------===//
 // MicroMIPS 16-bit Instruction Formats
 //===----------------------------------------------------------------------===//
 
+class ADDIUS5_FM_MM16 {
+  bits<5> rd;
+  bits<4> imm;
+
+  bits<16> Inst;
+
+  let Inst{15-10} = 0x13;
+  let Inst{9-5}   = rd;
+  let Inst{4-1}   = imm;
+  let Inst{0}     = 0;
+}
+
 class MOVE_FM_MM16<bits<6> funct> {
   bits<5> rs;
   bits<5> rd;
 
   bits<16> Inst;
 
   let Inst{15-10} = funct;
   let Inst{9-5}   = rd;

lib/Target/Mips/MicroMipsInstrInfo.td

 def addrimm12 : ComplexPattern<iPTR, 2, "selectIntAddrMM", [frameindex]>;
 
 def simm12 : Operand<i32> {
   let DecoderMethod = "DecodeSimm12";
 }
 
 def uimm5_lsl2 : Operand<OtherVT> {
   let EncoderMethod = "getUImm5Lsl2Encoding";
 }
 
+def simm5_addius5 : Operand<i32> {
+  let EncoderMethod = "getSImm5Addius5Value";
+}
+
 def mem_mm_12 : Operand<i32> {
   let PrintMethod = "printMemOperand";
   let MIOperandInfo = (ops GPR32, simm12);
   let EncoderMethod = "getMemEncodingMMImm12";
   let ParserMatchClass = MipsMemAsmOperand;
   let OperandType = "OPERAND_MEMORY";
 }
 
class LoadMM<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
   InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
          !strconcat(opstr, "\t$rt, $addr"),
          [(set RO:$rt, (OpNode addrimm12:$addr))], Itin, FrmI> {
   let DecoderMethod = "DecodeMemMMImm12";
   let canFoldAsLoad = 1;
   let mayLoad = 1;
 }
 
+class AddImmUS5<string opstr, RegisterOperand RO> :
+  MicroMipsInst16<(outs RO:$dst), (ins RO:$rd, simm5_addius5:$imm),
+                  !strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmR> {
+  let Constraints = "$rd = $dst";
+  let isCommutable = 1;
+}
+
 class MoveFromHILOMM<string opstr, RegisterOperand RO, Register UseReg> :
       MicroMipsInst16<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"),
   [], II_MFHI_MFLO, FrmR> {
   let Uses = [UseReg];
   let hasSideEffects = 0;
 }
 
 class MoveMM16<string opstr, RegisterOperand RO, bit isComm = 0,
InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
             [], IIBranch, FrmR>;
 
   class BranchCompareToZeroLinkMM<string opstr, DAGOperand opnd,
                                   RegisterOperand RO> :
     InstSE<(outs), (ins RO:$rs, opnd:$offset),
            !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI, opstr>;
 }
 
+def ADDIUS5_MM : AddImmUS5<"addius5", GPR32Opnd>, ADDIUS5_FM_MM16;
 def MFHI16_MM : MoveFromHILOMM<"mfhi", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x10>;
 def MFLO16_MM : MoveFromHILOMM<"mflo", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x12>;
 def MOVE16_MM : MoveMM16<"move", GPR32Opnd>, MOVE_FM_MM16<0x03>;
 def JALR16_MM : JumpLinkRegMM16<"jalr", GPR32Opnd>, JALR_FM_MM16<0x0e>;
 def JALRS16_MM : JumpLinkRegSMM16<"jalrs16", GPR32Opnd>, JALR_FM_MM16<0x0f>;
 def JRC16_MM : JumpLinkRegCMM16<"jrc", GPR32Opnd>, JALR_FM_MM16<0x0d>;
 def JRADDIUSP : JumpRAddiuStackMM16, JRADDIUSP_FM_MM16<0x18>;
 

test/MC/Mips/micromips-16-bit-instructions.s

 # RUN: llvm-mc %s -triple=mipsel -show-encoding -mattr=micromips | \
 # RUN: FileCheck -check-prefix=CHECK-EL %s
 # RUN: llvm-mc %s -triple=mips -show-encoding -mattr=micromips | \
 # RUN: FileCheck -check-prefix=CHECK-EB %s
 # Check that the assembler can handle the documented syntax
 # for arithmetic and logical instructions.
 #------------------------------------------------------------------------------
 # MicroMIPS 16-bit Instructions
 #------------------------------------------------------------------------------
 # Little endian
 #------------------------------------------------------------------------------
+# CHECK-EL: addius5 $7, -2          # encoding: [0xfc,0x4c]
 # CHECK-EL: mfhi    $9              # encoding: [0x09,0x46]
 # CHECK-EL: mflo    $9              # encoding: [0x49,0x46]
 # CHECK-EL: move    $25, $1         # encoding: [0x21,0x0f]
 # CHECK-EL: jrc     $9              # encoding: [0xa9,0x45]
 # CHECK-EL: jalr    $9              # encoding: [0xc9,0x45]
 # CHECK-EL: jraddiusp 20            # encoding: [0x05,0x47]
 # CHECK-EL: nop                     # encoding: [0x00,0x00,0x00,0x00]
 # CHECK-EL: jalrs16 $9              # encoding: [0xe9,0x45]
 # CHECK-EL: move    $zero, $zero    # encoding: [0x00,0x0c]
 #------------------------------------------------------------------------------
 # Big endian
 #------------------------------------------------------------------------------
+# CHECK-EB: addius5 $7, -2          # encoding: [0x4c,0xfc]
 # CHECK-EB: mfhi    $9              # encoding: [0x46,0x09]
 # CHECK-EB: mflo    $9              # encoding: [0x46,0x49]
 # CHECK-EB: move    $25, $1         # encoding: [0x0f,0x21]
 # CHECK-EB: jrc     $9              # encoding: [0x45,0xa9]
 # CHECK-EB: jalr    $9              # encoding: [0x45,0xc9]
 # CHECK-EB: jraddiusp 20            # encoding: [0x47,0x05]
 # CHECK-EB: nop                     # encoding: [0x00,0x00,0x00,0x00]
 # CHECK-EB: jalrs16 $9              # encoding: [0x45,0xe9]
 # CHECK-EB: move    $zero, $zero    # encoding: [0x0c,0x00]
 
+    addius5 $7, -2
     mfhi    $9
     mflo    $9
     move    $25, $1
     jrc     $9
     jalr    $9
     jraddiusp 20
     jalrs16 $9