[llvm-exegesis] Renaming classes and functions.

[gchatelet]

Summary

Functional No Op.

[gchatelet]

• Removing leftover and fixing some documentation.

[gchatelet]

Rebase on master.

[yubing]

llvm/trunk/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp

221

Hi, gchatelet:

I just wonder how to run this testcase. Could you please give us some help?

Thanks

[gchatelet]

llvm/trunk/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp

221

Sure, the target you want to use is unittests/tools/llvm-exegesis/X86/all
Here is the full cmd line I'm using

> cmake -DCMAKE_BUILD_TYPE=Debug -DLLVM_BUILD_TESTS=ON -DBUILD_SHARED_LIBS=ON -DLLVM_USE_SPLIT_DWARF=ON -DLLVM_OPTIMIZED_TABLEGEN=ON -DLLVM_ENABLE_WERROR=ON -H/redacted/git/llvm-project/llvm -B/tmp/llvm-project_dbg_compiled-with-clang -GNinja
> ninja -C /tmp/llvm-project_dbg_compiled-with-clang unittests/tools/llvm-exegesis/X86/all
> /tmp/llvm-project_dbg_compiled-with-clang/unittests/tools/llvm-exegesis/X86/LLVMExegesisX86Tests

[yubing]

llvm/trunk/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp

221

Hi, gachatelet.
Thanks for your answers.
I got some trouble when run this test TEST_F(UopsBenchmarkRunnerTest, MemoryUse) :

Expected: has substring "no tied variables"
  Actual: "instruction is parallel, repeating a random one."

Could you please explain the meaning of the errorlog shown above?

[yubing]

llvm/trunk/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp

221

When I debugged with gdb, I found that MOV32rm's AllDefRegs and AllUseRegs has no common elements which lead to this testfail
But I still don't know AllDefRegs and AllUseRegs's real meaning.

[gchatelet]

llvm/trunk/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp

221

@yubing would you mind opening a bug on buganizer instead? I feel like the patch review is not the right place to debug your issue.
Also, are you sure the code is up to date?
If I open llvm/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp I can't find TEST_F(UopsBenchmarkRunnerTest, MemoryUse) but TEST_F(UopsSnippetGeneratorTest, MemoryUse).

It seems like you're using an old version of the code.

llvm/trunk/tools/llvm-exegesis/lib/BenchmarkRunner.h

 // A class representing failures that happened during Benchmark, they are used
 // to report informations to the user.
 class BenchmarkFailure : public llvm::StringError {
 public:
   BenchmarkFailure(const llvm::Twine &S);
 };
 
 // A collection of instructions that are to be assembled, executed and measured.
-struct BenchmarkConfiguration {
-  // This code is run before the Snippet is iterated. Since it is part of the
-  // measurement it should be as short as possible. It is usually used to setup
-  // the content of the Registers.
-  struct Setup {
-    std::vector<unsigned> LiveIns; // The registers that are live on entry.
-    std::vector<unsigned> RegsToDef;
-  };
-  Setup SnippetSetup;
+struct BenchmarkCode {
+  // The sequence of instructions that are to be repeated.
+  std::vector<llvm::MCInst> Instructions;
+
+  // Before the code is executed some instructions are added to setup the
+  // registers initial values.
 
-  // The sequence of instructions that are to be repeated.
-  std::vector<llvm::MCInst> Snippet;
+  // We also need to provide the registers that are live on entry for the
+  // assembler to generate proper prologue/epilogue.
+  std::vector<unsigned> LiveIns;
 
   // Informations about how this configuration was built.
   std::string Info;
 };
 
 // Common code for all benchmark modes.
 class BenchmarkRunner {
 public:
private:
     const std::unique_ptr<char[]> UnalignedPtr;
     char *const AlignedPtr;
   };
 
 protected:
   const LLVMState &State;
   const RegisterAliasingTrackerCache RATC;
 
-  // Generates a single instruction prototype that has a self-dependency.
-  llvm::Expected<SnippetPrototype>
-  generateSelfAliasingPrototype(const Instruction &Instr) const;
-  // Generates a single instruction prototype without assignment constraints.
-  llvm::Expected<SnippetPrototype>
-  generateUnconstrainedPrototype(const Instruction &Instr,
+  // Generates a single code template that has a self-dependency.
+  llvm::Expected<CodeTemplate>
+  generateSelfAliasingCodeTemplate(const Instruction &Instr) const;
+  // Generates a single code template without assignment constraints.
+  llvm::Expected<CodeTemplate>
+  generateUnconstrainedCodeTemplate(const Instruction &Instr,
                                     llvm::StringRef Msg) const;
 
 private:
   // API to be implemented by subclasses.
-  virtual llvm::Expected<SnippetPrototype>
-  generatePrototype(unsigned Opcode) const = 0;
+  virtual llvm::Expected<CodeTemplate>
+  generateCodeTemplate(unsigned Opcode) const = 0;
 
   virtual std::vector<BenchmarkMeasure>
   runMeasurements(const ExecutableFunction &EF, ScratchSpace &Scratch,
                   const unsigned NumRepetitions) const = 0;
 
   // Internal helpers.
-  InstructionBenchmark runOne(const BenchmarkConfiguration &Configuration,
-                              unsigned Opcode, unsigned NumRepetitions) const;
+  InstructionBenchmark runConfiguration(const BenchmarkCode &Configuration,
+                                        unsigned Opcode,
+                                        unsigned NumRepetitions) const;
 
-  // Calls generatePrototype and expands the SnippetPrototype into one or more
-  // BenchmarkConfiguration.
-  llvm::Expected<std::vector<BenchmarkConfiguration>>
+  // Calls generateCodeTemplate and expands it into one or more BenchmarkCode.
+  llvm::Expected<std::vector<BenchmarkCode>>
   generateConfigurations(unsigned Opcode) const;
 
   llvm::Expected<std::string>
-  writeObjectFile(const BenchmarkConfiguration::Setup &Setup,
+  writeObjectFile(const BenchmarkCode &Configuration,
                   llvm::ArrayRef<llvm::MCInst> Code) const;
 
   const InstructionBenchmark::ModeE Mode;
 
   const std::unique_ptr<ScratchSpace> Scratch;
 };
 
 } // namespace exegesis
 
 #endif // LLVM_TOOLS_LLVM_EXEGESIS_BENCHMARKRUNNER_H

llvm/trunk/tools/llvm-exegesis/lib/BenchmarkRunner.cpp

if (InstrDesc.isPseudo())
     return llvm::make_error<BenchmarkFailure>("Unsupported opcode: isPseudo");
   if (InstrDesc.isBranch() || InstrDesc.isIndirectBranch())
     return llvm::make_error<BenchmarkFailure>(
         "Unsupported opcode: isBranch/isIndirectBranch");
   if (InstrDesc.isCall() || InstrDesc.isReturn())
     return llvm::make_error<BenchmarkFailure>(
         "Unsupported opcode: isCall/isReturn");
 
-  llvm::Expected<std::vector<BenchmarkConfiguration>> ConfigurationOrError =
+  llvm::Expected<std::vector<BenchmarkCode>> ConfigurationOrError =
       generateConfigurations(Opcode);
 
   if (llvm::Error E = ConfigurationOrError.takeError())
     return std::move(E);
 
   std::vector<InstructionBenchmark> InstrBenchmarks;
-  for (const BenchmarkConfiguration &Conf : ConfigurationOrError.get())
-    InstrBenchmarks.push_back(runOne(Conf, Opcode, NumRepetitions));
+  for (const BenchmarkCode &Conf : ConfigurationOrError.get())
+    InstrBenchmarks.push_back(runConfiguration(Conf, Opcode, NumRepetitions));
   return InstrBenchmarks;
 }
 
+// Repeat the snippet until there are at least NumInstructions in the resulting
+// code.
+static std::vector<llvm::MCInst>
+GenerateInstructions(const BenchmarkCode &BC, const int MinInstructions) {
+  std::vector<llvm::MCInst> Code = BC.Instructions;
+  for (int I = 0; I < MinInstructions; ++I)
+    Code.push_back(BC.Instructions[I % BC.Instructions.size()]);
+  return Code;
+}
+
 InstructionBenchmark
-BenchmarkRunner::runOne(const BenchmarkConfiguration &Configuration,
-                        unsigned Opcode, unsigned NumRepetitions) const {
+BenchmarkRunner::runConfiguration(const BenchmarkCode &BC, unsigned Opcode,
+                                  unsigned NumRepetitions) const {
   InstructionBenchmark InstrBenchmark;
   InstrBenchmark.Mode = Mode;
   InstrBenchmark.CpuName = State.getTargetMachine().getTargetCPU();
   InstrBenchmark.LLVMTriple =
       State.getTargetMachine().getTargetTriple().normalize();
   InstrBenchmark.NumRepetitions = NumRepetitions;
-  InstrBenchmark.Info = Configuration.Info;
+  InstrBenchmark.Info = BC.Info;
 
-  const std::vector<llvm::MCInst> &Snippet = Configuration.Snippet;
-  if (Snippet.empty()) {
+  const std::vector<llvm::MCInst> &Instructions = BC.Instructions;
+  if (Instructions.empty()) {
     InstrBenchmark.Error = "Empty snippet";
     return InstrBenchmark;
   }
 
-  InstrBenchmark.Key.Instructions = Snippet;
-
-  // Repeat the snippet until there are at least NumInstructions in the
-  // resulting code. The snippet is always repeated at least once.
-  const auto GenerateInstructions = [&Configuration](
-                                        const int MinInstructions) {
-    std::vector<llvm::MCInst> Code = Configuration.Snippet;
-    for (int I = 0; I < MinInstructions; ++I)
-      Code.push_back(Configuration.Snippet[I % Configuration.Snippet.size()]);
-    return Code;
-  };
+  InstrBenchmark.Key.Instructions = Instructions;
 
   // Assemble at least kMinInstructionsForSnippet instructions by repeating the
   // snippet for debug/analysis. This is so that the user clearly understands
   // that the inside instructions are repeated.
   constexpr const int kMinInstructionsForSnippet = 16;
   {
-    auto ObjectFilePath =
-        writeObjectFile(Configuration.SnippetSetup,
-                        GenerateInstructions(kMinInstructionsForSnippet));
+    auto ObjectFilePath = writeObjectFile(
+        BC, GenerateInstructions(BC, kMinInstructionsForSnippet));
     if (llvm::Error E = ObjectFilePath.takeError()) {
       InstrBenchmark.Error = llvm::toString(std::move(E));
       return InstrBenchmark;
     }
     const ExecutableFunction EF(State.createTargetMachine(),
                                 getObjectFromFile(*ObjectFilePath));
     const auto FnBytes = EF.getFunctionBytes();
     InstrBenchmark.AssembledSnippet.assign(FnBytes.begin(), FnBytes.end());
   }
 
   // Assemble NumRepetitions instructions repetitions of the snippet for
   // measurements.
-  auto ObjectFilePath =
-      writeObjectFile(Configuration.SnippetSetup,
-                      GenerateInstructions(InstrBenchmark.NumRepetitions));
+  auto ObjectFilePath = writeObjectFile(
+      BC, GenerateInstructions(BC, InstrBenchmark.NumRepetitions));
   if (llvm::Error E = ObjectFilePath.takeError()) {
     InstrBenchmark.Error = llvm::toString(std::move(E));
     return InstrBenchmark;
   }
   llvm::outs() << "Check generated assembly with: /usr/bin/objdump -d "
                << *ObjectFilePath << "\n";
   const ExecutableFunction EF(State.createTargetMachine(),
                               getObjectFromFile(*ObjectFilePath));
   InstrBenchmark.Measurements = runMeasurements(EF, *Scratch, NumRepetitions);
 
   return InstrBenchmark;
 }
 
-llvm::Expected<std::vector<BenchmarkConfiguration>>
+llvm::Expected<std::vector<BenchmarkCode>>
 BenchmarkRunner::generateConfigurations(unsigned Opcode) const {
-  if (auto E = generatePrototype(Opcode)) {
-    SnippetPrototype &Prototype = E.get();
-    // TODO: Generate as many configurations as needed here.
-    BenchmarkConfiguration Configuration;
-    Configuration.Info = Prototype.Explanation;
-    for (InstructionBuilder &IB : Prototype.Snippet) {
+  if (auto E = generateCodeTemplate(Opcode)) {
+    CodeTemplate &CT = E.get();
+    std::vector<BenchmarkCode> Output;
+    // TODO: Generate as many BenchmarkCode as needed.
+    {
+      BenchmarkCode BC;
+      BC.Info = CT.Info;
+      for (InstructionBuilder &IB : CT.Instructions) {
         IB.randomizeUnsetVariables(
-          Prototype.ScratchSpaceReg
-              ? RATC.getRegister(Prototype.ScratchSpaceReg).aliasedBits()
+            CT.ScratchSpacePointerInReg
+                ? RATC.getRegister(CT.ScratchSpacePointerInReg).aliasedBits()
                 : RATC.emptyRegisters());
-      Configuration.Snippet.push_back(IB.build());
+        BC.Instructions.push_back(IB.build());
+      }
+      if (CT.ScratchSpacePointerInReg)
+        BC.LiveIns.push_back(CT.ScratchSpacePointerInReg);
+      BC.RegsToDef = computeRegsToDef(CT.Instructions);
+      Output.push_back(std::move(BC));
     }
-    if (Prototype.ScratchSpaceReg)
-      Configuration.SnippetSetup.LiveIns.push_back(Prototype.ScratchSpaceReg);
-    Configuration.SnippetSetup.RegsToDef = computeRegsToDef(Prototype.Snippet);
-    return std::vector<BenchmarkConfiguration>{Configuration};
+    return Output;
   } else
     return E.takeError();
 }
 
 std::vector<unsigned> BenchmarkRunner::computeRegsToDef(
-    const std::vector<InstructionBuilder> &Snippet) const {
+    const std::vector<InstructionBuilder> &Instructions) const {
   // Collect all register uses and create an assignment for each of them.
   // Ignore memory operands which are handled separately.
   // Loop invariant: DefinedRegs[i] is true iif it has been set at least once
   // before the current instruction.
   llvm::BitVector DefinedRegs = RATC.emptyRegisters();
   std::vector<unsigned> RegsToDef;
-  for (const InstructionBuilder &IB : Snippet) {
+  for (const InstructionBuilder &IB : Instructions) {
     // Returns the register that this Operand sets or uses, or 0 if this is not
     // a register.
     const auto GetOpReg = [&IB](const Operand &Op) -> unsigned {
       if (Op.IsMem)
         return 0;
       if (Op.ImplicitReg)
         return *Op.ImplicitReg;
       if (Op.IsExplicit && IB.getValueFor(Op).isReg())
for (const Operand &Op : IB.Instr.Operands) {
           DefinedRegs.set(Reg);
       }
     }
   }
   return RegsToDef;
 }
 
 llvm::Expected<std::string>
-BenchmarkRunner::writeObjectFile(const BenchmarkConfiguration::Setup &Setup,
+BenchmarkRunner::writeObjectFile(const BenchmarkCode &BC,
                                  llvm::ArrayRef<llvm::MCInst> Code) const {
   int ResultFD = 0;
   llvm::SmallString<256> ResultPath;
   if (llvm::Error E = llvm::errorCodeToError(llvm::sys::fs::createTemporaryFile(
           "snippet", "o", ResultFD, ResultPath)))
     return std::move(E);
   llvm::raw_fd_ostream OFS(ResultFD, true /*ShouldClose*/);
   assembleToStream(State.getExegesisTarget(), State.createTargetMachine(),
-                   Setup.LiveIns, Setup.RegsToDef, Code, OFS);
+                   BC.LiveIns, BC.RegsToDef, Code, OFS);
   return ResultPath.str();
 }
 
-llvm::Expected<SnippetPrototype>
-BenchmarkRunner::generateSelfAliasingPrototype(const Instruction &Instr) const {
+llvm::Expected<CodeTemplate> BenchmarkRunner::generateSelfAliasingCodeTemplate(
+    const Instruction &Instr) const {
   const AliasingConfigurations SelfAliasing(Instr, Instr);
   if (SelfAliasing.empty()) {
     return llvm::make_error<BenchmarkFailure>("empty self aliasing");
   }
-  SnippetPrototype Prototype;
+  CodeTemplate CT;
   InstructionBuilder IB(Instr);
   if (SelfAliasing.hasImplicitAliasing()) {
-    Prototype.Explanation = "implicit Self cycles, picking random values.";
+    CT.Info = "implicit Self cycles, picking random values.";
   } else {
-    Prototype.Explanation =
-        "explicit self cycles, selecting one aliasing Conf.";
+    CT.Info = "explicit self cycles, selecting one aliasing Conf.";
     // This is a self aliasing instruction so defs and uses are from the same
     // instance, hence twice IB in the following call.
     setRandomAliasing(SelfAliasing, IB, IB);
   }
-  Prototype.Snippet.push_back(std::move(IB));
-  return std::move(Prototype);
+  CT.Instructions.push_back(std::move(IB));
+  return std::move(CT);
 }
 
-llvm::Expected<SnippetPrototype>
-BenchmarkRunner::generateUnconstrainedPrototype(const Instruction &Instr,
+llvm::Expected<CodeTemplate>
+BenchmarkRunner::generateUnconstrainedCodeTemplate(const Instruction &Instr,
                                                    llvm::StringRef Msg) const {
-  SnippetPrototype Prototype;
-  Prototype.Explanation =
-      llvm::formatv("{0}, repeating an unconstrained assignment", Msg);
-  Prototype.Snippet.emplace_back(Instr);
-  return std::move(Prototype);
+  CodeTemplate CT;
+  CT.Info = llvm::formatv("{0}, repeating an unconstrained assignment", Msg);
+  CT.Instructions.emplace_back(Instr);
+  return std::move(CT);
 }
 } // namespace exegesis

llvm/trunk/tools/llvm-exegesis/lib/Latency.h

 namespace exegesis {
 
 class LatencyBenchmarkRunner : public BenchmarkRunner {
 public:
   LatencyBenchmarkRunner(const LLVMState &State)
       : BenchmarkRunner(State, InstructionBenchmark::Latency) {}
   ~LatencyBenchmarkRunner() override;
 
-  llvm::Expected<SnippetPrototype>
-  generatePrototype(unsigned Opcode) const override;
+  llvm::Expected<CodeTemplate>
+  generateCodeTemplate(unsigned Opcode) const override;
 
 private:
   llvm::Error isInfeasible(const llvm::MCInstrDesc &MCInstrDesc) const;
 
-  llvm::Expected<SnippetPrototype> generateTwoInstructionPrototype(
-      const Instruction &Instr) const;
+  llvm::Expected<CodeTemplate>
+  generateTwoInstructionPrototype(const Instruction &Instr) const;
 
   std::vector<BenchmarkMeasure>
   runMeasurements(const ExecutableFunction &EF, ScratchSpace &Scratch,
                   const unsigned NumRepetitions) const override;
 
   virtual const char *getCounterName() const;
 };
 
 } // namespace exegesis
 
 #endif // LLVM_TOOLS_LLVM_EXEGESIS_LATENCY_H

llvm/trunk/tools/llvm-exegesis/lib/Latency.cpp

if (llvm::any_of(MCInstrDesc.operands(), hasUnknownOperand))
     return llvm::make_error<BenchmarkFailure>(
         "Infeasible : has unknown operands");
   if (llvm::any_of(MCInstrDesc.operands(), hasMemoryOperand))
     return llvm::make_error<BenchmarkFailure>(
         "Infeasible : has memory operands");
   return llvm::Error::success();
 }
 
-llvm::Expected<SnippetPrototype>
+llvm::Expected<CodeTemplate>
 LatencyBenchmarkRunner::generateTwoInstructionPrototype(
     const Instruction &Instr) const {
   std::vector<unsigned> Opcodes;
   Opcodes.resize(State.getInstrInfo().getNumOpcodes());
   std::iota(Opcodes.begin(), Opcodes.end(), 0U);
   std::shuffle(Opcodes.begin(), Opcodes.end(), randomGenerator());
   for (const unsigned OtherOpcode : Opcodes) {
     if (OtherOpcode == Instr.Description->Opcode)
for (const unsigned OtherOpcode : Opcodes) {
     if (Forward.empty() || Back.empty())
       continue;
     InstructionBuilder ThisIB(Instr);
     InstructionBuilder OtherIB(OtherInstr);
     if (!Forward.hasImplicitAliasing())
       setRandomAliasing(Forward, ThisIB, OtherIB);
     if (!Back.hasImplicitAliasing())
       setRandomAliasing(Back, OtherIB, ThisIB);
-    SnippetPrototype Prototype;
-    Prototype.Explanation =
-        llvm::formatv("creating cycle through {0}.",
+    CodeTemplate CT;
+    CT.Info = llvm::formatv("creating cycle through {0}.",
                             State.getInstrInfo().getName(OtherOpcode));
-    Prototype.Snippet.push_back(std::move(ThisIB));
-    Prototype.Snippet.push_back(std::move(OtherIB));
-    return std::move(Prototype);
+    CT.Instructions.push_back(std::move(ThisIB));
+    CT.Instructions.push_back(std::move(OtherIB));
+    return std::move(CT);
   }
   return llvm::make_error<BenchmarkFailure>(
       "Infeasible : Didn't find any scheme to make the instruction serial");
 }
 
-llvm::Expected<SnippetPrototype>
-LatencyBenchmarkRunner::generatePrototype(unsigned Opcode) const {
+llvm::Expected<CodeTemplate>
+LatencyBenchmarkRunner::generateCodeTemplate(unsigned Opcode) const {
   const auto &InstrDesc = State.getInstrInfo().get(Opcode);
   if (auto E = isInfeasible(InstrDesc))
     return std::move(E);
   const Instruction Instr(InstrDesc, RATC);
-  if (auto SelfAliasingPrototype = generateSelfAliasingPrototype(Instr))
-    return SelfAliasingPrototype;
+  if (auto CT = generateSelfAliasingCodeTemplate(Instr))
+    return CT;
   else
-    llvm::consumeError(SelfAliasingPrototype.takeError());
+    llvm::consumeError(CT.takeError());
   // No self aliasing, trying to create a dependency through another opcode.
   return generateTwoInstructionPrototype(Instr);
 }
 
 const char *LatencyBenchmarkRunner::getCounterName() const {
   if (!State.getSubtargetInfo().getSchedModel().hasExtraProcessorInfo())
     llvm::report_fatal_error("sched model is missing extra processor info!");
   const char *CounterName = State.getSubtargetInfo()

llvm/trunk/tools/llvm-exegesis/lib/MCInstrDescView.h

struct Instruction {
   llvm::BitVector DefRegisters; // The union of the aliased def registers.
   llvm::BitVector UseRegisters; // The union of the aliased use registers.
 };
 
 // A builder for an Instruction holding values for each of its Variables.
 struct InstructionBuilder {
   InstructionBuilder(const Instruction &Instr);
 
-  InstructionBuilder(const InstructionBuilder &);
-  InstructionBuilder &operator=(const InstructionBuilder &);
-  InstructionBuilder(InstructionBuilder &&);
-  InstructionBuilder &operator=(InstructionBuilder &&);
+  InstructionBuilder(const InstructionBuilder &);            // default
+  InstructionBuilder &operator=(const InstructionBuilder &); // default
+  InstructionBuilder(InstructionBuilder &&);                 // default
+  InstructionBuilder &operator=(InstructionBuilder &&);      // default
 
   unsigned getOpcode() const;
   llvm::MCOperand &getValueFor(const Variable &Var);
   const llvm::MCOperand &getValueFor(const Variable &Var) const;
   llvm::MCOperand &getValueFor(const Operand &Op);
   const llvm::MCOperand &getValueFor(const Operand &Op) const;
   bool hasImmediateVariables() const;
 
   // Assigns a Random Value to all Variables that are still Invalid.
   // Do not use any of the registers in `ForbiddenRegs`.
   void randomizeUnsetVariables(const llvm::BitVector &ForbiddenRegs);
 
-  // Returns the instance as an llvm::MCInst. The InstructionBuilder must be
-  // fully allocated (no invalid variables).
+  // Builds an llvm::MCInst from this InstructionBuilder setting its operands to
+  // the corresponding variable values.
+  // Precondition: All VariableValues must be set.
   llvm::MCInst build() const;
 
   Instruction Instr;
   llvm::SmallVector<llvm::MCOperand, 4> VariableValues;
 };
 
-// A prototype is a set of InstructionInstances with an explanation of how
-// it's been built. The prototype can then be randomized to exercice several
-// immediate values. It is also used to gather the used registers and define
-// their initial values.
-struct SnippetPrototype {
-  SnippetPrototype() = default;
-
-  // No copy.
-  SnippetPrototype(const SnippetPrototype &) = delete;
-  SnippetPrototype &operator=(const SnippetPrototype &) = delete;
-
-  // Moving is OK.
-  SnippetPrototype(SnippetPrototype &&);
-  SnippetPrototype &operator=(SnippetPrototype &&);
-
-  std::string Explanation;
-  // If the prototype uses the provided scratch memory, the register in which
+// A CodeTemplate is a set of InstructionBuilders that may not be fully
+// specified (i.e. some variables are not yet set).
+// This allows the BenchmarkRunner to instantiate it many times with specific
+// values to study their impact on instruction's performance.
+struct CodeTemplate {
+  CodeTemplate() = default;
+
+  CodeTemplate(CodeTemplate &&);            // default
+  CodeTemplate &operator=(CodeTemplate &&); // default
+  CodeTemplate(const CodeTemplate &) = delete;
+  CodeTemplate &operator=(const CodeTemplate &) = delete;
+
+  // Some information about how this template has been created.
+  std::string Info;
+  // The list of the instructions for this template.
+  std::vector<InstructionBuilder> Instructions;
+  // If the template uses the provided scratch memory, the register in which
   // the pointer to this memory is passed in to the function.
-  unsigned ScratchSpaceReg = 0;
-  std::vector<InstructionBuilder> Snippet;
+  unsigned ScratchSpacePointerInReg = 0;
 };
 
 // Represents the assignment of a Register to an Operand.
 struct RegisterOperandAssignment {
   RegisterOperandAssignment(const Operand *Operand, llvm::MCPhysReg Reg)
       : Op(Operand), Reg(Reg) {}
 
   const Operand *Op; // Pointer to an Explicit Register Operand.

llvm/trunk/tools/llvm-exegesis/lib/MCInstrDescView.cpp

llvm::MCInst InstructionBuilder::build() const {
   llvm::MCInst Result;
   Result.setOpcode(Instr.Description->Opcode);
   for (const auto &Op : Instr.Operands)
     if (Op.IsExplicit)
       Result.addOperand(getValueFor(Op));
   return Result;
 }
 
-SnippetPrototype::SnippetPrototype(SnippetPrototype &&) = default;
+CodeTemplate::CodeTemplate(CodeTemplate &&) = default;
 
-SnippetPrototype &SnippetPrototype::operator=(SnippetPrototype &&) = default;
+CodeTemplate &CodeTemplate::operator=(CodeTemplate &&) = default;
 
 bool RegisterOperandAssignment::
 operator==(const RegisterOperandAssignment &Other) const {
   return std::tie(Op, Reg) == std::tie(Other.Op, Other.Reg);
 }
 
 bool AliasingRegisterOperands::
 operator==(const AliasingRegisterOperands &Other) const {

llvm/trunk/tools/llvm-exegesis/lib/Uops.h

 namespace exegesis {
 
 class UopsBenchmarkRunner : public BenchmarkRunner {
 public:
   UopsBenchmarkRunner(const LLVMState &State)
       : BenchmarkRunner(State, InstructionBenchmark::Uops) {}
   ~UopsBenchmarkRunner() override;
 
-  llvm::Expected<SnippetPrototype>
-  generatePrototype(unsigned Opcode) const override;
+  llvm::Expected<CodeTemplate>
+  generateCodeTemplate(unsigned Opcode) const override;
 
   static constexpr const size_t kMinNumDifferentAddresses = 6;
 
 private:
   llvm::Error isInfeasible(const llvm::MCInstrDesc &MCInstrDesc) const;
 
   std::vector<BenchmarkMeasure>
   runMeasurements(const ExecutableFunction &EF, ScratchSpace &Scratch,

llvm/trunk/tools/llvm-exegesis/lib/Uops.cpp

static void remove(llvm::BitVector &a, const llvm::BitVector &b) {
   assert(a.size() == b.size());
   for (auto I : b.set_bits())
     a.reset(I);
 }
 
 UopsBenchmarkRunner::~UopsBenchmarkRunner() = default;
 
 void UopsBenchmarkRunner::instantiateMemoryOperands(
-    const unsigned ScratchSpaceReg,
-    std::vector<InstructionBuilder> &Snippet) const {
-  if (ScratchSpaceReg == 0)
+    const unsigned ScratchSpacePointerInReg,
+    std::vector<InstructionBuilder> &Instructions) const {
+  if (ScratchSpacePointerInReg == 0)
     return; // no memory operands.
   const auto &ET = State.getExegesisTarget();
   const unsigned MemStep = ET.getMaxMemoryAccessSize();
-  const size_t OriginalSnippetSize = Snippet.size();
+  const size_t OriginalInstructionsSize = Instructions.size();
   size_t I = 0;
-  for (InstructionBuilder &IB : Snippet) {
-    ET.fillMemoryOperands(IB, ScratchSpaceReg, I * MemStep);
+  for (InstructionBuilder &IB : Instructions) {
+    ET.fillMemoryOperands(IB, ScratchSpacePointerInReg, I * MemStep);
     ++I;
   }
 
-  while (Snippet.size() < kMinNumDifferentAddresses) {
-    InstructionBuilder IB = Snippet[I % OriginalSnippetSize];
-    ET.fillMemoryOperands(IB, ScratchSpaceReg, I * MemStep);
+  while (Instructions.size() < kMinNumDifferentAddresses) {
+    InstructionBuilder IB = Instructions[I % OriginalInstructionsSize];
+    ET.fillMemoryOperands(IB, ScratchSpacePointerInReg, I * MemStep);
     ++I;
-    Snippet.push_back(std::move(IB));
+    Instructions.push_back(std::move(IB));
   }
   assert(I * MemStep < ScratchSpace::kSize && "not enough scratch space");
 }
 
-llvm::Expected<SnippetPrototype>
-UopsBenchmarkRunner::generatePrototype(unsigned Opcode) const {
+llvm::Expected<CodeTemplate>
+UopsBenchmarkRunner::generateCodeTemplate(unsigned Opcode) const {
   const auto &InstrDesc = State.getInstrInfo().get(Opcode);
   if (auto E = isInfeasible(InstrDesc))
     return std::move(E);
   const Instruction Instr(InstrDesc, RATC);
   const auto &ET = State.getExegesisTarget();
-  SnippetPrototype Prototype;
+  CodeTemplate CT;
 
   const llvm::BitVector *ScratchSpaceAliasedRegs = nullptr;
   if (Instr.hasMemoryOperands()) {
-    Prototype.ScratchSpaceReg =
+    CT.ScratchSpacePointerInReg =
         ET.getScratchMemoryRegister(State.getTargetMachine().getTargetTriple());
-    if (Prototype.ScratchSpaceReg == 0)
+    if (CT.ScratchSpacePointerInReg == 0)
       return llvm::make_error<BenchmarkFailure>(
           "Infeasible : target does not support memory instructions");
     ScratchSpaceAliasedRegs =
-        &RATC.getRegister(Prototype.ScratchSpaceReg).aliasedBits();
-    // If the instruction implicitly writes to ScratchSpaceReg , abort.
+        &RATC.getRegister(CT.ScratchSpacePointerInReg).aliasedBits();
+    // If the instruction implicitly writes to ScratchSpacePointerInReg , abort.
     // FIXME: We could make a copy of the scratch register.
     for (const auto &Op : Instr.Operands) {
       if (Op.IsDef && Op.ImplicitReg &&
           ScratchSpaceAliasedRegs->test(*Op.ImplicitReg))
         return llvm::make_error<BenchmarkFailure>(
             "Infeasible : memory instruction uses scratch memory register");
     }
   }
 
   const AliasingConfigurations SelfAliasing(Instr, Instr);
   InstructionBuilder IB(Instr);
   if (SelfAliasing.empty()) {
-    Prototype.Explanation = "instruction is parallel, repeating a random one.";
-    Prototype.Snippet.push_back(std::move(IB));
-    instantiateMemoryOperands(Prototype.ScratchSpaceReg, Prototype.Snippet);
-    return std::move(Prototype);
+    CT.Info = "instruction is parallel, repeating a random one.";
+    CT.Instructions.push_back(std::move(IB));
+    instantiateMemoryOperands(CT.ScratchSpacePointerInReg, CT.Instructions);
+    return std::move(CT);
   }
   if (SelfAliasing.hasImplicitAliasing()) {
-    Prototype.Explanation = "instruction is serial, repeating a random one.";
-    Prototype.Snippet.push_back(std::move(IB));
-    instantiateMemoryOperands(Prototype.ScratchSpaceReg, Prototype.Snippet);
-    return std::move(Prototype);
+    CT.Info = "instruction is serial, repeating a random one.";
+    CT.Instructions.push_back(std::move(IB));
+    instantiateMemoryOperands(CT.ScratchSpacePointerInReg, CT.Instructions);
+    return std::move(CT);
   }
   const auto TiedVariables = getTiedVariables(Instr);
   if (!TiedVariables.empty()) {
     if (TiedVariables.size() > 1)
       return llvm::make_error<llvm::StringError>(
           "Infeasible : don't know how to handle several tied variables",
           llvm::inconvertibleErrorCode());
     const Variable *Var = TiedVariables.front();
     assert(Var);
     assert(!Var->TiedOperands.empty());
     const Operand &Op = Instr.Operands[Var->TiedOperands.front()];
     assert(Op.Tracker);
-    Prototype.Explanation =
-        "instruction has tied variables using static renaming.";
+    CT.Info = "instruction has tied variables using static renaming.";
     for (const llvm::MCPhysReg Reg : Op.Tracker->sourceBits().set_bits()) {
       if (ScratchSpaceAliasedRegs && ScratchSpaceAliasedRegs->test(Reg))
         continue; // Do not use the scratch memory address register.
       InstructionBuilder TmpIB = IB;
       TmpIB.getValueFor(*Var) = llvm::MCOperand::createReg(Reg);
-      Prototype.Snippet.push_back(std::move(TmpIB));
+      CT.Instructions.push_back(std::move(TmpIB));
     }
-    instantiateMemoryOperands(Prototype.ScratchSpaceReg, Prototype.Snippet);
-    return std::move(Prototype);
+    instantiateMemoryOperands(CT.ScratchSpacePointerInReg, CT.Instructions);
+    return std::move(CT);
   }
   // No tied variables, we pick random values for defs.
   llvm::BitVector Defs(State.getRegInfo().getNumRegs());
   for (const auto &Op : Instr.Operands) {
     if (Op.Tracker && Op.IsExplicit && Op.IsDef && !Op.IsMem) {
       auto PossibleRegisters = Op.Tracker->sourceBits();
       remove(PossibleRegisters, RATC.reservedRegisters());
       // Do not use the scratch memory address register.
if (Op.Tracker && Op.IsExplicit && !Op.IsDef && !Op.IsMem) {
       if (ScratchSpaceAliasedRegs)
         remove(PossibleRegisters, *ScratchSpaceAliasedRegs);
       remove(PossibleRegisters, DefAliases);
       assert(PossibleRegisters.any() && "No register left to choose from");
       const auto RandomReg = randomBit(PossibleRegisters);
       IB.getValueFor(Op) = llvm::MCOperand::createReg(RandomReg);
     }
   }
-  Prototype.Explanation =
+  CT.Info =
       "instruction has no tied variables picking Uses different from defs";
-  Prototype.Snippet.push_back(std::move(IB));
-  instantiateMemoryOperands(Prototype.ScratchSpaceReg, Prototype.Snippet);
-  return std::move(Prototype);
+  CT.Instructions.push_back(std::move(IB));
+  instantiateMemoryOperands(CT.ScratchSpacePointerInReg, CT.Instructions);
+  return std::move(CT);
 }
 
 std::vector<BenchmarkMeasure>
 UopsBenchmarkRunner::runMeasurements(const ExecutableFunction &Function,
                                      ScratchSpace &Scratch,
                                      const unsigned NumRepetitions) const {
   const auto &SchedModel = State.getSubtargetInfo().getSchedModel();
 

llvm/trunk/tools/llvm-exegesis/lib/X86/Target.cpp

 namespace exegesis {
 
 namespace {
 
 // Common code for X86 Uops and Latency runners.
 template <typename Impl> class X86BenchmarkRunner : public Impl {
   using Impl::Impl;
 
-  llvm::Expected<SnippetPrototype>
-  generatePrototype(unsigned Opcode) const override {
+  llvm::Expected<CodeTemplate>
+  generateCodeTemplate(unsigned Opcode) const override {
     // Test whether we can generate a snippet for this instruction.
     const auto &InstrInfo = this->State.getInstrInfo();
     const auto OpcodeName = InstrInfo.getName(Opcode);
     if (OpcodeName.startswith("POPF") || OpcodeName.startswith("PUSHF") ||
         OpcodeName.startswith("ADJCALLSTACK")) {
       return llvm::make_error<BenchmarkFailure>(
           "Unsupported opcode: Push/Pop/AdjCallStack");
     }
case llvm::X86II::OneArgFP:
       return llvm::make_error<BenchmarkFailure>("Unsupported x87 OneArgFP");
     case llvm::X86II::OneArgFPRW:
     case llvm::X86II::TwoArgFP: {
       // These are instructions like
       //   - `ST(0) = fsqrt(ST(0))` (OneArgFPRW)
       //   - `ST(0) = ST(0) + ST(i)` (TwoArgFP)
       // They are intrinsically serial and do not modify the state of the stack.
       // We generate the same code for latency and uops.
-      return this->generateSelfAliasingPrototype(Instr);
+      return this->generateSelfAliasingCodeTemplate(Instr);
     }
     case llvm::X86II::CompareFP:
       return Impl::handleCompareFP(Instr);
     case llvm::X86II::CondMovFP:
       return Impl::handleCondMovFP(Instr);
     case llvm::X86II::SpecialFP:
       return llvm::make_error<BenchmarkFailure>("Unsupported x87 SpecialFP");
     default:
       llvm_unreachable("Unknown FP Type!");
     }
 
     // Fallback to generic implementation.
-    return Impl::Base::generatePrototype(Opcode);
+    return Impl::Base::generateCodeTemplate(Opcode);
   }
 };
 
 class X86LatencyImpl : public LatencyBenchmarkRunner {
 protected:
   using Base = LatencyBenchmarkRunner;
   using Base::Base;
-  llvm::Expected<SnippetPrototype>
-  handleCompareFP(const Instruction &Instr) const {
+  llvm::Expected<CodeTemplate> handleCompareFP(const Instruction &Instr) const {
     return llvm::make_error<BenchmarkFailure>("Unsupported x87 CompareFP");
   }
-  llvm::Expected<SnippetPrototype>
-  handleCondMovFP(const Instruction &Instr) const {
+  llvm::Expected<CodeTemplate> handleCondMovFP(const Instruction &Instr) const {
     return llvm::make_error<BenchmarkFailure>("Unsupported x87 CondMovFP");
   }
 };
 
 class X86UopsImpl : public UopsBenchmarkRunner {
 protected:
   using Base = UopsBenchmarkRunner;
   using Base::Base;
   // We can compute uops for any FP instruction that does not grow or shrink the
   // stack (either do not touch the stack or push as much as they pop).
-  llvm::Expected<SnippetPrototype>
-  handleCompareFP(const Instruction &Instr) const {
-    return generateUnconstrainedPrototype(
+  llvm::Expected<CodeTemplate> handleCompareFP(const Instruction &Instr) const {
+    return generateUnconstrainedCodeTemplate(
         Instr, "instruction does not grow/shrink the FP stack");
   }
-  llvm::Expected<SnippetPrototype>
-  handleCondMovFP(const Instruction &Instr) const {
-    return generateUnconstrainedPrototype(
+  llvm::Expected<CodeTemplate> handleCondMovFP(const Instruction &Instr) const {
+    return generateUnconstrainedCodeTemplate(
         Instr, "instruction does not grow/shrink the FP stack");
   }
 };
 
 class ExegesisX86Target : public ExegesisTarget {
   void addTargetSpecificPasses(llvm::PassManagerBase &PM) const override {
     // Lowers FP pseudo-instructions, e.g. ABS_Fp32 -> ABS_F.
     PM.add(llvm::createX86FloatingPointStackifierPass());

llvm/trunk/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp

protected:
   const llvm::MCRegisterInfo &MCRegisterInfo;
 };
 
 template <typename BenchmarkRunner>
 class SnippetGeneratorTest : public X86SnippetGeneratorTest {
 protected:
   SnippetGeneratorTest() : Runner(State) {}
 
-  SnippetPrototype checkAndGetConfigurations(unsigned Opcode) {
+  CodeTemplate checkAndGetCodeTemplate(unsigned Opcode) {
     randomGenerator().seed(0); // Initialize seed.
-    auto ProtoOrError = Runner.generatePrototype(Opcode);
-    EXPECT_FALSE(ProtoOrError.takeError()); // Valid configuration.
-    return std::move(ProtoOrError.get());
+    auto CodeTemplateOrError = Runner.generateCodeTemplate(Opcode);
+    EXPECT_FALSE(CodeTemplateOrError.takeError()); // Valid configuration.
+    return std::move(CodeTemplateOrError.get());
   }
 
   BenchmarkRunner Runner;
 };
 
-using LatencySnippetGeneratorTest =
-    SnippetGeneratorTest<LatencyBenchmarkRunner>;
+using LatencyBenchmarkRunnerTest = SnippetGeneratorTest<LatencyBenchmarkRunner>;
 
-using UopsSnippetGeneratorTest = SnippetGeneratorTest<UopsBenchmarkRunner>;
+using UopsBenchmarkRunnerTest = SnippetGeneratorTest<UopsBenchmarkRunner>;
 
-TEST_F(LatencySnippetGeneratorTest, ImplicitSelfDependency) {
+TEST_F(LatencyBenchmarkRunnerTest, ImplicitSelfDependency) {
   // ADC16i16 self alias because of implicit use and def.
 
   // explicit use 0       : imm
   // implicit def         : AX
   // implicit def         : EFLAGS
   // implicit use         : AX
   // implicit use         : EFLAGS
   const unsigned Opcode = llvm::X86::ADC16i16;
   EXPECT_THAT(MCInstrInfo.get(Opcode).getImplicitDefs()[0], llvm::X86::AX);
   EXPECT_THAT(MCInstrInfo.get(Opcode).getImplicitDefs()[1], llvm::X86::EFLAGS);
   EXPECT_THAT(MCInstrInfo.get(Opcode).getImplicitUses()[0], llvm::X86::AX);
   EXPECT_THAT(MCInstrInfo.get(Opcode).getImplicitUses()[1], llvm::X86::EFLAGS);
-  const SnippetPrototype Proto = checkAndGetConfigurations(Opcode);
-  EXPECT_THAT(Proto.Explanation, HasSubstr("implicit"));
-  ASSERT_THAT(Proto.Snippet, SizeIs(1));
-  const InstructionBuilder &IB = Proto.Snippet[0];
+  const CodeTemplate CT = checkAndGetCodeTemplate(Opcode);
+  EXPECT_THAT(CT.Info, HasSubstr("implicit"));
+  ASSERT_THAT(CT.Instructions, SizeIs(1));
+  const InstructionBuilder &IB = CT.Instructions[0];
   EXPECT_THAT(IB.getOpcode(), Opcode);
   ASSERT_THAT(IB.VariableValues, SizeIs(1)); // Imm.
   EXPECT_THAT(IB.VariableValues[0], IsInvalid()) << "Immediate is not set";
 }
 
-TEST_F(LatencySnippetGeneratorTest, ExplicitSelfDependency) {
+TEST_F(LatencyBenchmarkRunnerTest, ExplicitSelfDependency) {
   // ADD16ri self alias because Op0 and Op1 are tied together.
 
   // explicit def 0       : reg RegClass=GR16
   // explicit use 1       : reg RegClass=GR16 | TIED_TO:0
   // explicit use 2       : imm
   // implicit def         : EFLAGS
   const unsigned Opcode = llvm::X86::ADD16ri;
   EXPECT_THAT(MCInstrInfo.get(Opcode).getImplicitDefs()[0], llvm::X86::EFLAGS);
-  const SnippetPrototype Proto = checkAndGetConfigurations(Opcode);
-  EXPECT_THAT(Proto.Explanation, HasSubstr("explicit"));
-  ASSERT_THAT(Proto.Snippet, SizeIs(1));
-  const InstructionBuilder &IB = Proto.Snippet[0];
+  const CodeTemplate CT = checkAndGetCodeTemplate(Opcode);
+  EXPECT_THAT(CT.Info, HasSubstr("explicit"));
+  ASSERT_THAT(CT.Instructions, SizeIs(1));
+  const InstructionBuilder &IB = CT.Instructions[0];
   EXPECT_THAT(IB.getOpcode(), Opcode);
   ASSERT_THAT(IB.VariableValues, SizeIs(2));
   EXPECT_THAT(IB.VariableValues[0], IsReg()) << "Operand 0 and 1";
   EXPECT_THAT(IB.VariableValues[1], IsInvalid()) << "Operand 2 is not set";
 }
 
-TEST_F(LatencySnippetGeneratorTest, DependencyThroughOtherOpcode) {
+TEST_F(LatencyBenchmarkRunnerTest, DependencyThroughOtherOpcode) {
   // CMP64rr
   // explicit use 0       : reg RegClass=GR64
   // explicit use 1       : reg RegClass=GR64
   // implicit def         : EFLAGS
 
   const unsigned Opcode = llvm::X86::CMP64rr;
-  const SnippetPrototype Proto = checkAndGetConfigurations(Opcode);
-  EXPECT_THAT(Proto.Explanation, HasSubstr("cycle through"));
-  ASSERT_THAT(Proto.Snippet, SizeIs(2));
-  const InstructionBuilder &IB = Proto.Snippet[0];
+  const CodeTemplate CT = checkAndGetCodeTemplate(Opcode);
+  EXPECT_THAT(CT.Info, HasSubstr("cycle through"));
+  ASSERT_THAT(CT.Instructions, SizeIs(2));
+  const InstructionBuilder &IB = CT.Instructions[0];
   EXPECT_THAT(IB.getOpcode(), Opcode);
   ASSERT_THAT(IB.VariableValues, SizeIs(2));
   EXPECT_THAT(IB.VariableValues, AnyOf(ElementsAre(IsReg(), IsInvalid()),
                                        ElementsAre(IsInvalid(), IsReg())));
-  EXPECT_THAT(Proto.Snippet[1].getOpcode(), Not(Opcode));
+  EXPECT_THAT(CT.Instructions[1].getOpcode(), Not(Opcode));
   // TODO: check that the two instructions alias each other.
 }
 
-TEST_F(LatencySnippetGeneratorTest, LAHF) {
+TEST_F(LatencyBenchmarkRunnerTest, LAHF) {
   const unsigned Opcode = llvm::X86::LAHF;
-  const SnippetPrototype Proto = checkAndGetConfigurations(Opcode);
-  EXPECT_THAT(Proto.Explanation, HasSubstr("cycle through"));
-  ASSERT_THAT(Proto.Snippet, SizeIs(2));
-  const InstructionBuilder &IB = Proto.Snippet[0];
+  const CodeTemplate CT = checkAndGetCodeTemplate(Opcode);
+  EXPECT_THAT(CT.Info, HasSubstr("cycle through"));
+  ASSERT_THAT(CT.Instructions, SizeIs(2));
+  const InstructionBuilder &IB = CT.Instructions[0];
   EXPECT_THAT(IB.getOpcode(), Opcode);
   ASSERT_THAT(IB.VariableValues, SizeIs(0));
 }
 
-TEST_F(UopsSnippetGeneratorTest, ParallelInstruction) {
+TEST_F(UopsBenchmarkRunnerTest, ParallelInstruction) {
   // BNDCL32rr is parallel no matter what.
 
   // explicit use 0       : reg RegClass=BNDR
   // explicit use 1       : reg RegClass=GR32
 
   const unsigned Opcode = llvm::X86::BNDCL32rr;
-  const SnippetPrototype Proto = checkAndGetConfigurations(Opcode);
-  EXPECT_THAT(Proto.Explanation, HasSubstr("parallel"));
-  ASSERT_THAT(Proto.Snippet, SizeIs(1));
-  const InstructionBuilder &IB = Proto.Snippet[0];
+  const CodeTemplate CT = checkAndGetCodeTemplate(Opcode);
+  EXPECT_THAT(CT.Info, HasSubstr("parallel"));
+  ASSERT_THAT(CT.Instructions, SizeIs(1));
+  const InstructionBuilder &IB = CT.Instructions[0];
   EXPECT_THAT(IB.getOpcode(), Opcode);
   ASSERT_THAT(IB.VariableValues, SizeIs(2));
   EXPECT_THAT(IB.VariableValues[0], IsInvalid());
   EXPECT_THAT(IB.VariableValues[1], IsInvalid());
 }
 
-TEST_F(UopsSnippetGeneratorTest, SerialInstruction) {
+TEST_F(UopsBenchmarkRunnerTest, SerialInstruction) {
   // CDQ is serial no matter what.
 
   // implicit def         : EAX
   // implicit def         : EDX
   // implicit use         : EAX
   const unsigned Opcode = llvm::X86::CDQ;
-  const SnippetPrototype Proto = checkAndGetConfigurations(Opcode);
-  EXPECT_THAT(Proto.Explanation, HasSubstr("serial"));
-  ASSERT_THAT(Proto.Snippet, SizeIs(1));
-  const InstructionBuilder &IB = Proto.Snippet[0];
+  const CodeTemplate CT = checkAndGetCodeTemplate(Opcode);
+  EXPECT_THAT(CT.Info, HasSubstr("serial"));
+  ASSERT_THAT(CT.Instructions, SizeIs(1));
+  const InstructionBuilder &IB = CT.Instructions[0];
   EXPECT_THAT(IB.getOpcode(), Opcode);
   ASSERT_THAT(IB.VariableValues, SizeIs(0));
 }
 
-TEST_F(UopsSnippetGeneratorTest, StaticRenaming) {
+TEST_F(UopsBenchmarkRunnerTest, StaticRenaming) {
   // CMOVA32rr has tied variables, we enumarate the possible values to execute
   // as many in parallel as possible.
 
   // explicit def 0       : reg RegClass=GR32
   // explicit use 1       : reg RegClass=GR32 | TIED_TO:0
   // explicit use 2       : reg RegClass=GR32
   // implicit use         : EFLAGS
   const unsigned Opcode = llvm::X86::CMOVA32rr;
-  const SnippetPrototype Proto = checkAndGetConfigurations(Opcode);
-  EXPECT_THAT(Proto.Explanation, HasSubstr("static renaming"));
+  const CodeTemplate CT = checkAndGetCodeTemplate(Opcode);
+  EXPECT_THAT(CT.Info, HasSubstr("static renaming"));
   constexpr const unsigned kInstructionCount = 15;
-  ASSERT_THAT(Proto.Snippet, SizeIs(kInstructionCount));
+  ASSERT_THAT(CT.Instructions, SizeIs(kInstructionCount));
   std::unordered_set<unsigned> AllDefRegisters;
-  for (const auto &IB : Proto.Snippet) {
+  for (const auto &IB : CT.Instructions) {
     ASSERT_THAT(IB.VariableValues, SizeIs(2));
     AllDefRegisters.insert(IB.VariableValues[0].getReg());
   }
   EXPECT_THAT(AllDefRegisters, SizeIs(kInstructionCount))
       << "Each instruction writes to a different register";
 }
 
-TEST_F(UopsSnippetGeneratorTest, NoTiedVariables) {
+TEST_F(UopsBenchmarkRunnerTest, NoTiedVariables) {
   // CMOV_GR32 has no tied variables, we make sure def and use are different
   // from each other.
 
   // explicit def 0       : reg RegClass=GR32
   // explicit use 1       : reg RegClass=GR32
   // explicit use 2       : reg RegClass=GR32
   // explicit use 3       : imm
   // implicit use         : EFLAGS
   const unsigned Opcode = llvm::X86::CMOV_GR32;
-  const SnippetPrototype Proto = checkAndGetConfigurations(Opcode);
-  EXPECT_THAT(Proto.Explanation, HasSubstr("no tied variables"));
-  ASSERT_THAT(Proto.Snippet, SizeIs(1));
-  const InstructionBuilder &IB = Proto.Snippet[0];
+  const CodeTemplate CT = checkAndGetCodeTemplate(Opcode);
+  EXPECT_THAT(CT.Info, HasSubstr("no tied variables"));
+  ASSERT_THAT(CT.Instructions, SizeIs(1));
+  const InstructionBuilder &IB = CT.Instructions[0];
   EXPECT_THAT(IB.getOpcode(), Opcode);
   ASSERT_THAT(IB.VariableValues, SizeIs(4));
   EXPECT_THAT(IB.VariableValues[0].getReg(), Not(IB.VariableValues[1].getReg()))
       << "Def is different from first Use";
   EXPECT_THAT(IB.VariableValues[0].getReg(), Not(IB.VariableValues[2].getReg()))
       << "Def is different from second Use";
   EXPECT_THAT(IB.VariableValues[3], IsInvalid());
 }
 
-TEST_F(UopsSnippetGeneratorTest, MemoryUse) {
+TEST_F(UopsBenchmarkRunnerTest, MemoryUse) {
   // Mov32rm reads from memory.
   const unsigned Opcode = llvm::X86::MOV32rm;
-  const SnippetPrototype Proto = checkAndGetConfigurations(Opcode);
-  EXPECT_THAT(Proto.Explanation, HasSubstr("no tied variables"));
-  ASSERT_THAT(Proto.Snippet,
+  const CodeTemplate CT = checkAndGetCodeTemplate(Opcode);
+  EXPECT_THAT(CT.Info, HasSubstr("no tied variables"));
+  ASSERT_THAT(CT.Instructions,
               SizeIs(UopsBenchmarkRunner::kMinNumDifferentAddresses));
-  const InstructionBuilder &IB = Proto.Snippet[0];
+  const InstructionBuilder &IB = CT.Instructions[0];
   EXPECT_THAT(IB.getOpcode(), Opcode);
   ASSERT_THAT(IB.VariableValues, SizeIs(6));
   EXPECT_EQ(IB.VariableValues[2].getImm(), 1);
   EXPECT_EQ(IB.VariableValues[3].getReg(), 0u);
   EXPECT_EQ(IB.VariableValues[4].getImm(), 0);
   EXPECT_EQ(IB.VariableValues[5].getReg(), 0u);
 }
 
-TEST_F(UopsSnippetGeneratorTest, MemoryUse_Movsb) {
+TEST_F(UopsBenchmarkRunnerTest, MemoryUse_Movsb) {
   // MOVSB writes to scratch memory register.
   const unsigned Opcode = llvm::X86::MOVSB;
-  auto Error = Runner.generatePrototype(Opcode).takeError();
+  auto Error = Runner.generateCodeTemplate(Opcode).takeError();
   EXPECT_TRUE((bool)Error);
   llvm::consumeError(std::move(Error));
 }
 
 class FakeBenchmarkRunner : public BenchmarkRunner {
 public:
   FakeBenchmarkRunner(const LLVMState &State)
       : BenchmarkRunner(State, InstructionBenchmark::Unknown) {}
 
   Instruction createInstruction(unsigned Opcode) {
     return Instruction(State.getInstrInfo().get(Opcode), RATC);
   }
 
 private:
-  llvm::Expected<SnippetPrototype>
-  generatePrototype(unsigned Opcode) const override {
+  llvm::Expected<CodeTemplate>
+  generateCodeTemplate(unsigned Opcode) const override {
     return llvm::make_error<llvm::StringError>("not implemented",
                                                llvm::inconvertibleErrorCode());
   }
 
   std::vector<BenchmarkMeasure>
   runMeasurements(const ExecutableFunction &EF, ScratchSpace &Scratch,
                   const unsigned NumRepetitions) const override {
     return {};