[llvm-exegesis] Rename InstructionInstance into InstructionBuilder.

[gchatelet]

Summary

Non functional change.

[gchatelet]

• Fixed a typo

llvm/trunk/tools/llvm-exegesis/lib/BenchmarkRunner.h

public:
 
   virtual ~BenchmarkRunner();
 
   llvm::Expected<std::vector<InstructionBenchmark>>
   run(unsigned Opcode, unsigned NumRepetitions);
 
   // Given a snippet, computes which registers the setup code needs to define.
   std::vector<unsigned>
-  computeRegsToDef(const std::vector<InstructionInstance> &Snippet) const;
+  computeRegsToDef(const std::vector<InstructionBuilder> &Snippet) const;
 
   // Scratch space to run instructions that touch memory.
   struct ScratchSpace {
     static constexpr const size_t kAlignment = 1024;
     static constexpr const size_t kSize = 1 << 20; // 1MB.
     ScratchSpace()
         : UnalignedPtr(llvm::make_unique<char[]>(kSize + kAlignment)),
           AlignedPtr(

llvm/trunk/tools/llvm-exegesis/lib/BenchmarkRunner.cpp

 
 llvm::Expected<std::vector<BenchmarkConfiguration>>
 BenchmarkRunner::generateConfigurations(unsigned Opcode) const {
   if (auto E = generatePrototype(Opcode)) {
     SnippetPrototype &Prototype = E.get();
     // TODO: Generate as many configurations as needed here.
     BenchmarkConfiguration Configuration;
     Configuration.Info = Prototype.Explanation;
-    for (InstructionInstance &II : Prototype.Snippet) {
-      II.randomizeUnsetVariables(
+    for (InstructionBuilder &IB : Prototype.Snippet) {
+      IB.randomizeUnsetVariables(
           Prototype.ScratchSpaceReg
               ? RATC.getRegister(Prototype.ScratchSpaceReg).aliasedBits()
               : RATC.emptyRegisters());
-      Configuration.Snippet.push_back(II.build());
+      Configuration.Snippet.push_back(IB.build());
     }
     if (Prototype.ScratchSpaceReg)
       Configuration.SnippetSetup.LiveIns.push_back(Prototype.ScratchSpaceReg);
     Configuration.SnippetSetup.RegsToDef = computeRegsToDef(Prototype.Snippet);
     return std::vector<BenchmarkConfiguration>{Configuration};
   } else
     return E.takeError();
 }
 
 std::vector<unsigned> BenchmarkRunner::computeRegsToDef(
-    const std::vector<InstructionInstance> &Snippet) const {
+    const std::vector<InstructionBuilder> &Snippet) const {
   // Collect all register uses and create an assignment for each of them.
   // Ignore memory operands which are handled separately.
   // Loop invariant: DefinedRegs[i] is true iif it has been set at least once
   // before the current instruction.
   llvm::BitVector DefinedRegs = RATC.emptyRegisters();
   std::vector<unsigned> RegsToDef;
-  for (const InstructionInstance &II : Snippet) {
+  for (const InstructionBuilder &IB : Snippet) {
     // Returns the register that this Operand sets or uses, or 0 if this is not
     // a register.
-    const auto GetOpReg = [&II](const Operand &Op) -> unsigned {
+    const auto GetOpReg = [&IB](const Operand &Op) -> unsigned {
       if (Op.IsMem)
         return 0;
       if (Op.ImplicitReg)
         return *Op.ImplicitReg;
-      if (Op.IsExplicit && II.getValueFor(Op).isReg())
-        return II.getValueFor(Op).getReg();
+      if (Op.IsExplicit && IB.getValueFor(Op).isReg())
+        return IB.getValueFor(Op).getReg();
       return 0;
     };
     // Collect used registers that have never been def'ed.
-    for (const Operand &Op : II.Instr.Operands) {
+    for (const Operand &Op : IB.Instr.Operands) {
       if (!Op.IsDef) {
         const unsigned Reg = GetOpReg(Op);
         if (Reg > 0 && !DefinedRegs.test(Reg)) {
           RegsToDef.push_back(Reg);
           DefinedRegs.set(Reg);
         }
       }
     }
     // Mark defs as having been def'ed.
-    for (const Operand &Op : II.Instr.Operands) {
+    for (const Operand &Op : IB.Instr.Operands) {
       if (Op.IsDef) {
         const unsigned Reg = GetOpReg(Op);
         if (Reg > 0)
           DefinedRegs.set(Reg);
       }
     }
   }
   return RegsToDef;

 
 llvm::Expected<SnippetPrototype>
 BenchmarkRunner::generateSelfAliasingPrototype(const Instruction &Instr) const {
   const AliasingConfigurations SelfAliasing(Instr, Instr);
   if (SelfAliasing.empty()) {
     return llvm::make_error<BenchmarkFailure>("empty self aliasing");
   }
   SnippetPrototype Prototype;
-  InstructionInstance II(Instr);
+  InstructionBuilder IB(Instr);
   if (SelfAliasing.hasImplicitAliasing()) {
     Prototype.Explanation = "implicit Self cycles, picking random values.";
   } else {
     Prototype.Explanation =
         "explicit self cycles, selecting one aliasing Conf.";
     // This is a self aliasing instruction so defs and uses are from the same
-    // instance, hence twice II in the following call.
-    setRandomAliasing(SelfAliasing, II, II);
+    // instance, hence twice IB in the following call.
+    setRandomAliasing(SelfAliasing, IB, IB);
   }
-  Prototype.Snippet.push_back(std::move(II));
+  Prototype.Snippet.push_back(std::move(IB));
   return std::move(Prototype);
 }
 
 llvm::Expected<SnippetPrototype>
 BenchmarkRunner::generateUnconstrainedPrototype(const Instruction &Instr,
                                                 llvm::StringRef Msg) const {
   SnippetPrototype Prototype;
   Prototype.Explanation =
       llvm::formatv("{0}, repeating an unconstrained assignment", Msg);
   Prototype.Snippet.emplace_back(Instr);
   return std::move(Prototype);
 }
 } // namespace exegesis

llvm/trunk/tools/llvm-exegesis/lib/Latency.cpp

if (auto E = isInfeasible(OtherInstrDesc)) {
       llvm::consumeError(std::move(E));
       continue;
     }
     const Instruction OtherInstr(OtherInstrDesc, RATC);
     const AliasingConfigurations Forward(Instr, OtherInstr);
     const AliasingConfigurations Back(OtherInstr, Instr);
     if (Forward.empty() || Back.empty())
       continue;
-    InstructionInstance ThisII(Instr);
-    InstructionInstance OtherII(OtherInstr);
+    InstructionBuilder ThisIB(Instr);
+    InstructionBuilder OtherIB(OtherInstr);
     if (!Forward.hasImplicitAliasing())
-      setRandomAliasing(Forward, ThisII, OtherII);
+      setRandomAliasing(Forward, ThisIB, OtherIB);
     if (!Back.hasImplicitAliasing())
-      setRandomAliasing(Back, OtherII, ThisII);
+      setRandomAliasing(Back, OtherIB, ThisIB);
     SnippetPrototype Prototype;
     Prototype.Explanation =
         llvm::formatv("creating cycle through {0}.",
                       State.getInstrInfo().getName(OtherOpcode));
-    Prototype.Snippet.push_back(std::move(ThisII));
-    Prototype.Snippet.push_back(std::move(OtherII));
+    Prototype.Snippet.push_back(std::move(ThisIB));
+    Prototype.Snippet.push_back(std::move(OtherIB));
     return std::move(Prototype);
   }
   return llvm::make_error<BenchmarkFailure>(
       "Infeasible : Didn't find any scheme to make the instruction serial");
 }
 
 llvm::Expected<SnippetPrototype>
 LatencyBenchmarkRunner::generatePrototype(unsigned Opcode) const {

llvm/trunk/tools/llvm-exegesis/lib/MCInstrDescView.h

 
 // A variable represents the value associated to an Operand or a set of Operands
 // if they are tied together.
 struct Variable {
   // The indices of the operands tied to this Variable.
   llvm::SmallVector<unsigned, 2> TiedOperands;
   llvm::MCOperand AssignedValue;
   // The index of this Variable in Instruction.Variables and its associated
-  // Value in InstructionInstance.VariableValues.
+  // Value in InstructionBuilder.VariableValues.
   unsigned Index = -1;
 };
 
 // MCOperandInfo can only represents Explicit operands. This object gives a
 // uniform view of Implicit and Explicit Operands.
 //
 // - Index: can be used to refer to MCInstrDesc::operands for Explicit operands.
 // - Tracker: is set for Register Operands and is used to keep track of possible
struct Instruction {
 
   const llvm::MCInstrDesc *Description; // Never nullptr.
   llvm::SmallVector<Operand, 8> Operands;
   llvm::SmallVector<Variable, 4> Variables;
   llvm::BitVector DefRegisters; // The union of the aliased def registers.
   llvm::BitVector UseRegisters; // The union of the aliased use registers.
 };
 
-// An instance of an Instruction holding values for each of its Variables.
-struct InstructionInstance {
-  InstructionInstance(const Instruction &Instr);
-
-  InstructionInstance(const InstructionInstance &);
-  InstructionInstance &operator=(const InstructionInstance &);
-  InstructionInstance(InstructionInstance &&);
-  InstructionInstance &operator=(InstructionInstance &&);
+// A builder for an Instruction holding values for each of its Variables.
+struct InstructionBuilder {
+  InstructionBuilder(const Instruction &Instr);
+
+  InstructionBuilder(const InstructionBuilder &);
+  InstructionBuilder &operator=(const InstructionBuilder &);
+  InstructionBuilder(InstructionBuilder &&);
+  InstructionBuilder &operator=(InstructionBuilder &&);
 
   unsigned getOpcode() const;
   llvm::MCOperand &getValueFor(const Variable &Var);
   const llvm::MCOperand &getValueFor(const Variable &Var) const;
   llvm::MCOperand &getValueFor(const Operand &Op);
   const llvm::MCOperand &getValueFor(const Operand &Op) const;
   bool hasImmediateVariables() const;
 
   // Assigns a Random Value to all Variables that are still Invalid.
   // Do not use any of the registers in `ForbiddenRegs`.
   void randomizeUnsetVariables(const llvm::BitVector &ForbiddenRegs);
 
-  // Returns the instance as an llvm::MCInst. The InstructionInstance must be
+  // Returns the instance as an llvm::MCInst. The InstructionBuilder must be
   // fully allocated (no invalid variables).
   llvm::MCInst build() const;
 
   Instruction Instr;
   llvm::SmallVector<llvm::MCOperand, 4> VariableValues;
 };
 
 // A prototype is a set of InstructionInstances with an explanation of how
struct SnippetPrototype {
   // Moving is OK.
   SnippetPrototype(SnippetPrototype &&);
   SnippetPrototype &operator=(SnippetPrototype &&);
 
   std::string Explanation;
   // If the prototype uses the provided scratch memory, the register in which
   // the pointer to this memory is passed in to the function.
   unsigned ScratchSpaceReg = 0;
-  std::vector<InstructionInstance> Snippet;
+  std::vector<InstructionBuilder> Snippet;
 };
 
 // Represents the assignment of a Register to an Operand.
 struct RegisterOperandAssignment {
   RegisterOperandAssignment(const Operand *Operand, llvm::MCPhysReg Reg)
       : Op(Operand), Reg(Reg) {}
 
   const Operand *Op; // Pointer to an Explicit Register Operand.

 
 // Picks a random bit among the bits set in Vector and returns its index.
 // Precondition: Vector must have at least one bit set.
 size_t randomBit(const llvm::BitVector &Vector);
 
 // Picks a random configuration, then selects a random def and a random use from
 // it and finally set the selected values in the provided InstructionInstances.
 void setRandomAliasing(const AliasingConfigurations &AliasingConfigurations,
-                       InstructionInstance &DefII, InstructionInstance &UseII);
+                       InstructionBuilder &DefIB, InstructionBuilder &UseIB);
 
 // Writes MCInst to OS.
 // This is not assembly but the internal LLVM's name for instructions and
 // registers.
 void DumpMCInst(const llvm::MCRegisterInfo &MCRegisterInfo,
                 const llvm::MCInstrInfo &MCInstrInfo,
                 const llvm::MCInst &MCInst, llvm::raw_ostream &OS);
 
 } // namespace exegesis
 
 #endif // LLVM_TOOLS_LLVM_EXEGESIS_MCINSTRDESCVIEW_H

llvm/trunk/tools/llvm-exegesis/lib/MCInstrDescView.cpp

Instruction::Instruction(const llvm::MCInstrDesc &MCInstrDesc,
   }
 }
 
 bool Instruction::hasMemoryOperands() const {
   return std::any_of(Operands.begin(), Operands.end(),
                      [](const Operand &Op) { return Op.IsMem; });
 }
 
-InstructionInstance::InstructionInstance(const Instruction &Instr)
+InstructionBuilder::InstructionBuilder(const Instruction &Instr)
     : Instr(Instr), VariableValues(Instr.Variables.size()) {}
 
-InstructionInstance::InstructionInstance(InstructionInstance &&) = default;
+InstructionBuilder::InstructionBuilder(InstructionBuilder &&) = default;
 
-InstructionInstance &InstructionInstance::
-operator=(InstructionInstance &&) = default;
+InstructionBuilder &InstructionBuilder::
+operator=(InstructionBuilder &&) = default;
 
-InstructionInstance::InstructionInstance(const InstructionInstance &) = default;
+InstructionBuilder::InstructionBuilder(const InstructionBuilder &) = default;
 
-InstructionInstance &InstructionInstance::
-operator=(const InstructionInstance &) = default;
+InstructionBuilder &InstructionBuilder::
+operator=(const InstructionBuilder &) = default;
 
-unsigned InstructionInstance::getOpcode() const {
+unsigned InstructionBuilder::getOpcode() const {
   return Instr.Description->getOpcode();
 }
 
-llvm::MCOperand &InstructionInstance::getValueFor(const Variable &Var) {
+llvm::MCOperand &InstructionBuilder::getValueFor(const Variable &Var) {
   return VariableValues[Var.Index];
 }
 
 const llvm::MCOperand &
-InstructionInstance::getValueFor(const Variable &Var) const {
+InstructionBuilder::getValueFor(const Variable &Var) const {
   return VariableValues[Var.Index];
 }
 
-llvm::MCOperand &InstructionInstance::getValueFor(const Operand &Op) {
+llvm::MCOperand &InstructionBuilder::getValueFor(const Operand &Op) {
   assert(Op.VariableIndex >= 0);
   return getValueFor(Instr.Variables[Op.VariableIndex]);
 }
 
 const llvm::MCOperand &
-InstructionInstance::getValueFor(const Operand &Op) const {
+InstructionBuilder::getValueFor(const Operand &Op) const {
   assert(Op.VariableIndex >= 0);
   return getValueFor(Instr.Variables[Op.VariableIndex]);
 }
 
 // forward declaration.
 static void randomize(const Instruction &Instr, const Variable &Var,
                       llvm::MCOperand &AssignedValue,
                       const llvm::BitVector &ForbiddenRegs);
 
-bool InstructionInstance::hasImmediateVariables() const {
+bool InstructionBuilder::hasImmediateVariables() const {
   return llvm::any_of(Instr.Variables, [this](const Variable &Var) {
     assert(!Var.TiedOperands.empty());
     const unsigned OpIndex = Var.TiedOperands[0];
     const Operand &Op = Instr.Operands[OpIndex];
     assert(Op.Info);
     return Op.Info->OperandType == llvm::MCOI::OPERAND_IMMEDIATE;
   });
 }
 
-void InstructionInstance::randomizeUnsetVariables(
+void InstructionBuilder::randomizeUnsetVariables(
     const llvm::BitVector &ForbiddenRegs) {
   for (const Variable &Var : Instr.Variables) {
     llvm::MCOperand &AssignedValue = getValueFor(Var);
     if (!AssignedValue.isValid())
       randomize(Instr, Var, AssignedValue, ForbiddenRegs);
   }
 }
 
-llvm::MCInst InstructionInstance::build() const {
+llvm::MCInst InstructionBuilder::build() const {
   llvm::MCInst Result;
   Result.setOpcode(Instr.Description->Opcode);
   for (const auto &Op : Instr.Operands)
     if (Op.IsExplicit)
       Result.addOperand(getValueFor(Op));
   return Result;
 }
 
case llvm::MCOI::OperandType::OPERAND_REGISTER: {
     break;
   }
   default:
     break;
   }
 }
 
 static void setRegisterOperandValue(const RegisterOperandAssignment &ROV,
-                                    InstructionInstance &II) {
+                                    InstructionBuilder &IB) {
   assert(ROV.Op);
   if (ROV.Op->IsExplicit) {
-    auto &AssignedValue = II.getValueFor(*ROV.Op);
+    auto &AssignedValue = IB.getValueFor(*ROV.Op);
     if (AssignedValue.isValid()) {
       assert(AssignedValue.isReg() && AssignedValue.getReg() == ROV.Reg);
       return;
     }
     AssignedValue = llvm::MCOperand::createReg(ROV.Reg);
   } else {
     assert(ROV.Op->ImplicitReg != nullptr);
     assert(ROV.Reg == *ROV.Op->ImplicitReg);
   }
 }
 
 size_t randomBit(const llvm::BitVector &Vector) {
   assert(Vector.any());
   auto Itr = Vector.set_bits_begin();
   for (size_t I = randomIndex(Vector.count()); I != 0; --I)
     ++Itr;
   return *Itr;
 }
 
 void setRandomAliasing(const AliasingConfigurations &AliasingConfigurations,
-                       InstructionInstance &DefII, InstructionInstance &UseII) {
+                       InstructionBuilder &DefIB, InstructionBuilder &UseIB) {
   assert(!AliasingConfigurations.empty());
   assert(!AliasingConfigurations.hasImplicitAliasing());
   const auto &RandomConf = randomElement(AliasingConfigurations.Configurations);
-  setRegisterOperandValue(randomElement(RandomConf.Defs), DefII);
-  setRegisterOperandValue(randomElement(RandomConf.Uses), UseII);
+  setRegisterOperandValue(randomElement(RandomConf.Defs), DefIB);
+  setRegisterOperandValue(randomElement(RandomConf.Uses), UseIB);
 }
 
 void DumpMCOperand(const llvm::MCRegisterInfo &MCRegisterInfo,
                    const llvm::MCOperand &Op, llvm::raw_ostream &OS) {
   if (!Op.isValid())
     OS << "Invalid";
   else if (Op.isReg())
     OS << MCRegisterInfo.getName(Op.getReg());

llvm/trunk/tools/llvm-exegesis/lib/Target.h

public:
   // Returns the register pointing to scratch memory, or 0 if this target does
   // not support memory operands. The benchmark function uses the default
   // calling convention.
   virtual unsigned getScratchMemoryRegister(const llvm::Triple &) const {
     return 0;
   }
 
   // Fills memory operands with references to the address at [Reg] + Offset.
-  virtual void fillMemoryOperands(InstructionInstance &II, unsigned Reg,
+  virtual void fillMemoryOperands(InstructionBuilder &IB, unsigned Reg,
                                   unsigned Offset) const {
     llvm_unreachable(
         "fillMemoryOperands() requires getScratchMemoryRegister() > 0");
   }
 
   // Returns the maximum number of bytes a load/store instruction can access at
   // once. This is typically the size of the largest register available on the
   // processor. Note that this only used as a hint to generate independant

llvm/trunk/tools/llvm-exegesis/lib/Uops.h

private:
   // we might generate:
   //   mov eax, [rdi]
   //   add eax, [rdi + 64]
   //   mov eax, [rdi + 128]
   //   add eax, [rdi + 192]
   //   mov eax, [rdi + 256]
   void
   instantiateMemoryOperands(unsigned ScratchSpaceReg,
-                            std::vector<InstructionInstance> &Snippet) const;
+                            std::vector<InstructionBuilder> &Snippet) const;
 };
 
 } // namespace exegesis
 
 #endif // LLVM_TOOLS_LLVM_EXEGESIS_UOPS_H

llvm/trunk/tools/llvm-exegesis/lib/Uops.cpp

static void remove(llvm::BitVector &a, const llvm::BitVector &b) {
   for (auto I : b.set_bits())
     a.reset(I);
 }
 
 UopsBenchmarkRunner::~UopsBenchmarkRunner() = default;
 
 void UopsBenchmarkRunner::instantiateMemoryOperands(
     const unsigned ScratchSpaceReg,
-    std::vector<InstructionInstance> &Snippet) const {
+    std::vector<InstructionBuilder> &Snippet) const {
   if (ScratchSpaceReg == 0)
-    return;  // no memory operands.
+    return; // no memory operands.
   const auto &ET = State.getExegesisTarget();
   const unsigned MemStep = ET.getMaxMemoryAccessSize();
   const size_t OriginalSnippetSize = Snippet.size();
   size_t I = 0;
-  for (InstructionInstance &II : Snippet) {
-    ET.fillMemoryOperands(II, ScratchSpaceReg, I * MemStep);
+  for (InstructionBuilder &IB : Snippet) {
+    ET.fillMemoryOperands(IB, ScratchSpaceReg, I * MemStep);
     ++I;
   }
 
   while (Snippet.size() < kMinNumDifferentAddresses) {
-    InstructionInstance II = Snippet[I % OriginalSnippetSize];
-    ET.fillMemoryOperands(II, ScratchSpaceReg, I * MemStep);
+    InstructionBuilder IB = Snippet[I % OriginalSnippetSize];
+    ET.fillMemoryOperands(IB, ScratchSpaceReg, I * MemStep);
     ++I;
-    Snippet.push_back(std::move(II));
+    Snippet.push_back(std::move(IB));
   }
   assert(I * MemStep < ScratchSpace::kSize && "not enough scratch space");
 }
 
 llvm::Expected<SnippetPrototype>
 UopsBenchmarkRunner::generatePrototype(unsigned Opcode) const {
   const auto &InstrDesc = State.getInstrInfo().get(Opcode);
   if (auto E = isInfeasible(InstrDesc))
for (const auto &Op : Instr.Operands) {
       if (Op.IsDef && Op.ImplicitReg &&
           ScratchSpaceAliasedRegs->test(*Op.ImplicitReg))
         return llvm::make_error<BenchmarkFailure>(
             "Infeasible : memory instruction uses scratch memory register");
     }
   }
 
   const AliasingConfigurations SelfAliasing(Instr, Instr);
-  InstructionInstance II(Instr);
+  InstructionBuilder IB(Instr);
   if (SelfAliasing.empty()) {
     Prototype.Explanation = "instruction is parallel, repeating a random one.";
-    Prototype.Snippet.push_back(std::move(II));
+    Prototype.Snippet.push_back(std::move(IB));
     instantiateMemoryOperands(Prototype.ScratchSpaceReg, Prototype.Snippet);
     return std::move(Prototype);
   }
   if (SelfAliasing.hasImplicitAliasing()) {
     Prototype.Explanation = "instruction is serial, repeating a random one.";
-    Prototype.Snippet.push_back(std::move(II));
+    Prototype.Snippet.push_back(std::move(IB));
     instantiateMemoryOperands(Prototype.ScratchSpaceReg, Prototype.Snippet);
     return std::move(Prototype);
   }
   const auto TiedVariables = getTiedVariables(Instr);
   if (!TiedVariables.empty()) {
     if (TiedVariables.size() > 1)
       return llvm::make_error<llvm::StringError>(
           "Infeasible : don't know how to handle several tied variables",
           llvm::inconvertibleErrorCode());
     const Variable *Var = TiedVariables.front();
     assert(Var);
     assert(!Var->TiedOperands.empty());
     const Operand &Op = Instr.Operands[Var->TiedOperands.front()];
     assert(Op.Tracker);
     Prototype.Explanation =
         "instruction has tied variables using static renaming.";
     for (const llvm::MCPhysReg Reg : Op.Tracker->sourceBits().set_bits()) {
       if (ScratchSpaceAliasedRegs && ScratchSpaceAliasedRegs->test(Reg))
         continue; // Do not use the scratch memory address register.
-      InstructionInstance TmpII = II;
-      TmpII.getValueFor(*Var) = llvm::MCOperand::createReg(Reg);
-      Prototype.Snippet.push_back(std::move(TmpII));
+      InstructionBuilder TmpIB = IB;
+      TmpIB.getValueFor(*Var) = llvm::MCOperand::createReg(Reg);
+      Prototype.Snippet.push_back(std::move(TmpIB));
     }
     instantiateMemoryOperands(Prototype.ScratchSpaceReg, Prototype.Snippet);
     return std::move(Prototype);
   }
   // No tied variables, we pick random values for defs.
   llvm::BitVector Defs(State.getRegInfo().getNumRegs());
   for (const auto &Op : Instr.Operands) {
     if (Op.Tracker && Op.IsExplicit && Op.IsDef && !Op.IsMem) {
       auto PossibleRegisters = Op.Tracker->sourceBits();
       remove(PossibleRegisters, RATC.reservedRegisters());
       // Do not use the scratch memory address register.
       if (ScratchSpaceAliasedRegs)
         remove(PossibleRegisters, *ScratchSpaceAliasedRegs);
       assert(PossibleRegisters.any() && "No register left to choose from");
       const auto RandomReg = randomBit(PossibleRegisters);
       Defs.set(RandomReg);
-      II.getValueFor(Op) = llvm::MCOperand::createReg(RandomReg);
+      IB.getValueFor(Op) = llvm::MCOperand::createReg(RandomReg);
     }
   }
   // And pick random use values that are not reserved and don't alias with defs.
   const auto DefAliases = getAliasedBits(State.getRegInfo(), Defs);
   for (const auto &Op : Instr.Operands) {
     if (Op.Tracker && Op.IsExplicit && !Op.IsDef && !Op.IsMem) {
       auto PossibleRegisters = Op.Tracker->sourceBits();
       remove(PossibleRegisters, RATC.reservedRegisters());
       // Do not use the scratch memory address register.
       if (ScratchSpaceAliasedRegs)
         remove(PossibleRegisters, *ScratchSpaceAliasedRegs);
       remove(PossibleRegisters, DefAliases);
       assert(PossibleRegisters.any() && "No register left to choose from");
       const auto RandomReg = randomBit(PossibleRegisters);
-      II.getValueFor(Op) = llvm::MCOperand::createReg(RandomReg);
+      IB.getValueFor(Op) = llvm::MCOperand::createReg(RandomReg);
     }
   }
   Prototype.Explanation =
       "instruction has no tied variables picking Uses different from defs";
-  Prototype.Snippet.push_back(std::move(II));
+  Prototype.Snippet.push_back(std::move(IB));
   instantiateMemoryOperands(Prototype.ScratchSpaceReg, Prototype.Snippet);
   return std::move(Prototype);
 }
 
 std::vector<BenchmarkMeasure>
 UopsBenchmarkRunner::runMeasurements(const ExecutableFunction &Function,
                                      ScratchSpace &Scratch,
                                      const unsigned NumRepetitions) const {

llvm/trunk/tools/llvm-exegesis/lib/X86/Target.cpp

if (!TT.isArch64Bit()) {
       // add some additional setup code.
       return 0;
     }
     return TT.isOSWindows() ? llvm::X86::RCX : llvm::X86::RDI;
   }
 
   unsigned getMaxMemoryAccessSize() const override { return 64; }
 
-  void fillMemoryOperands(InstructionInstance &II, unsigned Reg,
+  void fillMemoryOperands(InstructionBuilder &IB, unsigned Reg,
                           unsigned Offset) const override {
     // FIXME: For instructions that read AND write to memory, we use the same
     // value for input and output.
-    for (size_t I = 0, E = II.Instr.Operands.size(); I < E; ++I) {
-      const Operand *Op = &II.Instr.Operands[I];
+    for (size_t I = 0, E = IB.Instr.Operands.size(); I < E; ++I) {
+      const Operand *Op = &IB.Instr.Operands[I];
       if (Op->IsExplicit && Op->IsMem) {
         // Case 1: 5-op memory.
         assert((I + 5 <= E) && "x86 memory references are always 5 ops");
-        II.getValueFor(*Op) = llvm::MCOperand::createReg(Reg); // BaseReg
-        Op = &II.Instr.Operands[++I];
+        IB.getValueFor(*Op) = llvm::MCOperand::createReg(Reg); // BaseReg
+        Op = &IB.Instr.Operands[++I];
         assert(Op->IsMem);
         assert(Op->IsExplicit);
-        II.getValueFor(*Op) = llvm::MCOperand::createImm(1); // ScaleAmt
-        Op = &II.Instr.Operands[++I];
+        IB.getValueFor(*Op) = llvm::MCOperand::createImm(1); // ScaleAmt
+        Op = &IB.Instr.Operands[++I];
         assert(Op->IsMem);
         assert(Op->IsExplicit);
-        II.getValueFor(*Op) = llvm::MCOperand::createReg(0); // IndexReg
-        Op = &II.Instr.Operands[++I];
+        IB.getValueFor(*Op) = llvm::MCOperand::createReg(0); // IndexReg
+        Op = &IB.Instr.Operands[++I];
         assert(Op->IsMem);
         assert(Op->IsExplicit);
-        II.getValueFor(*Op) = llvm::MCOperand::createImm(Offset); // Disp
-        Op = &II.Instr.Operands[++I];
+        IB.getValueFor(*Op) = llvm::MCOperand::createImm(Offset); // Disp
+        Op = &IB.Instr.Operands[++I];
         assert(Op->IsMem);
         assert(Op->IsExplicit);
-        II.getValueFor(*Op) = llvm::MCOperand::createReg(0); // Segment
+        IB.getValueFor(*Op) = llvm::MCOperand::createReg(0); // Segment
         // Case2: segment:index addressing. We assume that ES is 0.
       }
     }
   }
 
   std::vector<llvm::MCInst> setRegToConstant(const llvm::MCSubtargetInfo &STI,
                                              unsigned Reg) const override {
     // GPR.

llvm/trunk/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp

TEST_F(LatencySnippetGeneratorTest, ImplicitSelfDependency) {
   const unsigned Opcode = llvm::X86::ADC16i16;
   EXPECT_THAT(MCInstrInfo.get(Opcode).getImplicitDefs()[0], llvm::X86::AX);
   EXPECT_THAT(MCInstrInfo.get(Opcode).getImplicitDefs()[1], llvm::X86::EFLAGS);
   EXPECT_THAT(MCInstrInfo.get(Opcode).getImplicitUses()[0], llvm::X86::AX);
   EXPECT_THAT(MCInstrInfo.get(Opcode).getImplicitUses()[1], llvm::X86::EFLAGS);
   const SnippetPrototype Proto = checkAndGetConfigurations(Opcode);
   EXPECT_THAT(Proto.Explanation, HasSubstr("implicit"));
   ASSERT_THAT(Proto.Snippet, SizeIs(1));
-  const InstructionInstance &II = Proto.Snippet[0];
-  EXPECT_THAT(II.getOpcode(), Opcode);
-  ASSERT_THAT(II.VariableValues, SizeIs(1)); // Imm.
-  EXPECT_THAT(II.VariableValues[0], IsInvalid()) << "Immediate is not set";
+  const InstructionBuilder &IB = Proto.Snippet[0];
+  EXPECT_THAT(IB.getOpcode(), Opcode);
+  ASSERT_THAT(IB.VariableValues, SizeIs(1)); // Imm.
+  EXPECT_THAT(IB.VariableValues[0], IsInvalid()) << "Immediate is not set";
 }
 
 TEST_F(LatencySnippetGeneratorTest, ExplicitSelfDependency) {
   // ADD16ri self alias because Op0 and Op1 are tied together.
 
   // explicit def 0       : reg RegClass=GR16
   // explicit use 1       : reg RegClass=GR16 | TIED_TO:0
   // explicit use 2       : imm
   // implicit def         : EFLAGS
   const unsigned Opcode = llvm::X86::ADD16ri;
   EXPECT_THAT(MCInstrInfo.get(Opcode).getImplicitDefs()[0], llvm::X86::EFLAGS);
   const SnippetPrototype Proto = checkAndGetConfigurations(Opcode);
   EXPECT_THAT(Proto.Explanation, HasSubstr("explicit"));
   ASSERT_THAT(Proto.Snippet, SizeIs(1));
-  const InstructionInstance &II = Proto.Snippet[0];
-  EXPECT_THAT(II.getOpcode(), Opcode);
-  ASSERT_THAT(II.VariableValues, SizeIs(2));
-  EXPECT_THAT(II.VariableValues[0], IsReg()) << "Operand 0 and 1";
-  EXPECT_THAT(II.VariableValues[1], IsInvalid()) << "Operand 2 is not set";
+  const InstructionBuilder &IB = Proto.Snippet[0];
+  EXPECT_THAT(IB.getOpcode(), Opcode);
+  ASSERT_THAT(IB.VariableValues, SizeIs(2));
+  EXPECT_THAT(IB.VariableValues[0], IsReg()) << "Operand 0 and 1";
+  EXPECT_THAT(IB.VariableValues[1], IsInvalid()) << "Operand 2 is not set";
 }
 
 TEST_F(LatencySnippetGeneratorTest, DependencyThroughOtherOpcode) {
   // CMP64rr
   // explicit use 0       : reg RegClass=GR64
   // explicit use 1       : reg RegClass=GR64
   // implicit def         : EFLAGS
 
   const unsigned Opcode = llvm::X86::CMP64rr;
   const SnippetPrototype Proto = checkAndGetConfigurations(Opcode);
   EXPECT_THAT(Proto.Explanation, HasSubstr("cycle through"));
   ASSERT_THAT(Proto.Snippet, SizeIs(2));
-  const InstructionInstance &II = Proto.Snippet[0];
-  EXPECT_THAT(II.getOpcode(), Opcode);
-  ASSERT_THAT(II.VariableValues, SizeIs(2));
-  EXPECT_THAT(II.VariableValues, AnyOf(ElementsAre(IsReg(), IsInvalid()),
+  const InstructionBuilder &IB = Proto.Snippet[0];
+  EXPECT_THAT(IB.getOpcode(), Opcode);
+  ASSERT_THAT(IB.VariableValues, SizeIs(2));
+  EXPECT_THAT(IB.VariableValues, AnyOf(ElementsAre(IsReg(), IsInvalid()),
                                        ElementsAre(IsInvalid(), IsReg())));
   EXPECT_THAT(Proto.Snippet[1].getOpcode(), Not(Opcode));
   // TODO: check that the two instructions alias each other.
 }
 
 TEST_F(LatencySnippetGeneratorTest, LAHF) {
   const unsigned Opcode = llvm::X86::LAHF;
   const SnippetPrototype Proto = checkAndGetConfigurations(Opcode);
   EXPECT_THAT(Proto.Explanation, HasSubstr("cycle through"));
   ASSERT_THAT(Proto.Snippet, SizeIs(2));
-  const InstructionInstance &II = Proto.Snippet[0];
-  EXPECT_THAT(II.getOpcode(), Opcode);
-  ASSERT_THAT(II.VariableValues, SizeIs(0));
+  const InstructionBuilder &IB = Proto.Snippet[0];
+  EXPECT_THAT(IB.getOpcode(), Opcode);
+  ASSERT_THAT(IB.VariableValues, SizeIs(0));
 }
 
 TEST_F(UopsSnippetGeneratorTest, ParallelInstruction) {
   // BNDCL32rr is parallel no matter what.
 
   // explicit use 0       : reg RegClass=BNDR
   // explicit use 1       : reg RegClass=GR32
 
   const unsigned Opcode = llvm::X86::BNDCL32rr;
   const SnippetPrototype Proto = checkAndGetConfigurations(Opcode);
   EXPECT_THAT(Proto.Explanation, HasSubstr("parallel"));
   ASSERT_THAT(Proto.Snippet, SizeIs(1));
-  const InstructionInstance &II = Proto.Snippet[0];
-  EXPECT_THAT(II.getOpcode(), Opcode);
-  ASSERT_THAT(II.VariableValues, SizeIs(2));
-  EXPECT_THAT(II.VariableValues[0], IsInvalid());
-  EXPECT_THAT(II.VariableValues[1], IsInvalid());
+  const InstructionBuilder &IB = Proto.Snippet[0];
+  EXPECT_THAT(IB.getOpcode(), Opcode);
+  ASSERT_THAT(IB.VariableValues, SizeIs(2));
+  EXPECT_THAT(IB.VariableValues[0], IsInvalid());
+  EXPECT_THAT(IB.VariableValues[1], IsInvalid());
 }
 
 TEST_F(UopsSnippetGeneratorTest, SerialInstruction) {
   // CDQ is serial no matter what.
 
   // implicit def         : EAX
   // implicit def         : EDX
   // implicit use         : EAX
   const unsigned Opcode = llvm::X86::CDQ;
   const SnippetPrototype Proto = checkAndGetConfigurations(Opcode);
   EXPECT_THAT(Proto.Explanation, HasSubstr("serial"));
   ASSERT_THAT(Proto.Snippet, SizeIs(1));
-  const InstructionInstance &II = Proto.Snippet[0];
-  EXPECT_THAT(II.getOpcode(), Opcode);
-  ASSERT_THAT(II.VariableValues, SizeIs(0));
+  const InstructionBuilder &IB = Proto.Snippet[0];
+  EXPECT_THAT(IB.getOpcode(), Opcode);
+  ASSERT_THAT(IB.VariableValues, SizeIs(0));
 }
 
 TEST_F(UopsSnippetGeneratorTest, StaticRenaming) {
   // CMOVA32rr has tied variables, we enumarate the possible values to execute
   // as many in parallel as possible.
 
   // explicit def 0       : reg RegClass=GR32
   // explicit use 1       : reg RegClass=GR32 | TIED_TO:0
   // explicit use 2       : reg RegClass=GR32
   // implicit use         : EFLAGS
   const unsigned Opcode = llvm::X86::CMOVA32rr;
   const SnippetPrototype Proto = checkAndGetConfigurations(Opcode);
   EXPECT_THAT(Proto.Explanation, HasSubstr("static renaming"));
   constexpr const unsigned kInstructionCount = 15;
   ASSERT_THAT(Proto.Snippet, SizeIs(kInstructionCount));
   std::unordered_set<unsigned> AllDefRegisters;
-  for (const auto &II : Proto.Snippet) {
-    ASSERT_THAT(II.VariableValues, SizeIs(2));
-    AllDefRegisters.insert(II.VariableValues[0].getReg());
+  for (const auto &IB : Proto.Snippet) {
+    ASSERT_THAT(IB.VariableValues, SizeIs(2));
+    AllDefRegisters.insert(IB.VariableValues[0].getReg());
   }
   EXPECT_THAT(AllDefRegisters, SizeIs(kInstructionCount))
       << "Each instruction writes to a different register";
 }
 
 TEST_F(UopsSnippetGeneratorTest, NoTiedVariables) {
   // CMOV_GR32 has no tied variables, we make sure def and use are different
   // from each other.
 
   // explicit def 0       : reg RegClass=GR32
   // explicit use 1       : reg RegClass=GR32
   // explicit use 2       : reg RegClass=GR32
   // explicit use 3       : imm
   // implicit use         : EFLAGS
   const unsigned Opcode = llvm::X86::CMOV_GR32;
   const SnippetPrototype Proto = checkAndGetConfigurations(Opcode);
   EXPECT_THAT(Proto.Explanation, HasSubstr("no tied variables"));
   ASSERT_THAT(Proto.Snippet, SizeIs(1));
-  const InstructionInstance &II = Proto.Snippet[0];
-  EXPECT_THAT(II.getOpcode(), Opcode);
-  ASSERT_THAT(II.VariableValues, SizeIs(4));
-  EXPECT_THAT(II.VariableValues[0].getReg(), Not(II.VariableValues[1].getReg()))
+  const InstructionBuilder &IB = Proto.Snippet[0];
+  EXPECT_THAT(IB.getOpcode(), Opcode);
+  ASSERT_THAT(IB.VariableValues, SizeIs(4));
+  EXPECT_THAT(IB.VariableValues[0].getReg(), Not(IB.VariableValues[1].getReg()))
       << "Def is different from first Use";
-  EXPECT_THAT(II.VariableValues[0].getReg(), Not(II.VariableValues[2].getReg()))
+  EXPECT_THAT(IB.VariableValues[0].getReg(), Not(IB.VariableValues[2].getReg()))
       << "Def is different from second Use";
-  EXPECT_THAT(II.VariableValues[3], IsInvalid());
+  EXPECT_THAT(IB.VariableValues[3], IsInvalid());
 }
 
 TEST_F(UopsSnippetGeneratorTest, MemoryUse) {
   // Mov32rm reads from memory.
   const unsigned Opcode = llvm::X86::MOV32rm;
   const SnippetPrototype Proto = checkAndGetConfigurations(Opcode);
   EXPECT_THAT(Proto.Explanation, HasSubstr("no tied variables"));
   ASSERT_THAT(Proto.Snippet,
               SizeIs(UopsBenchmarkRunner::kMinNumDifferentAddresses));
-  const InstructionInstance &II = Proto.Snippet[0];
-  EXPECT_THAT(II.getOpcode(), Opcode);
-  ASSERT_THAT(II.VariableValues, SizeIs(6));
-  EXPECT_EQ(II.VariableValues[2].getImm(), 1);
-  EXPECT_EQ(II.VariableValues[3].getReg(), 0u);
-  EXPECT_EQ(II.VariableValues[4].getImm(), 0);
-  EXPECT_EQ(II.VariableValues[5].getReg(), 0u);
+  const InstructionBuilder &IB = Proto.Snippet[0];
+  EXPECT_THAT(IB.getOpcode(), Opcode);
+  ASSERT_THAT(IB.VariableValues, SizeIs(6));
+  EXPECT_EQ(IB.VariableValues[2].getImm(), 1);
+  EXPECT_EQ(IB.VariableValues[3].getReg(), 0u);
+  EXPECT_EQ(IB.VariableValues[4].getImm(), 0);
+  EXPECT_EQ(IB.VariableValues[5].getReg(), 0u);
 }
 
 TEST_F(UopsSnippetGeneratorTest, MemoryUse_Movsb) {
   // MOVSB writes to scratch memory register.
   const unsigned Opcode = llvm::X86::MOVSB;
   auto Error = Runner.generatePrototype(Opcode).takeError();
   EXPECT_TRUE((bool)Error);
   llvm::consumeError(std::move(Error));

 using FakeSnippetGeneratorTest = SnippetGeneratorTest<FakeBenchmarkRunner>;
 
 TEST_F(FakeSnippetGeneratorTest, ComputeRegsToDefAdd16ri) {
   // ADD16ri:
   // explicit def 0       : reg RegClass=GR16
   // explicit use 1       : reg RegClass=GR16 | TIED_TO:0
   // explicit use 2       : imm
   // implicit def         : EFLAGS
-  InstructionInstance II(Runner.createInstruction(llvm::X86::ADD16ri));
-  II.getValueFor(II.Instr.Variables[0]) =
+  InstructionBuilder IB(Runner.createInstruction(llvm::X86::ADD16ri));
+  IB.getValueFor(IB.Instr.Variables[0]) =
       llvm::MCOperand::createReg(llvm::X86::AX);
-  std::vector<InstructionInstance> Snippet;
-  Snippet.push_back(std::move(II));
+  std::vector<InstructionBuilder> Snippet;
+  Snippet.push_back(std::move(IB));
   const auto RegsToDef = Runner.computeRegsToDef(Snippet);
   EXPECT_THAT(RegsToDef, UnorderedElementsAre(llvm::X86::AX));
 }
 
 TEST_F(FakeSnippetGeneratorTest, ComputeRegsToDefAdd64rr) {
   // ADD64rr:
   //  mov64ri rax, 42
   //  add64rr rax, rax, rbx
   // -> only rbx needs defining.
-  std::vector<InstructionInstance> Snippet;
+  std::vector<InstructionBuilder> Snippet;
   {
-    InstructionInstance Mov(Runner.createInstruction(llvm::X86::MOV64ri));
+    InstructionBuilder Mov(Runner.createInstruction(llvm::X86::MOV64ri));
     Mov.getValueFor(Mov.Instr.Variables[0]) =
         llvm::MCOperand::createReg(llvm::X86::RAX);
     Mov.getValueFor(Mov.Instr.Variables[1]) = llvm::MCOperand::createImm(42);
     Snippet.push_back(std::move(Mov));
   }
   {
-    InstructionInstance Add(Runner.createInstruction(llvm::X86::ADD64rr));
+    InstructionBuilder Add(Runner.createInstruction(llvm::X86::ADD64rr));
     Add.getValueFor(Add.Instr.Variables[0]) =
         llvm::MCOperand::createReg(llvm::X86::RAX);
     Add.getValueFor(Add.Instr.Variables[1]) =
         llvm::MCOperand::createReg(llvm::X86::RBX);
     Snippet.push_back(std::move(Add));
   }
 
   const auto RegsToDef = Runner.computeRegsToDef(Snippet);
   EXPECT_THAT(RegsToDef, UnorderedElementsAre(llvm::X86::RBX));
 }
 
 } // namespace
 } // namespace exegesis