Skip to content

Commit 171f3f4

Browse files
gchateletgchatelet
committedAug 2, 2018
[llvm-exegesis] Rename InstructionInstance into InstructionBuilder.
Summary: Non functional change. Subscribers: tschuett, courbet, llvm-commits Differential Revision: https://reviews.llvm.org/D50176 llvm-svn: 338701
1 parent 440e96f commit 171f3f4

File tree

10 files changed

+129
-129
lines changed

10 files changed

+129
-129
lines changed
 

‎llvm/tools/llvm-exegesis/lib/BenchmarkRunner.cpp

+14-14
Original file line numberDiff line numberDiff line change
@@ -131,12 +131,12 @@ BenchmarkRunner::generateConfigurations(unsigned Opcode) const {
131131
// TODO: Generate as many configurations as needed here.
132132
BenchmarkConfiguration Configuration;
133133
Configuration.Info = Prototype.Explanation;
134-
for (InstructionInstance &II : Prototype.Snippet) {
135-
II.randomizeUnsetVariables(
134+
for (InstructionBuilder &IB : Prototype.Snippet) {
135+
IB.randomizeUnsetVariables(
136136
Prototype.ScratchSpaceReg
137137
? RATC.getRegister(Prototype.ScratchSpaceReg).aliasedBits()
138138
: RATC.emptyRegisters());
139-
Configuration.Snippet.push_back(II.build());
139+
Configuration.Snippet.push_back(IB.build());
140140
}
141141
if (Prototype.ScratchSpaceReg)
142142
Configuration.SnippetSetup.LiveIns.push_back(Prototype.ScratchSpaceReg);
@@ -147,27 +147,27 @@ BenchmarkRunner::generateConfigurations(unsigned Opcode) const {
147147
}
148148

149149
std::vector<unsigned> BenchmarkRunner::computeRegsToDef(
150-
const std::vector<InstructionInstance> &Snippet) const {
150+
const std::vector<InstructionBuilder> &Snippet) const {
151151
// Collect all register uses and create an assignment for each of them.
152152
// Ignore memory operands which are handled separately.
153153
// Loop invariant: DefinedRegs[i] is true iif it has been set at least once
154154
// before the current instruction.
155155
llvm::BitVector DefinedRegs = RATC.emptyRegisters();
156156
std::vector<unsigned> RegsToDef;
157-
for (const InstructionInstance &II : Snippet) {
157+
for (const InstructionBuilder &IB : Snippet) {
158158
// Returns the register that this Operand sets or uses, or 0 if this is not
159159
// a register.
160-
const auto GetOpReg = [&II](const Operand &Op) -> unsigned {
160+
const auto GetOpReg = [&IB](const Operand &Op) -> unsigned {
161161
if (Op.IsMem)
162162
return 0;
163163
if (Op.ImplicitReg)
164164
return *Op.ImplicitReg;
165-
if (Op.IsExplicit && II.getValueFor(Op).isReg())
166-
return II.getValueFor(Op).getReg();
165+
if (Op.IsExplicit && IB.getValueFor(Op).isReg())
166+
return IB.getValueFor(Op).getReg();
167167
return 0;
168168
};
169169
// Collect used registers that have never been def'ed.
170-
for (const Operand &Op : II.Instr.Operands) {
170+
for (const Operand &Op : IB.Instr.Operands) {
171171
if (!Op.IsDef) {
172172
const unsigned Reg = GetOpReg(Op);
173173
if (Reg > 0 && !DefinedRegs.test(Reg)) {
@@ -177,7 +177,7 @@ std::vector<unsigned> BenchmarkRunner::computeRegsToDef(
177177
}
178178
}
179179
// Mark defs as having been def'ed.
180-
for (const Operand &Op : II.Instr.Operands) {
180+
for (const Operand &Op : IB.Instr.Operands) {
181181
if (Op.IsDef) {
182182
const unsigned Reg = GetOpReg(Op);
183183
if (Reg > 0)
@@ -209,17 +209,17 @@ BenchmarkRunner::generateSelfAliasingPrototype(const Instruction &Instr) const {
209209
return llvm::make_error<BenchmarkFailure>("empty self aliasing");
210210
}
211211
SnippetPrototype Prototype;
212-
InstructionInstance II(Instr);
212+
InstructionBuilder IB(Instr);
213213
if (SelfAliasing.hasImplicitAliasing()) {
214214
Prototype.Explanation = "implicit Self cycles, picking random values.";
215215
} else {
216216
Prototype.Explanation =
217217
"explicit self cycles, selecting one aliasing Conf.";
218218
// This is a self aliasing instruction so defs and uses are from the same
219-
// instance, hence twice II in the following call.
220-
setRandomAliasing(SelfAliasing, II, II);
219+
// instance, hence twice IB in the following call.
220+
setRandomAliasing(SelfAliasing, IB, IB);
221221
}
222-
Prototype.Snippet.push_back(std::move(II));
222+
Prototype.Snippet.push_back(std::move(IB));
223223
return std::move(Prototype);
224224
}
225225

‎llvm/tools/llvm-exegesis/lib/BenchmarkRunner.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -67,7 +67,7 @@ class BenchmarkRunner {
6767

6868
// Given a snippet, computes which registers the setup code needs to define.
6969
std::vector<unsigned>
70-
computeRegsToDef(const std::vector<InstructionInstance> &Snippet) const;
70+
computeRegsToDef(const std::vector<InstructionBuilder> &Snippet) const;
7171

7272
// Scratch space to run instructions that touch memory.
7373
struct ScratchSpace {

‎llvm/tools/llvm-exegesis/lib/Latency.cpp

+6-6
Original file line numberDiff line numberDiff line change
@@ -62,18 +62,18 @@ LatencyBenchmarkRunner::generateTwoInstructionPrototype(
6262
const AliasingConfigurations Back(OtherInstr, Instr);
6363
if (Forward.empty() || Back.empty())
6464
continue;
65-
InstructionInstance ThisII(Instr);
66-
InstructionInstance OtherII(OtherInstr);
65+
InstructionBuilder ThisIB(Instr);
66+
InstructionBuilder OtherIB(OtherInstr);
6767
if (!Forward.hasImplicitAliasing())
68-
setRandomAliasing(Forward, ThisII, OtherII);
68+
setRandomAliasing(Forward, ThisIB, OtherIB);
6969
if (!Back.hasImplicitAliasing())
70-
setRandomAliasing(Back, OtherII, ThisII);
70+
setRandomAliasing(Back, OtherIB, ThisIB);
7171
SnippetPrototype Prototype;
7272
Prototype.Explanation =
7373
llvm::formatv("creating cycle through {0}.",
7474
State.getInstrInfo().getName(OtherOpcode));
75-
Prototype.Snippet.push_back(std::move(ThisII));
76-
Prototype.Snippet.push_back(std::move(OtherII));
75+
Prototype.Snippet.push_back(std::move(ThisIB));
76+
Prototype.Snippet.push_back(std::move(OtherIB));
7777
return std::move(Prototype);
7878
}
7979
return llvm::make_error<BenchmarkFailure>(

‎llvm/tools/llvm-exegesis/lib/MCInstrDescView.cpp

+20-20
Original file line numberDiff line numberDiff line change
@@ -89,39 +89,39 @@ bool Instruction::hasMemoryOperands() const {
8989
[](const Operand &Op) { return Op.IsMem; });
9090
}
9191

92-
InstructionInstance::InstructionInstance(const Instruction &Instr)
92+
InstructionBuilder::InstructionBuilder(const Instruction &Instr)
9393
: Instr(Instr), VariableValues(Instr.Variables.size()) {}
9494

95-
InstructionInstance::InstructionInstance(InstructionInstance &&) = default;
95+
InstructionBuilder::InstructionBuilder(InstructionBuilder &&) = default;
9696

97-
InstructionInstance &InstructionInstance::
98-
operator=(InstructionInstance &&) = default;
97+
InstructionBuilder &InstructionBuilder::
98+
operator=(InstructionBuilder &&) = default;
9999

100-
InstructionInstance::InstructionInstance(const InstructionInstance &) = default;
100+
InstructionBuilder::InstructionBuilder(const InstructionBuilder &) = default;
101101

102-
InstructionInstance &InstructionInstance::
103-
operator=(const InstructionInstance &) = default;
102+
InstructionBuilder &InstructionBuilder::
103+
operator=(const InstructionBuilder &) = default;
104104

105-
unsigned InstructionInstance::getOpcode() const {
105+
unsigned InstructionBuilder::getOpcode() const {
106106
return Instr.Description->getOpcode();
107107
}
108108

109-
llvm::MCOperand &InstructionInstance::getValueFor(const Variable &Var) {
109+
llvm::MCOperand &InstructionBuilder::getValueFor(const Variable &Var) {
110110
return VariableValues[Var.Index];
111111
}
112112

113113
const llvm::MCOperand &
114-
InstructionInstance::getValueFor(const Variable &Var) const {
114+
InstructionBuilder::getValueFor(const Variable &Var) const {
115115
return VariableValues[Var.Index];
116116
}
117117

118-
llvm::MCOperand &InstructionInstance::getValueFor(const Operand &Op) {
118+
llvm::MCOperand &InstructionBuilder::getValueFor(const Operand &Op) {
119119
assert(Op.VariableIndex >= 0);
120120
return getValueFor(Instr.Variables[Op.VariableIndex]);
121121
}
122122

123123
const llvm::MCOperand &
124-
InstructionInstance::getValueFor(const Operand &Op) const {
124+
InstructionBuilder::getValueFor(const Operand &Op) const {
125125
assert(Op.VariableIndex >= 0);
126126
return getValueFor(Instr.Variables[Op.VariableIndex]);
127127
}
@@ -131,7 +131,7 @@ static void randomize(const Instruction &Instr, const Variable &Var,
131131
llvm::MCOperand &AssignedValue,
132132
const llvm::BitVector &ForbiddenRegs);
133133

134-
bool InstructionInstance::hasImmediateVariables() const {
134+
bool InstructionBuilder::hasImmediateVariables() const {
135135
return llvm::any_of(Instr.Variables, [this](const Variable &Var) {
136136
assert(!Var.TiedOperands.empty());
137137
const unsigned OpIndex = Var.TiedOperands[0];
@@ -141,7 +141,7 @@ bool InstructionInstance::hasImmediateVariables() const {
141141
});
142142
}
143143

144-
void InstructionInstance::randomizeUnsetVariables(
144+
void InstructionBuilder::randomizeUnsetVariables(
145145
const llvm::BitVector &ForbiddenRegs) {
146146
for (const Variable &Var : Instr.Variables) {
147147
llvm::MCOperand &AssignedValue = getValueFor(Var);
@@ -150,7 +150,7 @@ void InstructionInstance::randomizeUnsetVariables(
150150
}
151151
}
152152

153-
llvm::MCInst InstructionInstance::build() const {
153+
llvm::MCInst InstructionBuilder::build() const {
154154
llvm::MCInst Result;
155155
Result.setOpcode(Instr.Description->Opcode);
156156
for (const auto &Op : Instr.Operands)
@@ -261,10 +261,10 @@ static void randomize(const Instruction &Instr, const Variable &Var,
261261
}
262262

263263
static void setRegisterOperandValue(const RegisterOperandAssignment &ROV,
264-
InstructionInstance &II) {
264+
InstructionBuilder &IB) {
265265
assert(ROV.Op);
266266
if (ROV.Op->IsExplicit) {
267-
auto &AssignedValue = II.getValueFor(*ROV.Op);
267+
auto &AssignedValue = IB.getValueFor(*ROV.Op);
268268
if (AssignedValue.isValid()) {
269269
assert(AssignedValue.isReg() && AssignedValue.getReg() == ROV.Reg);
270270
return;
@@ -285,12 +285,12 @@ size_t randomBit(const llvm::BitVector &Vector) {
285285
}
286286

287287
void setRandomAliasing(const AliasingConfigurations &AliasingConfigurations,
288-
InstructionInstance &DefII, InstructionInstance &UseII) {
288+
InstructionBuilder &DefIB, InstructionBuilder &UseIB) {
289289
assert(!AliasingConfigurations.empty());
290290
assert(!AliasingConfigurations.hasImplicitAliasing());
291291
const auto &RandomConf = randomElement(AliasingConfigurations.Configurations);
292-
setRegisterOperandValue(randomElement(RandomConf.Defs), DefII);
293-
setRegisterOperandValue(randomElement(RandomConf.Uses), UseII);
292+
setRegisterOperandValue(randomElement(RandomConf.Defs), DefIB);
293+
setRegisterOperandValue(randomElement(RandomConf.Uses), UseIB);
294294
}
295295

296296
void DumpMCOperand(const llvm::MCRegisterInfo &MCRegisterInfo,

‎llvm/tools/llvm-exegesis/lib/MCInstrDescView.h

+11-11
Original file line numberDiff line numberDiff line change
@@ -39,7 +39,7 @@ struct Variable {
3939
llvm::SmallVector<unsigned, 2> TiedOperands;
4040
llvm::MCOperand AssignedValue;
4141
// The index of this Variable in Instruction.Variables and its associated
42-
// Value in InstructionInstance.VariableValues.
42+
// Value in InstructionBuilder.VariableValues.
4343
unsigned Index = -1;
4444
};
4545

@@ -82,14 +82,14 @@ struct Instruction {
8282
llvm::BitVector UseRegisters; // The union of the aliased use registers.
8383
};
8484

85-
// An instance of an Instruction holding values for each of its Variables.
86-
struct InstructionInstance {
87-
InstructionInstance(const Instruction &Instr);
85+
// A builder for an Instruction holding values for each of its Variables.
86+
struct InstructionBuilder {
87+
InstructionBuilder(const Instruction &Instr);
8888

89-
InstructionInstance(const InstructionInstance &);
90-
InstructionInstance &operator=(const InstructionInstance &);
91-
InstructionInstance(InstructionInstance &&);
92-
InstructionInstance &operator=(InstructionInstance &&);
89+
InstructionBuilder(const InstructionBuilder &);
90+
InstructionBuilder &operator=(const InstructionBuilder &);
91+
InstructionBuilder(InstructionBuilder &&);
92+
InstructionBuilder &operator=(InstructionBuilder &&);
9393

9494
unsigned getOpcode() const;
9595
llvm::MCOperand &getValueFor(const Variable &Var);
@@ -102,7 +102,7 @@ struct InstructionInstance {
102102
// Do not use any of the registers in `ForbiddenRegs`.
103103
void randomizeUnsetVariables(const llvm::BitVector &ForbiddenRegs);
104104

105-
// Returns the instance as an llvm::MCInst. The InstructionInstance must be
105+
// Returns the instance as an llvm::MCInst. The InstructionBuilder must be
106106
// fully allocated (no invalid variables).
107107
llvm::MCInst build() const;
108108

@@ -129,7 +129,7 @@ struct SnippetPrototype {
129129
// If the prototype uses the provided scratch memory, the register in which
130130
// the pointer to this memory is passed in to the function.
131131
unsigned ScratchSpaceReg = 0;
132-
std::vector<InstructionInstance> Snippet;
132+
std::vector<InstructionBuilder> Snippet;
133133
};
134134

135135
// Represents the assignment of a Register to an Operand.
@@ -186,7 +186,7 @@ size_t randomBit(const llvm::BitVector &Vector);
186186
// Picks a random configuration, then selects a random def and a random use from
187187
// it and finally set the selected values in the provided InstructionInstances.
188188
void setRandomAliasing(const AliasingConfigurations &AliasingConfigurations,
189-
InstructionInstance &DefII, InstructionInstance &UseII);
189+
InstructionBuilder &DefIB, InstructionBuilder &UseIB);
190190

191191
// Writes MCInst to OS.
192192
// This is not assembly but the internal LLVM's name for instructions and

‎llvm/tools/llvm-exegesis/lib/Target.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -48,7 +48,7 @@ class ExegesisTarget {
4848
}
4949

5050
// Fills memory operands with references to the address at [Reg] + Offset.
51-
virtual void fillMemoryOperands(InstructionInstance &II, unsigned Reg,
51+
virtual void fillMemoryOperands(InstructionBuilder &IB, unsigned Reg,
5252
unsigned Offset) const {
5353
llvm_unreachable(
5454
"fillMemoryOperands() requires getScratchMemoryRegister() > 0");

‎llvm/tools/llvm-exegesis/lib/Uops.cpp

+16-16
Original file line numberDiff line numberDiff line change
@@ -126,23 +126,23 @@ UopsBenchmarkRunner::~UopsBenchmarkRunner() = default;
126126

127127
void UopsBenchmarkRunner::instantiateMemoryOperands(
128128
const unsigned ScratchSpaceReg,
129-
std::vector<InstructionInstance> &Snippet) const {
129+
std::vector<InstructionBuilder> &Snippet) const {
130130
if (ScratchSpaceReg == 0)
131-
return; // no memory operands.
131+
return; // no memory operands.
132132
const auto &ET = State.getExegesisTarget();
133133
const unsigned MemStep = ET.getMaxMemoryAccessSize();
134134
const size_t OriginalSnippetSize = Snippet.size();
135135
size_t I = 0;
136-
for (InstructionInstance &II : Snippet) {
137-
ET.fillMemoryOperands(II, ScratchSpaceReg, I * MemStep);
136+
for (InstructionBuilder &IB : Snippet) {
137+
ET.fillMemoryOperands(IB, ScratchSpaceReg, I * MemStep);
138138
++I;
139139
}
140140

141141
while (Snippet.size() < kMinNumDifferentAddresses) {
142-
InstructionInstance II = Snippet[I % OriginalSnippetSize];
143-
ET.fillMemoryOperands(II, ScratchSpaceReg, I * MemStep);
142+
InstructionBuilder IB = Snippet[I % OriginalSnippetSize];
143+
ET.fillMemoryOperands(IB, ScratchSpaceReg, I * MemStep);
144144
++I;
145-
Snippet.push_back(std::move(II));
145+
Snippet.push_back(std::move(IB));
146146
}
147147
assert(I * MemStep < ScratchSpace::kSize && "not enough scratch space");
148148
}
@@ -176,16 +176,16 @@ UopsBenchmarkRunner::generatePrototype(unsigned Opcode) const {
176176
}
177177

178178
const AliasingConfigurations SelfAliasing(Instr, Instr);
179-
InstructionInstance II(Instr);
179+
InstructionBuilder IB(Instr);
180180
if (SelfAliasing.empty()) {
181181
Prototype.Explanation = "instruction is parallel, repeating a random one.";
182-
Prototype.Snippet.push_back(std::move(II));
182+
Prototype.Snippet.push_back(std::move(IB));
183183
instantiateMemoryOperands(Prototype.ScratchSpaceReg, Prototype.Snippet);
184184
return std::move(Prototype);
185185
}
186186
if (SelfAliasing.hasImplicitAliasing()) {
187187
Prototype.Explanation = "instruction is serial, repeating a random one.";
188-
Prototype.Snippet.push_back(std::move(II));
188+
Prototype.Snippet.push_back(std::move(IB));
189189
instantiateMemoryOperands(Prototype.ScratchSpaceReg, Prototype.Snippet);
190190
return std::move(Prototype);
191191
}
@@ -205,9 +205,9 @@ UopsBenchmarkRunner::generatePrototype(unsigned Opcode) const {
205205
for (const llvm::MCPhysReg Reg : Op.Tracker->sourceBits().set_bits()) {
206206
if (ScratchSpaceAliasedRegs && ScratchSpaceAliasedRegs->test(Reg))
207207
continue; // Do not use the scratch memory address register.
208-
InstructionInstance TmpII = II;
209-
TmpII.getValueFor(*Var) = llvm::MCOperand::createReg(Reg);
210-
Prototype.Snippet.push_back(std::move(TmpII));
208+
InstructionBuilder TmpIB = IB;
209+
TmpIB.getValueFor(*Var) = llvm::MCOperand::createReg(Reg);
210+
Prototype.Snippet.push_back(std::move(TmpIB));
211211
}
212212
instantiateMemoryOperands(Prototype.ScratchSpaceReg, Prototype.Snippet);
213213
return std::move(Prototype);
@@ -224,7 +224,7 @@ UopsBenchmarkRunner::generatePrototype(unsigned Opcode) const {
224224
assert(PossibleRegisters.any() && "No register left to choose from");
225225
const auto RandomReg = randomBit(PossibleRegisters);
226226
Defs.set(RandomReg);
227-
II.getValueFor(Op) = llvm::MCOperand::createReg(RandomReg);
227+
IB.getValueFor(Op) = llvm::MCOperand::createReg(RandomReg);
228228
}
229229
}
230230
// And pick random use values that are not reserved and don't alias with defs.
@@ -239,12 +239,12 @@ UopsBenchmarkRunner::generatePrototype(unsigned Opcode) const {
239239
remove(PossibleRegisters, DefAliases);
240240
assert(PossibleRegisters.any() && "No register left to choose from");
241241
const auto RandomReg = randomBit(PossibleRegisters);
242-
II.getValueFor(Op) = llvm::MCOperand::createReg(RandomReg);
242+
IB.getValueFor(Op) = llvm::MCOperand::createReg(RandomReg);
243243
}
244244
}
245245
Prototype.Explanation =
246246
"instruction has no tied variables picking Uses different from defs";
247-
Prototype.Snippet.push_back(std::move(II));
247+
Prototype.Snippet.push_back(std::move(IB));
248248
instantiateMemoryOperands(Prototype.ScratchSpaceReg, Prototype.Snippet);
249249
return std::move(Prototype);
250250
}

‎llvm/tools/llvm-exegesis/lib/Uops.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -62,7 +62,7 @@ class UopsBenchmarkRunner : public BenchmarkRunner {
6262
// mov eax, [rdi + 256]
6363
void
6464
instantiateMemoryOperands(unsigned ScratchSpaceReg,
65-
std::vector<InstructionInstance> &Snippet) const;
65+
std::vector<InstructionBuilder> &Snippet) const;
6666
};
6767

6868
} // namespace exegesis

0 commit comments

Comments
 (0)
Please sign in to comment.