AMDGPU/R600: Add MOV instructions to BFE patterns

[jvesely]

Summary

R600 can't handle immediates for BFE, the movs will be eliminated later.
Fixes powr/pow regressions n r600 since r334817.

[jvesely]

v2: copy tests to a new file

[arsenm]

LGTM

lib/Target/AMDGPU/AMDGPUInstructions.td

   // x & ((1 << y) - 1)
   def : AMDGPUPat <
     (and i32:$src, (add_oneuse (shl_oneuse 1, i32:$width), -1)),
-    (UBFE $src, (i32 0), $width)
+    (UBFE $src, (MOV (i32 0)), $width)
   >;
 
   // x & ~(-1 << y)
   def : AMDGPUPat <
     (and i32:$src, (xor_oneuse (shl_oneuse -1, i32:$width), -1)),
-    (UBFE $src, (i32 0), $width)
+    (UBFE $src, (MOV (i32 0)), $width)
   >;
 
   // x & (-1 >> (bitwidth - y))
   def : AMDGPUPat <
     (and i32:$src, (srl_oneuse -1, (sub 32, i32:$width))),
-    (UBFE $src, (i32 0), $width)
+    (UBFE $src, (MOV (i32 0)), $width)
   >;
 
   // x << (bitwidth - y) >> (bitwidth - y)
   def : AMDGPUPat <
     (srl (shl_oneuse i32:$src, (sub 32, i32:$width)), (sub 32, i32:$width)),
-    (UBFE $src, (i32 0), $width)
+    (UBFE $src, (MOV (i32 0)), $width)
   >;
 
   def : AMDGPUPat <
     (sra (shl_oneuse i32:$src, (sub 32, i32:$width)), (sub 32, i32:$width)),
-    (SBFE $src, (i32 0), $width)
+    (SBFE $src, (MOV (i32 0)), $width)
   >;
 }
 

test/CodeGen/AMDGPU/extract-lowbits.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -march=amdgcn -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=AMDGPU %s
 ; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=AMDGPU %s
+; RUN: llc -march=r600 -mtriple=r600-- -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=R600 -check-prefix=EG -check-prefix=AMDGPU %s
+; RUN: llc -march=r600 -mtriple=r600-- -mcpu=cayman -verify-machineinstrs < %s | FileCheck -check-prefix=R600 -check-prefix=CM -check-prefix=AMDGPU %s
 
 ; Loosely based on test/CodeGen/{X86,AArch64}/extract-lowbits.ll,
 ; but with all 64-bit tests, and tests with loads dropped.

 ; GCN-NEXT:   v_bfe_u32 [[RES:v[0-9]*]], s[[VAL]], 0, [[BITS]]
 ; SI-NEXT:    buffer_store_dword [[RES]]
 ; VI:         flat_store_dword {{.*}}, [[RES]]
+
+; EG:         MEM_RAT_CACHELESS STORE_RAW [[RET:T[0-1]+\.[XYZW]]]
+; CM:         MEM_RAT_CACHELESS STORE_DWORD [[RET:T[0-1]+\.[XYZW]]]
+; R600:       BFE_UINT {{\*?}} [[RET]], KC0[2].Y, 0.0, KC0[2].Z
 define amdgpu_kernel void @bzhi32_a0(i32 %val, i32 %numlowbits, i32 addrspace(1)* %out) {
   %onebit = shl i32 1, %numlowbits
   %mask = add nsw i32 %onebit, -1

 ; GCN-NEXT:   v_bfe_u32 [[RES:v[0-9]*]], s[[VAL]], 0, [[BITS]]
 ; SI-NEXT:    buffer_store_dword [[RES]]
 ; VI:         flat_store_dword {{.*}}, [[RES]]
+
+; EG:         MEM_RAT_CACHELESS STORE_RAW [[RET:T[0-1]+\.[XYZW]]]
+; CM:         MEM_RAT_CACHELESS STORE_DWORD [[RET:T[0-1]+\.[XYZW]]]
+; R600:       BFE_UINT {{\*?}} [[RET]], KC0[2].Y, 0.0, KC0[2].Z
 define amdgpu_kernel void @bzhi32_a1_indexzext(i32 %val, i8 zeroext %numlowbits, i32 addrspace(1)* %out) {
   %conv = zext i8 %numlowbits to i32
   %onebit = shl i32 1, %conv

 ; GCN-NEXT:   v_bfe_u32 [[RES:v[0-9]*]], s[[VAL]], 0, [[BITS]]
 ; SI-NEXT:    buffer_store_dword [[RES]]
 ; VI:         flat_store_dword {{.*}}, [[RES]]
+
+; EG:         MEM_RAT_CACHELESS STORE_RAW [[RET:T[0-1]+\.[XYZW]]]
+; CM:         MEM_RAT_CACHELESS STORE_DWORD [[RET:T[0-1]+\.[XYZW]]]
+; R600:       BFE_UINT {{\*?}} [[RET]], KC0[2].Y, 0.0, KC0[2].Z
 define amdgpu_kernel void @bzhi32_a4_commutative(i32 %val, i32 %numlowbits, i32 addrspace(1)* %out) {
   %onebit = shl i32 1, %numlowbits
   %mask = add nsw i32 %onebit, -1

 ; GCN-NEXT:   v_bfe_u32 [[RES:v[0-9]*]], s[[VAL]], 0, [[BITS]]
 ; SI-NEXT:    buffer_store_dword [[RES]]
 ; VI:         flat_store_dword {{.*}}, [[RES]]
+
+; EG:         MEM_RAT_CACHELESS STORE_RAW [[RET:T[0-1]+\.[XYZW]]]
+; CM:         MEM_RAT_CACHELESS STORE_DWORD [[RET:T[0-1]+\.[XYZW]]]
+; R600:       BFE_UINT {{\*?}} [[RET]], KC0[2].Y, 0.0, KC0[2].Z
 define amdgpu_kernel void @bzhi32_b0(i32 %val, i32 %numlowbits, i32 addrspace(1)* %out) {
   %notmask = shl i32 -1, %numlowbits
   %mask = xor i32 %notmask, -1

 ; GCN-NEXT:   v_bfe_u32 [[RES:v[0-9]*]], s[[VAL]], 0, [[BITS]]
 ; SI-NEXT:    buffer_store_dword [[RES]]
 ; VI:         flat_store_dword {{.*}}, [[RES]]
+
+; EG:         MEM_RAT_CACHELESS STORE_RAW [[RET:T[0-1]+\.[XYZW]]]
+; CM:         MEM_RAT_CACHELESS STORE_DWORD [[RET:T[0-1]+\.[XYZW]]]
+; R600:       BFE_UINT {{\*?}} [[RET]], KC0[2].Y, 0.0, KC0[2].Z
 define amdgpu_kernel void @bzhi32_b1_indexzext(i32 %val, i8 zeroext %numlowbits, i32 addrspace(1)* %out) {
   %conv = zext i8 %numlowbits to i32
   %notmask = shl i32 -1, %conv

 ; GCN-NEXT:   v_bfe_u32 [[RES:v[0-9]*]], s[[VAL]], 0, [[BITS]]
 ; SI-NEXT:    buffer_store_dword [[RES]]
 ; VI:         flat_store_dword {{.*}}, [[RES]]
+
+; EG:         MEM_RAT_CACHELESS STORE_RAW [[RET:T[0-1]+\.[XYZW]]]
+; CM:         MEM_RAT_CACHELESS STORE_DWORD [[RET:T[0-1]+\.[XYZW]]]
+; R600:       BFE_UINT {{\*?}} [[RET]], KC0[2].Y, 0.0, KC0[2].Z
 define amdgpu_kernel void @bzhi32_b4_commutative(i32 %val, i32 %numlowbits, i32 addrspace(1)* %out) {
   %notmask = shl i32 -1, %numlowbits
   %mask = xor i32 %notmask, -1

 ; GCN-NEXT:   v_bfe_u32 [[RES:v[0-9]*]], s[[VAL]], 0, [[BITS]]
 ; SI-NEXT:    buffer_store_dword [[RES]]
 ; VI:         flat_store_dword {{.*}}, [[RES]]
+
+; EG:         MEM_RAT_CACHELESS STORE_RAW [[RET:T[0-1]+\.[XYZW]]]
+; CM:         MEM_RAT_CACHELESS STORE_DWORD [[RET:T[0-1]+\.[XYZW]]]
+; R600:       BFE_UINT {{\*?}} [[RET]], KC0[2].Y, 0.0, KC0[2].Z
 define amdgpu_kernel void @bzhi32_c0(i32 %val, i32 %numlowbits, i32 addrspace(1)* %out) {
   %numhighbits = sub i32 32, %numlowbits
   %mask = lshr i32 -1, %numhighbits

 ; GCN:        v_mov_b32_e32 [[RES:v[0-9]+]], [[SRES]]
 ; SI:         buffer_store_dword [[RES]]
 ; VI:         flat_store_dword {{.*}}, [[RES]]
+
+; EG:         MEM_RAT_CACHELESS STORE_RAW [[RET:T[0-1]+\.[XYZW]]]
+; CM:         MEM_RAT_CACHELESS STORE_DWORD [[RET:T[0-1]+\.[XYZW]]]
+; R600:       SUB_INT {{\*?}} [[SUBR:T[0-9]+]].[[SUBC:[XYZW]]], literal.x, KC0[2].Z
+; R600-NEXT:  32
+; R600-NEXT:  AND_INT {{\*?}} {{T[0-9]+}}.[[AND1C:[XYZW]]], {{T[0-9]+|PV}}.[[SUBC]], literal.x
+; R600-NEXT:  255
+; R600:       LSHR {{\*?}} {{T[0-9]}}.[[LSHRC:[XYZW]]], literal.x, {{T[0-9]+|PV}}.[[AND1C]]
+; R600-NEXT:  -1
+; R600-NEXT:  AND_INT {{[* ]*}}[[RET]], {{T[0-9]+|PV}}.[[LSHRC]], KC0[2].Y
 define amdgpu_kernel void @bzhi32_c1_indexzext(i32 %val, i8 %numlowbits, i32 addrspace(1)* %out) {
   %numhighbits = sub i8 32, %numlowbits
   %sh_prom = zext i8 %numhighbits to i32

 ; GCN-NEXT:   v_bfe_u32 [[RES:v[0-9]*]], s[[VAL]], 0, [[BITS]]
 ; SI-NEXT:    buffer_store_dword [[RES]]
 ; VI:         flat_store_dword {{.*}}, [[RES]]
+
+; EG:         MEM_RAT_CACHELESS STORE_RAW [[RET:T[0-1]+\.[XYZW]]]
+; CM:         MEM_RAT_CACHELESS STORE_DWORD [[RET:T[0-1]+\.[XYZW]]]
+; R600:       BFE_UINT {{\*?}} [[RET]], KC0[2].Y, 0.0, KC0[2].Z
 define amdgpu_kernel void @bzhi32_c4_commutative(i32 %val, i32 %numlowbits, i32 addrspace(1)* %out) {
   %numhighbits = sub i32 32, %numlowbits
   %mask = lshr i32 -1, %numhighbits

 ; GCN-NEXT:   v_bfe_u32 [[RES:v[0-9]*]], s[[VAL]], 0, [[BITS]]
 ; SI-NEXT:    buffer_store_dword [[RES]]
 ; VI:         flat_store_dword {{.*}}, [[RES]]
+
+; EG:         MEM_RAT_CACHELESS STORE_RAW [[RET:T[0-1]+\.[XYZW]]]
+; CM:         MEM_RAT_CACHELESS STORE_DWORD [[RET:T[0-1]+\.[XYZW]]]
+; R600:       BFE_UINT {{\*?}} [[RET]], KC0[2].Y, 0.0, KC0[2].Z
 define amdgpu_kernel void @bzhi32_d0(i32 %val, i32 %numlowbits, i32 addrspace(1)* %out) {
   %numhighbits = sub i32 32, %numlowbits
   %highbitscleared = shl i32 %val, %numhighbits

 ; GCN:        v_mov_b32_e32 [[RES:v[0-9]+]], [[SHR]]
 ; SI:         buffer_store_dword [[RES]]
 ; VI:         flat_store_dword {{.*}}, [[RES]]
+
+; EG:         MEM_RAT_CACHELESS STORE_RAW [[RET:T[0-1]+\.[XYZW]]]
+; CM:         MEM_RAT_CACHELESS STORE_DWORD [[RET:T[0-1]+\.[XYZW]]]
+; R600:       SUB_INT {{\*?}} [[SUBR:T[0-9]+]].[[SUBC:[XYZW]]], literal.x, KC0[2].Z
+; R600-NEXT:  32
+; R600-NEXT:  AND_INT {{\*?}} [[AND:T[0-9]+\.[XYZW]]], {{T[0-9]+|PV}}.[[SUBC]], literal.x
+; R600-NEXT:  255
+; R600:       LSHL {{\*?}} {{T[0-9]}}.[[LSHLC:[XYZW]]], KC0[2].Y, {{T[0-9]+|PV}}.[[AND1C]]
+; R600:       LSHR {{[* ]*}}[[RET]], {{T[0-9]+|PV}}.[[LSHLC]], [[AND]]
 define amdgpu_kernel void @bzhi32_d1_indexzext(i32 %val, i8 %numlowbits, i32 addrspace(1)* %out) {
   %numhighbits = sub i8 32, %numlowbits
   %sh_prom = zext i8 %numhighbits to i32