This is an archive of the discontinued LLVM Phabricator instance.

Differential D49625

AMDGPU/GlobalISel: Define instruction mapping for G_INSERT
ClosedPublic

Authored by tstellar on Jul 20 2018, 5:03 PM.

Details

Reviewers
arsenm
Commits
rG8adc86a7dc4a: AMDGPU/GlobalISel: Define instruction mapping for G_INSERT
rL339491: AMDGPU/GlobalISel: Define instruction mapping for G_INSERT

Diff Detail

Repository
rL LLVM

Event Timeline

tstellar created this revision.Jul 20 2018, 5:03 PM
Herald added subscribers: t-tye, tpr, dstuttard and 6 others. · View Herald TranscriptJul 20 2018, 5:03 PM
arsenm accepted this revision.Jul 21 2018, 12:18 AM

LGTM

This revision is now accepted and ready to land.Jul 21 2018, 12:18 AM
Closed by commit rL339491: AMDGPU/GlobalISel: Define instruction mapping for G_INSERT (authored by tstellar). · Explain WhyAug 10 2018, 5:52 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
AMDGPU/
14 lines
test/
CodeGen/
AMDGPU/
GlobalISel/
83 lines

Diff 160217

llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

Show First 20 Lines • Show All 187 Lines • ▼ Show 20 Linesstatic bool isInstrUniform(const MachineInstr &MI) {
const MachineMemOperand *MMO = *MI.memoperands_begin(); const MachineMemOperand *MMO = *MI.memoperands_begin();
return AMDGPUInstrInfo::isUniformMMO(MMO); return AMDGPUInstrInfo::isUniformMMO(MMO);
} }
bool AMDGPURegisterBankInfo::isSALUMapping(const MachineInstr &MI) const { bool AMDGPURegisterBankInfo::isSALUMapping(const MachineInstr &MI) const {
const MachineFunction &MF = *MI.getParent()->getParent(); const MachineFunction &MF = *MI.getParent()->getParent();
const MachineRegisterInfo &MRI = MF.getRegInfo(); const MachineRegisterInfo &MRI = MF.getRegInfo();
for (unsigned i = 0, e = MI.getNumOperands();i != e; ++i) { for (unsigned i = 0, e = MI.getNumOperands();i != e; ++i) {
if (!MI.getOperand(i).isReg())
continue;
unsigned Reg = MI.getOperand(i).getReg(); unsigned Reg = MI.getOperand(i).getReg();
const RegisterBank *Bank = getRegBank(Reg, MRI, *TRI); const RegisterBank *Bank = getRegBank(Reg, MRI, *TRI);
if (Bank && Bank->getID() != AMDGPU::SGPRRegBankID) if (Bank && Bank->getID() != AMDGPU::SGPRRegBankID)
return false; return false;
} }
return true; return true;
} }
▲ Show 20 Lines • Show All 122 Lines • ▼ Show 20 Lines case AMDGPU::G_IMPLICIT_DEF: {
break; break;
} }
case AMDGPU::G_FCONSTANT: case AMDGPU::G_FCONSTANT:
case AMDGPU::G_CONSTANT: { case AMDGPU::G_CONSTANT: {
unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(); unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size); OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size);
break; break;
} }
case AMDGPU::G_INSERT: {
unsigned BankID = isSALUMapping(MI) ? AMDGPU::SGPRRegBankID :
AMDGPU::VGPRRegBankID;
unsigned DstSize = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
unsigned SrcSize = getSizeInBits(MI.getOperand(1).getReg(), MRI, *TRI);
unsigned EltSize = getSizeInBits(MI.getOperand(2).getReg(), MRI, *TRI);
OpdsMapping[0] = AMDGPU::getValueMapping(BankID, DstSize);
OpdsMapping[1] = AMDGPU::getValueMapping(BankID, SrcSize);
OpdsMapping[2] = AMDGPU::getValueMapping(BankID, EltSize);
OpdsMapping[3] = nullptr;
break;
}
case AMDGPU::G_EXTRACT: { case AMDGPU::G_EXTRACT: {
unsigned BankID = getRegBankID(MI.getOperand(1).getReg(), MRI, *TRI); unsigned BankID = getRegBankID(MI.getOperand(1).getReg(), MRI, *TRI);
unsigned DstSize = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI); unsigned DstSize = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
unsigned SrcSize = getSizeInBits(MI.getOperand(1).getReg(), MRI, *TRI); unsigned SrcSize = getSizeInBits(MI.getOperand(1).getReg(), MRI, *TRI);
OpdsMapping[0] = AMDGPU::getValueMapping(BankID, DstSize); OpdsMapping[0] = AMDGPU::getValueMapping(BankID, DstSize);
OpdsMapping[1] = AMDGPU::getValueMapping(BankID, SrcSize); OpdsMapping[1] = AMDGPU::getValueMapping(BankID, SrcSize);
OpdsMapping[2] = nullptr; OpdsMapping[2] = nullptr;
break; break;
▲ Show 20 Lines • Show All 196 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
---
name: insert_lo32_i64_ss
legalized: true
body: |
bb.0:
liveins: $sgpr0_sgpr1, $sgpr2
; CHECK-LABEL: name: insert_lo32_i64_ss
; CHECK: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
; CHECK: [[INSERT:%[0-9]+]]:sgpr(s64) = G_INSERT [[COPY]], [[COPY1]](s32), 0
%0:_(s64) = COPY $sgpr0_sgpr1
%1:_(s32) = COPY $sgpr2
%2:_(s64) = G_INSERT %0, %1, 0
...
---
name: insert_lo32_i64_sv
legalized: true
body: |
bb.0:
liveins: $sgpr0_sgpr1, $vgpr2
; CHECK-LABEL: name: insert_lo32_i64_sv
; CHECK: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64)
; CHECK: [[INSERT:%[0-9]+]]:vgpr(s64) = G_INSERT [[COPY2]], [[COPY1]](s32), 0
%0:_(s64) = COPY $sgpr0_sgpr1
%1:_(s32) = COPY $vgpr2
%2:_(s64) = G_INSERT %0, %1, 0
...
---
name: insert_lo32_i64_vs
legalized: true
body: |
bb.0:
liveins: $vgpr0_vgpr1, $sgpr2
; CHECK-LABEL: name: insert_lo32_i64_vs
; CHECK: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; CHECK: [[INSERT:%[0-9]+]]:vgpr(s64) = G_INSERT [[COPY]], [[COPY2]](s32), 0
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s32) = COPY $sgpr2
%2:_(s64) = G_INSERT %0, %1, 0
...
---
name: insert_lo32_i64_vv
legalized: true
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2
; CHECK-LABEL: name: insert_lo32_i64_vv
; CHECK: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
; CHECK: [[INSERT:%[0-9]+]]:sgpr(s64) = G_INSERT [[COPY]], [[COPY1]](s32), 0
%0:_(s64) = COPY $sgpr0_sgpr1
%1:_(s32) = COPY $sgpr2
%2:_(s64) = G_INSERT %0, %1, 0
...
---
name: insert_lo32_i96_v
legalized: true
body: |
bb.0:
liveins: $vgpr0_vgpr1_vgpr2, $vgpr3
; CHECK-LABEL: name: insert_lo32_i96_v
; CHECK: [[COPY:%[0-9]+]]:vgpr(s96) = COPY $vgpr0_vgpr1_vgpr2
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr3
; CHECK: [[INSERT:%[0-9]+]]:vgpr(s96) = G_INSERT [[COPY]], [[COPY1]](s32), 0
%0:_(s96) = COPY $vgpr0_vgpr1_vgpr2
%1:_(s32) = COPY $vgpr3
%2:_(s96) = G_INSERT %0, %1, 0
...