AMDGPU/GlobalISel: Fix crash in regbankselect on non-power-of-2 types

[arsenm]

LGTM

llvm/trunk/lib/Target/AMDGPU/AMDGPUGenRegisterBankInfo.def

const RegisterBankInfo::ValueMapping *getValueMapping(unsigned BankID,
   case 1:
     Idx = BankID == AMDGPU::SCCRegBankID ? PM_SGPR1 : PM_VGPR1;
     break;
   case 96:
     Idx = BankID == AMDGPU::SGPRRegBankID ? PM_SGPR96 : PM_VGPR96;
     break;
   default:
     Idx = BankID == AMDGPU::VGPRRegBankID ? VGPRStartIdx : SGPRStartIdx;
-    Idx += llvm::countTrailingZeros(Size);
+    Idx += Log2_32_Ceil(Size);
     break;
   }
   return &ValMappings[Idx];
 }
 
 } // End AMDGPU namespace.
 } // End llvm namespace.

llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect.mir

 # RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=regbankselect %s -verify-machineinstrs -o - | FileCheck %s
 
 # REQUIRES: global-isel
 
 --- |
   define amdgpu_kernel void @load_constant(i32 addrspace(4)* %ptr0) { ret void }
   define amdgpu_kernel void @load_global_uniform(i32 addrspace(1)* %ptr1) {
     %tmp0 = load i32, i32 addrspace(1)* %ptr1
     ret void
   }
   define amdgpu_kernel void @load_global_non_uniform(i32 addrspace(1)* %ptr2) {
     %tmp0 = call i32 @llvm.amdgcn.workitem.id.x() #0
     %tmp1 = getelementptr i32, i32 addrspace(1)* %ptr2, i32 %tmp0
     %tmp2 = load i32, i32 addrspace(1)* %tmp1
     ret void
   }
+  define void @non_power_of_2() { ret void }
   declare i32 @llvm.amdgcn.workitem.id.x() #0
   attributes #0 = { nounwind readnone }
 ...
 
 ---
 name : load_constant
 legalized: true
 

 
 
 body: |
   bb.0:
     liveins: $sgpr0_sgpr1
     %0:_(p1) = COPY $sgpr0_sgpr1
     %1:_(s32) = G_LOAD %0 :: (load 4 from %ir.tmp1)
 ...
+
+---
+name: non_power_of_2
+legalized: true
+
+# CHECK-LABEL: name: non_power_of_2
+# CHECK: [[S448:%[0-9]+]]:sgpr(s448) = G_IMPLICIT_DEF
+# CHECK: sgpr(s32) = G_EXTRACT [[S448]](s448), 0
+
+body: |
+  bb.0:
+    %0:_(s448) = G_IMPLICIT_DEF
+    %1:_(s32) = G_EXTRACT %0:_(s448), 0
+    $sgpr0 = COPY %1:_(s32)
+    SI_RETURN_TO_EPILOG $sgpr0
+...