This is an archive of the discontinued LLVM Phabricator instance.

Differential D49601

AMDGPU/GlobalISel: Legalize G_INSERT
ClosedPublic

Authored by tstellar on Jul 20 2018, 8:13 AM.

Details

Reviewers
arsenm
Commits
rGb7f19e6d1e7b: AMDGPU/GlobalISel: Legalize G_INSERT
rL337798: AMDGPU/GlobalISel: Legalize G_INSERT

Diff Detail

Repository
rL LLVM

Event Timeline

tstellar created this revision.Jul 20 2018, 8:13 AM
Herald added subscribers: t-tye, tpr, dstuttard and 6 others. · View Herald TranscriptJul 20 2018, 8:13 AM
Harbormaster completed remote builds in B20548: Diff 156490.Jul 20 2018, 8:13 AM
arsenm accepted this revision.Jul 20 2018, 8:23 AM

LGTM

This revision is now accepted and ready to land.Jul 20 2018, 8:23 AM
Closed by commit rL337798: AMDGPU/GlobalISel: Legalize G_INSERT (authored by tstellar). · Explain WhyJul 23 2018, 7:19 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
AMDGPU/
2 lines
test/
CodeGen/
AMDGPU/
GlobalISel/
123 lines

Diff 156958

llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

Show First 20 Lines • Show All 166 Lines • ▼ Show 20 Lines getActionDefinitionsBuilder(Op)
const LLT &IdxTy = Query.Types[2]; const LLT &IdxTy = Query.Types[2];
return VecTy.getSizeInBits() % 32 == 0 && return VecTy.getSizeInBits() % 32 == 0 &&
VecTy.getSizeInBits() <= 512 && VecTy.getSizeInBits() <= 512 &&
IdxTy.getSizeInBits() == 32; IdxTy.getSizeInBits() == 32;
}); });
} }
// FIXME: Doesn't handle extract of illegal sizes. // FIXME: Doesn't handle extract of illegal sizes.
getActionDefinitionsBuilder(G_EXTRACT) getActionDefinitionsBuilder({G_EXTRACT, G_INSERT})
.legalIf([=](const LegalityQuery &Query) { .legalIf([=](const LegalityQuery &Query) {
const LLT &Ty0 = Query.Types[0]; const LLT &Ty0 = Query.Types[0];
const LLT &Ty1 = Query.Types[1]; const LLT &Ty1 = Query.Types[1];
return (Ty0.getSizeInBits() % 32 == 0) && return (Ty0.getSizeInBits() % 32 == 0) &&
(Ty1.getSizeInBits() % 32 == 0); (Ty1.getSizeInBits() % 32 == 0);
}); });
// Merge/Unmerge // Merge/Unmerge
Show All 29 Lines

llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-insert.mir

# RUN: llc -mtriple=amdgcn-mesa-mesa3d -run-pass=legalizer %s -o - | FileCheck %s
---
name: test_insert_lo32_i64
body: |
bb.0.entry:
liveins: $vgpr0_vgpr1, $vgpr2
; CHECK-LABEL: name: test_insert_lo32_i64
; CHECK: %2:_(s64) = G_INSERT %0, %1(s32), 0
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s32) = COPY $vgpr2
%2:_(s64) = G_INSERT %0, %1, 0
S_ENDPGM implicit %2
...
---
name: test_insert_hi32_i64
body: |
bb.0.entry:
liveins: $vgpr0_vgpr1, $vgpr2
; CHECK-LABEL: name: test_insert_hi32_i64
; CHECK: %2:_(s64) = G_INSERT %0, %1(s32), 32
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s32) = COPY $vgpr2
%2:_(s64) = G_INSERT %0, %1, 32
S_ENDPGM implicit %2
...
---
name: test_insert_dword0_i128
body: |
bb.0.entry:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
; CHECK-LABEL: name: test_insert_dword0_i128
; CHECK: %2:_(s128) = G_INSERT %0, %1(s32), 0
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s32) = COPY $vgpr4
%2:_(s128) = G_INSERT %0, %1, 0
S_ENDPGM implicit %2
...
---
name: test_insert_dword1_i128
body: |
bb.0.entry:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
; CHECK-LABEL: name: test_insert_dword1_i128
; CHECK: %2:_(s128) = G_INSERT %0, %1(s32), 32
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s32) = COPY $vgpr4
%2:_(s128) = G_INSERT %0, %1, 32
S_ENDPGM implicit %2
...
---
name: test_insert_dword2_i128
body: |
bb.0.entry:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
; CHECK-LABEL: name: test_insert_dword2_i128
; CHECK: %2:_(s128) = G_INSERT %0, %1(s32), 64
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s32) = COPY $vgpr4
%2:_(s128) = G_INSERT %0, %1, 64
S_ENDPGM implicit %2
...
---
name: test_insert_dword3_i128
body: |
bb.0.entry:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
; CHECK-LABEL: name: test_insert_dword3_i128
; CHECK: %2:_(s128) = G_INSERT %0, %1(s32), 96
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s32) = COPY $vgpr4
%2:_(s128) = G_INSERT %0, %1, 96
S_ENDPGM implicit %2
...
---
name: test_insert_dword0_i96
body: |
bb.0.entry:
liveins: $vgpr0_vgpr1_vgpr2, $vgpr3
; CHECK-LABEL: name: test_insert_dword0_i96
; CHECK: %2:_(s96) = G_INSERT %0, %1(s32), 0
%0:_(s96) = COPY $vgpr0_vgpr1_vgpr2
%1:_(s32) = COPY $vgpr3
%2:_(s96) = G_INSERT %0, %1, 0
S_ENDPGM implicit %2
...
---
name: test_insert_dword1_i96
body: |
bb.0.entry:
liveins: $vgpr0_vgpr1_vgpr2, $vgpr3
; CHECK-LABEL: name: test_insert_dword1_i96
; CHECK: %2:_(s96) = G_INSERT %0, %1(s32), 32
%0:_(s96) = COPY $vgpr0_vgpr1_vgpr2
%1:_(s32) = COPY $vgpr3
%2:_(s96) = G_INSERT %0, %1, 32
S_ENDPGM implicit %2
...
---
name: test_insert_dword2_i96
body: |
bb.0.entry:
liveins: $vgpr0_vgpr1_vgpr2, $vgpr3
; CHECK-LABEL: name: test_insert_dword2_i96
; CHECK: %2:_(s96) = G_INSERT %0, %1(s32), 64
%0:_(s96) = COPY $vgpr0_vgpr1_vgpr2
%1:_(s32) = COPY $vgpr3
%2:_(s96) = G_INSERT %0, %1, 64
S_ENDPGM implicit %2
...