[x86/SLH] Rename and comment the main hardening function. NFC.

[chandlerc]

Summary

This provides an overview of the algorithm used to harden specific
loads. It also brings this our terminology further in line with
hardening rather than checking.

[echristo]

LGTM.

llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp

private:
 
   void hardenEdgesWithLFENCE(MachineFunction &MF);
 
   SmallVector<BlockCondInfo, 16> collectBlockCondInfo(MachineFunction &MF);
 
   SmallVector<MachineInstr *, 16>
   tracePredStateThroughCFG(MachineFunction &MF, ArrayRef<BlockCondInfo> Infos);
 
-  void checkAllLoads(MachineFunction &MF);
+  void hardenAllLoads(MachineFunction &MF);
 
   unsigned saveEFLAGS(MachineBasicBlock &MBB,
                       MachineBasicBlock::iterator InsertPt, DebugLoc Loc);
   void restoreEFLAGS(MachineBasicBlock &MBB,
                      MachineBasicBlock::iterator InsertPt, DebugLoc Loc,
                      unsigned OFReg);
 
   void mergePredStateIntoSP(MachineBasicBlock &MBB,
for (MachineBasicBlock &MBB : MF) {
       if (!MBB.isEHPad())
         continue;
       PS->SSA.AddAvailableValue(
           &MBB,
           extractPredStateFromSP(MBB, MBB.SkipPHIsAndLabels(MBB.begin()), Loc));
     }
   }
 
-  // Now check all of the loads using the predicate state.
-  checkAllLoads(MF);
+  // Now harden all of the loads in the function using the predicate state.
+  hardenAllLoads(MF);
 
   // Now rewrite all the uses of the pred state using the SSA updater so that
   // we track updates through the CFG.
   for (MachineInstr *CMovI : CMovs)
     for (MachineOperand &Op : CMovI->operands()) {
       if (!Op.isReg() || Op.getReg() != PS->InitialReg)
         continue;
 
if (MI.killsRegister(X86::EFLAGS, &TRI))
       return false;
   }
 
   // If we didn't find anything conclusive (neither definitely alive or
   // definitely dead) return whether it lives into the block.
   return MBB.isLiveIn(X86::EFLAGS);
 }
 
-void X86SpeculativeLoadHardeningPass::checkAllLoads(MachineFunction &MF) {
+/// Harden all of the loads (including implicit loads) in the function.
+///
+/// This operates in two passes. First, we analyze the loads to determine which
+/// strategy will be used to harden them: hardening the address or hardening the
+/// loaded value when loaded into a register amenable to hardening. We have to
+/// process these first because the two strategies may interact -- later
+/// hardening may change what strategy we wish to use. We also will analyze
+/// data dependencies between loads and avoid hardening those loads that are
+/// data dependent on a load with a hardened address. We also skip hardening
+/// loads already behind an LFENCE as that is sufficient to harden them against
+/// misspeculation.
+///
+/// Second, we apply the hardening steps we determined necessary in the first
+/// pass.
+///
+/// These two passes are applied to each basic block. We operate one block at
+/// a time to simplify reasoning about reachability and sequencing.
+void X86SpeculativeLoadHardeningPass::hardenAllLoads(MachineFunction &MF) {
   // If the actual checking of loads is disabled, skip doing anything here.
   if (!HardenLoads)
     return;
 
   SmallPtrSet<MachineInstr *, 16> HardenPostLoad;
   SmallPtrSet<MachineInstr *, 16> HardenLoadAddr;
 
   SmallSet<unsigned, 16> HardenedAddrRegs;