[PowerPC] Enhance the selection(ISD::VSELECT) of vector type

[• wuzish]

Summary

To make ISD::VSELECT available(legal) so long as there are altivec instruction, otherwise it's default behavior is expanding,
which is legalized at type-legalization phase. Use xxsel to match vselect if vsx is open, or use vsel.

[• wuzish]

Hi, all.
Could you please have a review if you don't mind :)?

[nemanjai]

LGTM.

[• wuzish]

Could someone commit for me since I don't have svn access. Thank you very much.

[nemanjai]

In D49531#1198338, @wuzish wrote:

Could someone commit for me since I don't have svn access. Thank you very much.

I'll commit it for you later today.

[efriedma]

llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp

590 ↗

(On Diff #160816)

I don't think Promote does the right thing here; VectorLegalizer::Promote on a VSELECT just bitcasts the operands/result, and the documentation for ISD::VSELECT say "The condition follows the BooleanContent format of the target." So DAGCombine might transform it incorrectly in some cases involving v16i8 or v8i16.

Granted, I'm not sure DAGCombine actually does any relevant transforms on the condition of a VSELECT, but it seems like a bad idea to rely on that.

[• wuzish]

Add some more detail explanation.

llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp

590 ↗

(On Diff #160816)

Well, for v16i8 the initial DAG is like this

SelectionDAG has 15 nodes:
  t0: ch = EntryToken
        t6: v16i8,ch = CopyFromReg t0, Register:v16i8 %2
        t8: v16i8,ch = CopyFromReg t0, Register:v16i8 %3
      **t10: v16i1 = setcc t6, t8, seteq:ch**
      t2: v16i8,ch = CopyFromReg t0, Register:v16i8 %0
      t4: v16i8,ch = CopyFromReg t0, Register:v16i8 %1
    t11: v16i8 = vselect t10, t2, t4
  t13: ch,glue = CopyToReg t0, Register:v16i8 $v2, t11
  t14: ch = PPCISD::RET_FLAG t13, Register:v16i8 $v2, t13:1

The setcc result type is v16i1, but legalize type phase will change it to v16i8 as you said that follow the BooleanContent format of the target. So it 's like blow.

  t0: ch = EntryToken
        t6: v16i8,ch = CopyFromReg t0, Register:v16i8 %2
        t8: v16i8,ch = CopyFromReg t0, Register:v16i8 %3
**      t15: v16i8 = setcc t6, t8, seteq:ch**
      t2: v16i8,ch = CopyFromReg t0, Register:v16i8 %0
      t4: v16i8,ch = CopyFromReg t0, Register:v16i8 %1
**    t16: v16i8 = vselect t15, t2, t4**
  t13: ch,glue = CopyToReg t0, Register:v16i8 $v2, t16
  t14: ch = PPCISD::RET_FLAG t13, Register:v16i8 $v2, t13:1

What promote does is just make v16i8 to v4i32 consistently or canonically, so that we can just write one single pattern in td file to select vselect since the xxsel instruction is suitable for all vector type like v16i8/v8i16 because it's bit selection.

After legalize operation phase:

 SelectionDAG has 19 nodes:
  t0: ch = EntryToken
            t6: v16i8,ch = CopyFromReg t0, Register:v16i8 %2
             t8: v16i8,ch = CopyFromReg t0, Register:v16i8 %3
           t15: v16i8 = setcc t6, t8, seteq:ch
 **        t17: v4i32 = bitcast t15**
           t2: v16i8,ch = CopyFromReg t0, Register:v16i8 %0
**        t18: v4i32 = bitcast t2**
           t4: v16i8,ch = CopyFromReg t0, Register:v16i8 %1
**        t19: v4i32 = bitcast t4**
 **      t20: v4i32 = vselect t17, t18, t19**
     t21: v16i8 = bitcast t20
   t13: ch,glue = CopyToReg t0, Register:v16i8 $v2, t21
   t14: ch = PPCISD::RET_FLAG t13, Register:v16i8 $v2, t13:1

[• wuzish]

It's reverted before. Reopen it.

Author: nemanjai
Date: Mon Aug 27 13:20:42 2018 UTC (4 weeks ago)
Changed paths: 6
Log Message:

[PowerPC] Revert commit r339779

This commit has caused failures in some internal benchmarks. Temporarily
reverting this patch until the issue can be diagnosed and fixed.

[• wuzish]

It should be recommitted after the patch https://reviews.llvm.org/D52449

[efriedma]

llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp

590 ↗

(On Diff #160816)

The SelectionDAG DAG is a target-independent IR, just like LLVM IR; it has target-independent opcodes with target-independent meanings. It's not defined quite as formally as LLVM IR, but the concept is the same. And DAGCombine makes transforms based on that target-independent meaning. And if the target-independent meaning for an operation is that it returns an undefined value, you can't "extend" it to return something defined just because it would be convenient for your target. (IIRC the MIPS backend tried to do this with vector shifts, and ended up with miscompiles.)

The issue here, specifically, is that ISD::VSELECT is defined as a per-element select, and the result is undefined if any of the elements is not a boolean of the correct form (on PPC, BooleanContent for a vector requires an all-zeros or all-ones value).

There are a couple of ways to solve this: one, introduce a target-specific opcode (PPCISD::XXSEL, or something like that, which has the correct semantics). Two, you could change the promotion logic; promoting a v4i32 vselect to a v16i8 vselect should be fine.

[• wuzish]

llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp

590 ↗

(On Diff #160816)

The issue here, specifically, is that ISD::VSELECT is defined as a per-element select, and the result is undefined if any of the elements is not a boolean of the correct form (on PPC, BooleanContent for a vector requires an all-zeros or all-ones value).

It's already correct form boolean content in PPC (all-ones) after the type legalization.( That's why the result type of setcc is v16i8 not v16i1).
So all vector type bitcast to v4i32 is just a kind of canonical so that we do not need to write many patterns in td.

[efriedma]

llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp

590 ↗

(On Diff #160816)

No, it's not the correct boolean content: the elements of the condition of a v4i32 VSELECT are required to have value 0x00000000 or 0xFFFFFFFF, but your v4i32 can have elements of the form 0x0000FF00, which is not a boolean.

[• wuzish]

llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp

590 ↗

(On Diff #160816)

Yes, it's not a perfect way to simply the pattern matching lazily.

It's better to write every legal pattern in td file.

[• wuzish]

I think it's a workaround that use vsel instead of xxsel for v16i8 and v8i16. So maybe we can change back in another patch after fix the encountered failures in check-all to make the selection consistently.

lib/Target/PowerPC/PPCInstrVSX.td

1159

I can not use this pattern since the register class of XXSEL operand is vsrc, and it does not accept v16i8 or v8i16 as following registerclass definition.

def VRRC : RegisterClass<"PPC",
                         [v16i8,v8i16,v4i32,v2i64,v1i128,v4f32,v2f64, f128],
                         128,
                         (add V2, V3, V4, V5, V0, V1, V6, V7, V8, V9, V10, V11,
                             V12, V13, V14, V15, V16, V17, V18, V19, V31, V30,
                             V29, V28, V27, V26, V25, V24, V23, V22, V21, V20)>;

// VSX register classes (the allocation order mirrors that of the corresponding
// subregister classes).
def VSLRC : RegisterClass<"PPC", [v4i32,v4f32,v2f64,v2i64], 128,
                          (add (sequence "VSL%u", 0, 13),
                               (sequence "VSL%u", 31, 14))>;
def VSRC  : RegisterClass<"PPC", [v4i32,v4f32,v2f64,v2i64], 128,
                          (add VSLRC, VRRC)>;

if I add v16i8 and v8i16 into VSRC, it will cause many failures in check-all. But now v16i8 and v8i16 can not use xxsel but vsel although VSX is available. Why does VSRC RegisterClass not contain v16i8 and v8i16 like VRRC? Should I keep the patch and add v16i8 and v8i16 into VSRC and fix the failures in check-all?

@nemanjai @hfinkel

test/CodeGen/PowerPC/vsx.ll

485 ↗

(On Diff #173125)

Since the reason I comment above, xxsel can not be selected.

[nemanjai]

lib/Target/PowerPC/PPCInstrVSX.td

1159

There's no need to add the traditional Altivec types to VSX vectors. There are very few VSX instructions that can operate on byte or halfword elements. So for the vast majority of cases, allowing them in VSX registers won't help at all.
All you need to do in this case is use COPY_TO_REGCLASS such as:

def : Pat<(v16i8 (vselect v16i8:$vA, v16i8:$vB, v16i8:$vC)),
          (XXSEL (COPY_TO_REGCLASS $vC, VSRC), 
                 (COPY_TO_REGCLASS $vB, VSRC),
                 (COPY_TO_REGCLASS $vA, VSRC))>;

[• wuzish]

lib/Target/PowerPC/PPCInstrVSX.td

1159

Thanks a lot for the information.

[• wuzish]

lib/Target/PowerPC/PPCInstrVSX.td

1159

I am afraid it can not work. I use following pattern to hack.

def : Pat<(v16i8 (vselect v16i8:$vA, v16i8:$vB, v16i8:$vC)),
          (COPY_TO_REGCLASS
                 (XXSEL (COPY_TO_REGCLASS $vC, VSRC),
                        (COPY_TO_REGCLASS $vB, VSRC),
                        (COPY_TO_REGCLASS $vA, VSRC)), VRRC)>;

[• wuzish]

@efriedma @nemanjai

Gentle ping.

[nemanjai]

LGTM now that we don't bitcast types any longer.

lib/Target/PowerPC/PPCISelDAGToDAG.cpp

case ISD::SELECT_CC: {
     else
       SelectCCOp = PPC::SELECT_CC_VRRC;
 
     SDValue Ops[] = { CCReg, N->getOperand(2), N->getOperand(3),
                         getI32Imm(BROpc, dl) };
     CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), Ops);
     return;
   }
-  case ISD::VSELECT:
-    if (PPCSubTarget->hasVSX()) {
-      SDValue Ops[] = { N->getOperand(2), N->getOperand(1), N->getOperand(0) };
-      CurDAG->SelectNodeTo(N, PPC::XXSEL, N->getValueType(0), Ops);
-      return;
-    }
-    break;
-
   case ISD::VECTOR_SHUFFLE:
     if (PPCSubTarget->hasVSX() && (N->getValueType(0) == MVT::v2f64 ||
                                   N->getValueType(0) == MVT::v2i64)) {
       ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
 
       SDValue Op1 = N->getOperand(SVN->getMaskElt(0) < 2 ? 0 : 1),
               Op2 = N->getOperand(SVN->getMaskElt(1) < 2 ? 0 : 1);
       unsigned DM[2];

lib/Target/PowerPC/PPCISelLowering.cpp

for (MVT VT : MVT::vector_valuetypes()) {
       setOperationAction(ISD::OR    , VT, Promote);
       AddPromotedToType (ISD::OR    , VT, MVT::v4i32);
       setOperationAction(ISD::XOR   , VT, Promote);
       AddPromotedToType (ISD::XOR   , VT, MVT::v4i32);
       setOperationAction(ISD::LOAD  , VT, Promote);
       AddPromotedToType (ISD::LOAD  , VT, MVT::v4i32);
       setOperationAction(ISD::SELECT, VT, Promote);
       AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
+      setOperationAction(ISD::VSELECT, VT, Legal);
       setOperationAction(ISD::SELECT_CC, VT, Promote);
       AddPromotedToType (ISD::SELECT_CC, VT, MVT::v4i32);
       setOperationAction(ISD::STORE, VT, Promote);
       AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
 
       // No other operations are legal.
       setOperationAction(ISD::MUL , VT, Expand);
       setOperationAction(ISD::SDIV, VT, Expand);
for (MVT VT : MVT::vector_valuetypes()) {
       setOperationAction(ISD::MULHS, VT, Expand);
       setOperationAction(ISD::UMUL_LOHI, VT, Expand);
       setOperationAction(ISD::SMUL_LOHI, VT, Expand);
       setOperationAction(ISD::UDIVREM, VT, Expand);
       setOperationAction(ISD::SDIVREM, VT, Expand);
       setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
       setOperationAction(ISD::FPOW, VT, Expand);
       setOperationAction(ISD::BSWAP, VT, Expand);
-      setOperationAction(ISD::VSELECT, VT, Expand);
       setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
       setOperationAction(ISD::ROTL, VT, Expand);
       setOperationAction(ISD::ROTR, VT, Expand);
 
       for (MVT InnerVT : MVT::vector_valuetypes()) {
         setTruncStoreAction(VT, InnerVT, Expand);
         setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
         setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
if (Subtarget.hasVSX()) {
       setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
 
       setOperationAction(ISD::MUL, MVT::v2f64, Legal);
       setOperationAction(ISD::FMA, MVT::v2f64, Legal);
 
       setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
       setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
 
-      setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
-      setOperationAction(ISD::VSELECT, MVT::v8i16, Legal);
-      setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
-      setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
-      setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
-
       // Share the Altivec comparison restrictions.
       setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand);
       setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand);
       setCondCodeAction(ISD::SETO,   MVT::v2f64, Expand);
       setCondCodeAction(ISD::SETONE, MVT::v2f64, Expand);
 
       setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
       setOperationAction(ISD::STORE, MVT::v2f64, Legal);

lib/Target/PowerPC/PPCInstrAltivec.td

def : Pat<(v4f32 (ffloor v4f32:$vA)),
           (VRFIM $vA)>;
 def : Pat<(v4f32 (fceil v4f32:$vA)),
           (VRFIP $vA)>;
 def : Pat<(v4f32 (ftrunc v4f32:$vA)),
           (VRFIZ $vA)>;
 def : Pat<(v4f32 (fnearbyint v4f32:$vA)),
           (VRFIN $vA)>;
 
+// Vector selection
+def : Pat<(v16i8 (vselect v16i8:$vA, v16i8:$vB, v16i8:$vC)),
+          (VSEL $vC, $vB, $vA)>;
+def : Pat<(v8i16 (vselect v8i16:$vA, v8i16:$vB, v8i16:$vC)),
+          (VSEL $vC, $vB, $vA)>;
+def : Pat<(v4i32 (vselect v4i32:$vA, v4i32:$vB, v4i32:$vC)),
+          (VSEL $vC, $vB, $vA)>;
+def : Pat<(v2i64 (vselect v2i64:$vA, v2i64:$vB, v2i64:$vC)),
+          (VSEL $vC, $vB, $vA)>;
+def : Pat<(v4f32 (vselect v4i32:$vA, v4f32:$vB, v4f32:$vC)),
+          (VSEL $vC, $vB, $vA)>;
+def : Pat<(v2f64 (vselect v2i64:$vA, v2f64:$vB, v2f64:$vC)),
+          (VSEL $vC, $vB, $vA)>;
+
 } // end HasAltivec
 
 def HasP8Altivec : Predicate<"PPCSubTarget->hasP8Altivec()">;
 def HasP8Crypto : Predicate<"PPCSubTarget->hasP8Crypto()">;
 let Predicates = [HasP8Altivec] in {
 
 let isCommutable = 1 in {
 def VMULESW : VX1_Int_Ty2<904, "vmulesw", int_ppc_altivec_vmulesw,

lib/Target/PowerPC/PPCInstrVSX.td

def : Pat<(int_ppc_vsx_xvredp v2f64:$A),
           (XVREDP $A)>;
 
 // Recip. square root estimate
 def : Pat<(int_ppc_vsx_xvrsqrtesp v4f32:$A),
           (XVRSQRTESP $A)>;
 def : Pat<(int_ppc_vsx_xvrsqrtedp v2f64:$A),
           (XVRSQRTEDP $A)>;
 
+// Vector selection
+def : Pat<(v16i8 (vselect v16i8:$vA, v16i8:$vB, v16i8:$vC)),
+          (COPY_TO_REGCLASS 
+                 (XXSEL (COPY_TO_REGCLASS $vC, VSRC),
+                        (COPY_TO_REGCLASS $vB, VSRC), 
+                        (COPY_TO_REGCLASS $vA, VSRC)), VRRC)>;
+def : Pat<(v8i16 (vselect v8i16:$vA, v8i16:$vB, v8i16:$vC)),
+          (COPY_TO_REGCLASS 
+                 (XXSEL (COPY_TO_REGCLASS $vC, VSRC),
+                        (COPY_TO_REGCLASS $vB, VSRC), 
+                        (COPY_TO_REGCLASS $vA, VSRC)), VRRC)>;
+def : Pat<(vselect v4i32:$vA, v4i32:$vB, v4i32:$vC),
+          (XXSEL $vC, $vB, $vA)>;
+def : Pat<(vselect v2i64:$vA, v2i64:$vB, v2i64:$vC),
+          (XXSEL $vC, $vB, $vA)>;
+def : Pat<(vselect v4i32:$vA, v4f32:$vB, v4f32:$vC),
+          (XXSEL $vC, $vB, $vA)>;
+def : Pat<(vselect v2i64:$vA, v2f64:$vB, v2f64:$vC),
+          (XXSEL $vC, $vB, $vA)>;
+
 let Predicates = [IsLittleEndian] in {
 def : Pat<(f64 (PPCfcfid (PPCmtvsra (i64 (vector_extract v2i64:$S, 0))))),
           (f64 (XSCVSXDDP (COPY_TO_REGCLASS (XXPERMDI $S, $S, 2), VSFRC)))>;
 def : Pat<(f64 (PPCfcfid (PPCmtvsra (i64 (vector_extract v2i64:$S, 1))))),
           (f64 (XSCVSXDDP (COPY_TO_REGCLASS (f64 (COPY_TO_REGCLASS $S, VSRC)), VSFRC)))>;
 def : Pat<(f64 (PPCfcfidu (PPCmtvsra (i64 (vector_extract v2i64:$S, 0))))),
           (f64 (XSCVUXDDP (COPY_TO_REGCLASS (XXPERMDI $S, $S, 2), VSFRC)))>;
 def : Pat<(f64 (PPCfcfidu (PPCmtvsra (i64 (vector_extract v2i64:$S, 1))))),

test/CodeGen/PowerPC/vec_select.ll

-; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-linux-gnu -mattr=+altivec | FileCheck %s
+; RUN: llc -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s -mtriple=powerpc64-linux-gnu -mcpu=pwr8 -mattr=+vsx | FileCheck %s -check-prefix=CHECK-VSX
+; RUN: llc -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s -mtriple=powerpc64-linux-gnu -mcpu=pwr8 -mattr=-vsx | FileCheck %s -check-prefix=CHECK-NOVSX
+; RUN: llc -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s -mtriple=powerpc64le-linux-gnu -mcpu=pwr8 -mattr=+vsx | FileCheck %s -check-prefix=CHECK-VSX
+; RUN: llc -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s -mtriple=powerpc64le-linux-gnu -mcpu=pwr8 -mattr=-vsx | FileCheck %s -check-prefix=CHECK-NOVSX
 
-; CHECK: vsel_float
-define <4 x float> @vsel_float(<4 x float> %v1, <4 x float> %v2) {
-  %vsel = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x float> %v1, <4 x float> %v2
-  ret <4 x float> %vsel
+define <4 x float> @test1(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d) {
+entry:
+  %m = fcmp oeq <4 x float> %c, %d
+  %v = select <4 x i1> %m, <4 x float> %a, <4 x float> %b
+  ret <4 x float> %v
 }
+; CHECK-VSX-LABLE: test1
+; CHECK-VSX: xvcmpeqsp [[REG1:(vs|v)[0-9]+]], v4, v5
+; CHECK-VSX: xxsel v2, v3, v2, [[REG1]]
+; CHECK-VSX: blr
+
+; CHECK-NOVSX-LABLE: test1
+; CHECK-NOVSX: vcmpeqfp v[[REG1:[0-9]+]], v4, v5
+; CHECK-NOVSX: vsel v2, v3, v2, v[[REG1]]
+; CHECK-NOVSX: blr
+
+define <2 x double> @test2(<2 x double> %a, <2 x double> %b, <2 x double> %c, <2 x double> %d) {
+entry:
+  %m = fcmp oeq <2 x double> %c, %d
+  %v = select <2 x i1> %m, <2 x double> %a, <2 x double> %b
+  ret <2 x double> %v
+}
+; CHECK-VSX-LABLE: test2
+; CHECK-VSX: xvcmpeqdp [[REG1:(vs|v)[0-9]+]], v4, v5
+; CHECK-VSX: xxsel v2, v3, v2, [[REG1]]
+; CHECK-VSX: blr
+
+; CHECK-NOVSX-LABLE: test2
+; CHECK-NOVSX: fcmp
+; CHECK-NOVSX: fcmp
+; CHECK-NOVSX: blr
+
+define <16 x i8> @test3(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, <16 x i8> %d) {
+entry:
+  %m = icmp eq <16 x i8> %c, %d
+  %v = select <16 x i1> %m, <16 x i8> %a, <16 x i8> %b
+  ret <16 x i8> %v
+}
+; CHECK-VSX-LABLE: test3
+; CHECK-VSX: vcmpequb v[[REG1:[0-9]+]], v4, v5
+; CHECK-VSX: xxsel v2, v3, v2, v[[REG1]]
+; CHECK-VSX: blr
+
+; CHECK-NOVSX-LABLE: test3
+; CHECK-NOVSX: vcmpequb v[[REG1:[0-9]+]], v4, v5
+; CHECK-NOVSX: vsel v2, v3, v2, v[[REG1]]
+; CHECK-NOVSX: blr
+
+define <8 x i16> @test4(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c, <8 x i16> %d) {
+entry:
+  %m = icmp eq <8 x i16> %c, %d
+  %v = select <8 x i1> %m, <8 x i16> %a, <8 x i16> %b
+  ret <8 x i16> %v
+}
+; CHECK-VSX-LABLE: test4
+; CHECK-VSX: vcmpequh v[[REG1:[0-9]+]], v4, v5
+; CHECK-VSX: xxsel v2, v3, v2, v[[REG1]]
+; CHECK-VSX: blr
+
+; CHECK-NOVSX-LABLE: test4
+; CHECK-NOVSX: vcmpequh v[[REG1:[0-9]+]], v4, v5
+; CHECK-NOVSX: vsel v2, v3, v2, v[[REG1]]
+; CHECK-NOVSX: blr
+
+define <4 x i32> @test5(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d) {
+entry:
+  %m = icmp eq <4 x i32> %c, %d
+  %v = select <4 x i1> %m, <4 x i32> %a, <4 x i32> %b
+  ret <4 x i32> %v
+}
+; CHECK-VSX-LABLE: test5
+; CHECK-VSX: vcmpequw v[[REG1:[0-9]+]], v4, v5
+; CHECK-VSX: xxsel v2, v3, v2, v[[REG1]]
+; CHECK-VSX: blr
+
+; CHECK-NOVSX-LABLE: test5
+; CHECK-NOVSX: vcmpequw v[[REG1:[0-9]+]], v4, v5
+; CHECK-NOVSX: vsel v2, v3, v2, v[[REG1]]
+; CHECK-NOVSX: blr
+
+define <2 x i64> @test6(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c, <2 x i64> %d) {
+entry:
+  %m = icmp eq <2 x i64> %c, %d
+  %v = select <2 x i1> %m, <2 x i64> %a, <2 x i64> %b
+  ret <2 x i64> %v
+}
+; CHECK-VSX-LABLE: test6
+; CHECK-VSX: vcmpequd v[[REG1:[0-9]+]], v4, v5
+; CHECK-VSX: xxsel v2, v3, v2, v[[REG1]]
+; CHECK-VSX: blr
+
+; CHECK-NOVSX-LABLE: test6
+; CHECK-NOVSX: vcmpequd v[[REG1:[0-9]+]], v4, v5
+; CHECK-NOVSX: vsel v2, v3, v2, v[[REG1]]
+; CHECK-NOVSX: blr