[x32] Fix FrameIndex check in SelectLEA64_32Addr

[pavel.v.chupin]

Summary

Fixes http://llvm.org/bugs/show_bug.cgi?id=20016 reproducible on new
lea-5.ll case.
Also use RSP/RBP for x32 lea to save 1 byte used for 0x67 prefix in
ESP/EBP case.

[dschuff]

lib/Target/X86/X86RegisterInfo.cpp

503

should this just be added to the if-else chain above?

test/CodeGen/X86/lea-5.ll

2

can this test be simplified at all? it should have some comments about what it's testing for, and what e.g. the control flow is for.

[pavel.v.chupin]

Modified code according review comments. Simplified a bit test case.

[dschuff]

LGTM with one nit.

test/CodeGen/X86/lea-4.ll

1

this triple should probably still specify linux as the OS, as the others do.

[pavel.v.chupin]

It's appeared that last version of patch is not correct because both needsStackRealignment and Opc == X86::LEA64_32r can be true at the same time. Making this check separate again and adding test revealing that.
Please review.

[dschuff]

test/CodeGen/X86/lea-5.ll

6

Unfortunately this won't work in environments without sed (none of the other tests use sed either). While it's not great, it's probably better just to duplicate this test function with the other alignment. (presumably then you can also de-regex the -40 in the CHECK line?)

[pavel.v.chupin]

Ok. Actually I found couple of tests with sed (e.g. test/Transforms/GCOVProfiling/linezero.ll) so thought it's fine... not sure how they work though when no sed available. I'll change this test.

[pavel.v.chupin]

Fixed

[dschuff]

thanks; yeah I wasn't sure either. I asked on IRC and the consensus seemed to be to just duplicate if the test is fairly small.

test/CodeGen/X86/lea-5.ll

48

shouldn't this just be X32: ?
you can check it in the same run, and you aren't calling FileCheck with X32-ALIGN64 anyway.

[pavel.v.chupin]

test/CodeGen/X86/lea-5.ll

48

It's called at line 35, but you are right, it's redundant.

[pavel.v.chupin]

Fixed

[dschuff]

LGTM, thanks.

[pavel.v.chupin]

Closed by commit rL216065 (authored by pvchupin).

lib/Target/X86/X86ISelDAGToDAG.cpp

bool X86DAGToDAGISel::SelectLEA64_32Addr(SDValue N, SDValue &Base,
                                          SDValue &Disp, SDValue &Segment) {
   if (!SelectLEAAddr(N, Base, Scale, Index, Disp, Segment))
     return false;
 
   SDLoc DL(N);
   RegisterSDNode *RN = dyn_cast<RegisterSDNode>(Base);
   if (RN && RN->getReg() == 0)
     Base = CurDAG->getRegister(0, MVT::i64);
-  else if (Base.getValueType() == MVT::i32 && !dyn_cast<FrameIndexSDNode>(N)) {
+  else if (Base.getValueType() == MVT::i32 && !dyn_cast<FrameIndexSDNode>(Base)) {
     // Base could already be %rip, particularly in the x32 ABI.
     Base = SDValue(CurDAG->getMachineNode(
                        TargetOpcode::SUBREG_TO_REG, DL, MVT::i64,
                        CurDAG->getTargetConstant(0, MVT::i64),
                        Base,
                        CurDAG->getTargetConstant(X86::sub_32bit, MVT::i32)),
                    0);
   }

lib/Target/X86/X86RegisterInfo.cpp

X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
   unsigned Opc = MI.getOpcode();
   bool AfterFPPop = Opc == X86::TAILJMPm64 || Opc == X86::TAILJMPm;
   if (hasBasePointer(MF))
     BasePtr = (FrameIndex < 0 ? FramePtr : getBaseRegister());
   else if (needsStackRealignment(MF))
     BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
   else if (AfterFPPop)
     BasePtr = StackPtr;
-  else
+  else if (Opc == X86::LEA64_32r) {
+    // For LEA64_32r when BasePtr is 32-bits (X32) we can use full-size 64-bit
+    // register as source operand, semantic is the same and destination is
+    // 32-bits. It saves one byte per lea in code since 0x67 prefix is avoided.
+    BasePtr = (TFI->hasFP(MF) ? FramePtr : StackPtr);
+    if (X86::GR32RegClass.contains(BasePtr))
+      BasePtr = getX86SubSuperRegister(BasePtr, MVT::i64, false);
+  } else
     BasePtr = (TFI->hasFP(MF) ? FramePtr : StackPtr);
 
+
   // This must be part of a four operand memory reference.  Replace the
   // FrameIndex with base register with EBP.  Add an offset to the offset.
   MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
 
   // Now add the frame object offset to the offset from EBP.
   int FIOffset;
   if (AfterFPPop) {
     // Tail call jmp happens after FP is popped.
     const MachineFrameInfo *MFI = MF.getFrameInfo();
     FIOffset = MFI->getObjectOffset(FrameIndex) - TFI->getOffsetOfLocalArea();
   } else
     FIOffset = TFI->getFrameIndexOffset(MF, FrameIndex);

test/CodeGen/X86/lea-2.ll

-; RUN: llc < %s -march=x86 -x86-asm-syntax=intel | FileCheck %s
+; RUN: llc < %s -mtriple=i686-linux -x86-asm-syntax=intel | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-linux -x86-asm-syntax=intel | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-linux-gnux32 -x86-asm-syntax=intel | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-nacl -x86-asm-syntax=intel | FileCheck %s
 
 define i32 @test1(i32 %A, i32 %B) {
   %tmp1 = shl i32 %A, 2
   %tmp3 = add i32 %B, -5
   %tmp4 = add i32 %tmp3, %tmp1
 ; The above computation of %tmp4 should match a single lea, without using
 ; actual add instructions.
 ; CHECK-NOT: add
 ; CHECK: lea {{[a-z]+}}, dword ptr [{{[a-z]+}} + 4*{{[a-z]+}} - 5]
 
   ret i32 %tmp4
 }
 
 

test/CodeGen/X86/lea-3.ll

 ; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-linux-gnux32 | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-nacl | FileCheck %s
 ; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s
 
 ; CHECK: leaq (,[[A0:%rdi|%rcx]],4), %rax
 define i64 @test2(i64 %a) {
         %tmp2 = shl i64 %a, 2
   %tmp3 = or i64 %tmp2, %a
         ret i64 %tmp3
 }

test/CodeGen/X86/lea-4.ll

-; RUN: llc < %s -march=x86-64 | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64 | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-linux-gnux32 | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-nacl | FileCheck %s
+
 
 define zeroext i16 @t1(i32 %on_off) nounwind {
 entry:
   %0 = sub i32 %on_off, 1
   %1 = mul i32 %0, 2
   %2 = trunc i32 %1 to i16
   %3 = zext i16 %2 to i32
   %4 = trunc i32 %3 to i16

test/CodeGen/X86/lea-5.ll

+; test for more complicated forms of lea operands which can be generated
+; in loop optimized cases.
+; See also http://llvm.org/bugs/show_bug.cgi?id=20016
+
+; RUN: llc < %s -mtriple=x86_64-linux -O2        | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-linux-gnux32 -O2 | FileCheck %s -check-prefix=X32
+; RUN: llc < %s -mtriple=x86_64-nacl -O2 | FileCheck %s -check-prefix=X32
+
+; Function Attrs: nounwind readnone uwtable
+define void @bar(i32 %x, i32 %d) #0 {
+entry:
+  %a = alloca [8 x i32], align 16
+  br label %while.cond
+
+while.cond:                                       ; preds = %while.cond, %entry
+  %d.addr.0 = phi i32 [ %d, %entry ], [ %inc, %while.cond ]
+  %arrayidx = getelementptr inbounds [8 x i32]* %a, i32 0, i32 %d.addr.0
+
+; CHECK: leaq -40(%rsp,%r{{[^,]*}},4), %rax
+; X32:   leal -40(%rsp,%r{{[^,]*}},4), %eax
+  %0 = load i32* %arrayidx, align 4
+  %cmp1 = icmp eq i32 %0, 0
+  %inc = add nsw i32 %d.addr.0, 1
+
+; CHECK: leaq 4(%r{{[^,]*}}), %r{{[^,]*}}
+; X32:   leal 4(%r{{[^,]*}}), %e{{[^,]*}}
+  br i1 %cmp1, label %while.end, label %while.cond
+
+while.end:                                        ; preds = %while.cond
+  ret void
+}

test/CodeGen/X86/lea.ll

 ; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s
 ; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-linux-gnux32 | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-nacl | FileCheck %s
 
 define i32 @test1(i32 %x) nounwind {
         %tmp1 = shl i32 %x, 3
         %tmp2 = add i32 %tmp1, 7
         ret i32 %tmp2
 ; CHECK-LABEL: test1:
 ; CHECK:    leal 7(,%r[[A0:di|cx]],8), %eax
 }