[ARM] ParallelDSP: only support i16 loads for now.

[SjoerdMeijer]

Summary

We were miscompiling i8 loads, so reject them as unsupported narrow operations
for now.

[SjoerdMeijer]

Some more clean ups

[samparker]

LGTM

lib/Target/ARM/ARMParallelDSP.cpp

bool runOnLoop(Loop *TheLoop, LPPassManager &) override {
 
       LLVM_DEBUG(dbgs() << "\n== Parallel DSP pass ==\n\n");
       Changes = MatchSMLAD(F);
       return Changes;
     }
   };
 }
 
-template<unsigned BitWidth>
+// MaxBitwidth: the maximum supported bitwidth of the elements in the DSP
+// instructions, which is set to 16. So here we should collect all i8 and i16
+// narrow operations.
+// TODO: we currently only collect i16, and will support i8 later, so that's
+// why we check that types are equal to MaxBitWidth, and not <= MaxBitWidth.
+template<unsigned MaxBitWidth>
 static bool IsNarrowSequence(Value *V, ValueList &VL) {
-  LLVM_DEBUG(dbgs() << "Is narrow sequence: "; V->dump());
+  LLVM_DEBUG(dbgs() << "Is narrow sequence? "; V->dump());
   ConstantInt *CInt;
 
   if (match(V, m_ConstantInt(CInt))) {
     // TODO: if a constant is used, it needs to fit within the bit width.
     return false;
   }
 
   auto *I = dyn_cast<Instruction>(V);
   if (!I)
    return false;
 
   Value *Val, *LHS, *RHS;
-  bool isNarrow = false;
-
   if (match(V, m_Trunc(m_Value(Val)))) {
-    if (cast<TruncInst>(I)->getDestTy()->getIntegerBitWidth() == BitWidth)
-      isNarrow = IsNarrowSequence<BitWidth>(Val, VL);
+    if (cast<TruncInst>(I)->getDestTy()->getIntegerBitWidth() == MaxBitWidth)
+      return IsNarrowSequence<MaxBitWidth>(Val, VL);
   } else if (match(V, m_Add(m_Value(LHS), m_Value(RHS)))) {
     // TODO: we need to implement sadd16/sadd8 for this, which enables to
     // also do the rewrite for smlad8.ll, but it is unsupported for now.
-    isNarrow = false;
+    LLVM_DEBUG(dbgs() << "No, unsupported Op:\t"; I->dump());
+    return false;
   } else if (match(V, m_ZExtOrSExt(m_Value(Val)))) {
-    if (cast<CastInst>(I)->getSrcTy()->getIntegerBitWidth() == BitWidth)
-      isNarrow = true;
-    else
-      LLVM_DEBUG(dbgs() << "Wrong SrcTy size of CastInst: " <<
-                 cast<CastInst>(I)->getSrcTy()->getIntegerBitWidth());
-
-    if (match(Val, m_Load(m_Value(Val)))) {
-      auto *Ld = dyn_cast<LoadInst>(I->getOperand(0));
-      LLVM_DEBUG(dbgs() << "Found narrow Load:\t"; Ld->dump());
-      VL.push_back(Ld);
-      isNarrow = true;
-    } else if (!isa<Instruction>(I->getOperand(0)))
-      VL.push_back(I->getOperand(0));
+    if (cast<CastInst>(I)->getSrcTy()->getIntegerBitWidth() != MaxBitWidth) {
+      LLVM_DEBUG(dbgs() << "No, wrong SrcTy size: " <<
+        cast<CastInst>(I)->getSrcTy()->getIntegerBitWidth() << "\n");
+      return false;
     }
 
-  if (isNarrow) {
-    LLVM_DEBUG(dbgs() << "Found narrow Op:\t"; I->dump());
+    if (match(Val, m_Load(m_Value()))) {
+      LLVM_DEBUG(dbgs() << "Yes, found narrow Load:\t"; Val->dump());
+      VL.push_back(Val);
       VL.push_back(I);
-  } else
-    LLVM_DEBUG(dbgs() << "Found unsupported Op:\t"; I->dump());
-
-  return isNarrow;
+      return true;
+    }
+  }
+  LLVM_DEBUG(dbgs() << "No, unsupported Op:\t"; I->dump());
+  return false;
 }
 
 // Element-by-element comparison of Value lists returning true if they are
 // instructions with the same opcode or constants with the same value.
 static bool AreSymmetrical(const ValueList &VL0,
                            const ValueList &VL1) {
   if (VL0.size() != VL1.size()) {
     LLVM_DEBUG(dbgs() << "Muls are mismatching operand list lengths: "

test/CodeGen/ARM/smlad1.ll

 ; RUN: opt -mtriple=arm-arm-eabi -mcpu=cortex-m33 < %s -parallel-dsp -S | FileCheck %s
 
+; CHECK-LABEL: @test1
 ; CHECK:  %mac1{{\.}}026 = phi i32 [ [[V8:%[0-9]+]], %for.body ], [ 0, %for.body.preheader ]
 ; CHECK:  [[V4:%[0-9]+]] = bitcast i16* %arrayidx3 to i32*
 ; CHECK:  [[V5:%[0-9]+]] = load i32, i32* [[V4]], align 2
 ; CHECK:  [[V6:%[0-9]+]] = bitcast i16* %arrayidx to i32*
 ; CHECK:  [[V7:%[0-9]+]] = load i32, i32* [[V6]], align 2
 ; CHECK:  [[V8]] = call i32 @llvm.arm.smlad(i32 [[V5]], i32 [[V7]], i32 %mac1{{\.}}026)
 
-define dso_local i32 @test(i32 %arg, i32* nocapture readnone %arg1, i16* nocapture readonly %arg2, i16* nocapture readonly %arg3) {
+define dso_local i32 @test1(i32 %arg, i32* nocapture readnone %arg1, i16* nocapture readonly %arg2, i16* nocapture readonly %arg3) {
 entry:
   %cmp24 = icmp sgt i32 %arg, 0
   br i1 %cmp24, label %for.body.preheader, label %for.cond.cleanup
 
 for.body.preheader:
   %.pre = load i16, i16* %arg3, align 2
   %.pre27 = load i16, i16* %arg2, align 2
   br label %for.body

 
 ; And here the Add is the LHS, the Mul the RHS
   %add11 = add i32 %add10, %mul9
 
   %exitcond = icmp ne i32 %add, %arg
   br i1 %exitcond, label %for.body, label %for.cond.cleanup
 }
 
+; Here we have i8 loads, which we do want to support, but don't handle yet.
+;
+; CHECK-LABEL: @test2
+; CHECK-NOT:   call i32 @llvm.arm.smlad
+;
+define dso_local i32 @test2(i32 %arg, i32* nocapture readnone %arg1, i8* nocapture readonly %arg2, i8* nocapture readonly %arg3) {
+entry:
+  %cmp24 = icmp sgt i32 %arg, 0
+  br i1 %cmp24, label %for.body.preheader, label %for.cond.cleanup
+
+for.body.preheader:
+  %.pre = load i8, i8* %arg3, align 2
+  %.pre27 = load i8, i8* %arg2, align 2
+  br label %for.body
+
+for.cond.cleanup:
+  %mac1.0.lcssa = phi i32 [ 0, %entry ], [ %add11, %for.body ]
+  ret i32 %mac1.0.lcssa
+
+for.body:
+  %mac1.026 = phi i32 [ %add11, %for.body ], [ 0, %for.body.preheader ]
+  %i.025 = phi i32 [ %add, %for.body ], [ 0, %for.body.preheader ]
+  %arrayidx = getelementptr inbounds i8, i8* %arg3, i32 %i.025
+  %0 = load i8, i8* %arrayidx, align 2
+  %add = add nuw nsw i32 %i.025, 1
+  %arrayidx1 = getelementptr inbounds i8, i8* %arg3, i32 %add
+  %1 = load i8, i8* %arrayidx1, align 2
+  %arrayidx3 = getelementptr inbounds i8, i8* %arg2, i32 %i.025
+  %2 = load i8, i8* %arrayidx3, align 2
+  %conv = sext i8 %2 to i32
+  %conv4 = sext i8 %0 to i32
+  %mul = mul nsw i32 %conv, %conv4
+  %arrayidx6 = getelementptr inbounds i8, i8* %arg2, i32 %add
+  %3 = load i8, i8* %arrayidx6, align 2
+  %conv7 = sext i8 %3 to i32
+  %conv8 = sext i8 %1 to i32
+  %mul9 = mul nsw i32 %conv7, %conv8
+  %add10 = add i32 %mul, %mac1.026
+  %add11 = add i32 %add10, %mul9
+  %exitcond = icmp ne i32 %add, %arg
+  br i1 %exitcond, label %for.body, label %for.cond.cleanup
+}
+
+