[NEON] Fix combining of vldx_dup intrinsics with updating of base addresses

[kosarev]

Summary

Resolves:
Unsupported ARM Neon intrinsics in Target-specific DAG combine function for VLDDUP
https://bugs.llvm.org/show_bug.cgi?id=38031

Related diff: D48439

[dnsampaio]

Hi Ivan,
The patch fixes the crash, but I would like to know if the desired updates aren't already done, just needing to copy paste them?
Cheers
Diogo

lib/Target/ARM/ARMISelLowering.cpp

11492

Perhaps I got something wrong, but the desired actions for these 3 intrinsics aren't already defined in the "else" statement below, where it already receives the desired node type? Just need to define isLane=true and NumVecs and NewOpc accordingly.

11518–11521

Actions defined here.

[kosarev]

lib/Target/ARM/ARMISelLowering.cpp

11492

Yes, we have the VLDxDUP_UPD nodes, but they are not supported for 256-bit vectors (q versions of the intrinsics) yet.

[dnsampaio]

Seems good to me.

lib/Target/ARM/ARMISelLowering.cpp

if (isIntrinsic) {
       case Intrinsic::arm_neon_vld1:     NewOpc = ARMISD::VLD1_UPD;
         NumVecs = 1; break;
       case Intrinsic::arm_neon_vld2:     NewOpc = ARMISD::VLD2_UPD;
         NumVecs = 2; break;
       case Intrinsic::arm_neon_vld3:     NewOpc = ARMISD::VLD3_UPD;
         NumVecs = 3; break;
       case Intrinsic::arm_neon_vld4:     NewOpc = ARMISD::VLD4_UPD;
         NumVecs = 4; break;
+      case Intrinsic::arm_neon_vld2dup:
+      case Intrinsic::arm_neon_vld3dup:
+      case Intrinsic::arm_neon_vld4dup:
+        // TODO: Support updating VLDxDUP nodes. For now, we just skip
+        // combining base updates for such intrinsics.
+        continue;
       case Intrinsic::arm_neon_vld2lane: NewOpc = ARMISD::VLD2LN_UPD;
         NumVecs = 2; isLaneOp = true; break;
       case Intrinsic::arm_neon_vld3lane: NewOpc = ARMISD::VLD3LN_UPD;
         NumVecs = 3; isLaneOp = true; break;
       case Intrinsic::arm_neon_vld4lane: NewOpc = ARMISD::VLD4LN_UPD;
         NumVecs = 4; isLaneOp = true; break;
       case Intrinsic::arm_neon_vst1:     NewOpc = ARMISD::VST1_UPD;
         NumVecs = 1; isLoadOp = false; break;
if (isIntrinsic) {
         NumVecs = 3; isLoadOp = false; isLaneOp = true; break;
       case Intrinsic::arm_neon_vst4lane: NewOpc = ARMISD::VST4LN_UPD;
         NumVecs = 4; isLoadOp = false; isLaneOp = true; break;
       }
     } else {
       isLaneOp = true;
       switch (N->getOpcode()) {
       default: llvm_unreachable("unexpected opcode for Neon base update");
       case ARMISD::VLD1DUP: NewOpc = ARMISD::VLD1DUP_UPD; NumVecs = 1; break;
       case ARMISD::VLD2DUP: NewOpc = ARMISD::VLD2DUP_UPD; NumVecs = 2; break;
       case ARMISD::VLD3DUP: NewOpc = ARMISD::VLD3DUP_UPD; NumVecs = 3; break;
       case ARMISD::VLD4DUP: NewOpc = ARMISD::VLD4DUP_UPD; NumVecs = 4; break;
       case ISD::LOAD:       NewOpc = ARMISD::VLD1_UPD;
         NumVecs = 1; isLaneOp = false; break;
       case ISD::STORE:      NewOpc = ARMISD::VST1_UPD;
         NumVecs = 1; isLaneOp = false; isLoadOp = false; break;
       }
     }
 
     // Find the size of memory referenced by the load/store.

test/CodeGen/ARM/arm-vlddup-update.ll

+; RUN: llc < %s -mtriple=armv8-linux-gnueabi -verify-machineinstrs \
+; RUN:     -asm-verbose=false | FileCheck %s
+
+%struct.uint32x2x2_t = type { <2 x i32>, <2 x i32> }
+%struct.uint32x2x3_t = type { <2 x i32>, <2 x i32>, <2 x i32> }
+%struct.uint32x2x4_t = type { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> }
+
+declare %struct.uint32x2x2_t @llvm.arm.neon.vld2dup.v2i32.p0i8(i8*, i32)
+declare %struct.uint32x2x3_t @llvm.arm.neon.vld3dup.v2i32.p0i8(i8*, i32)
+declare %struct.uint32x2x4_t @llvm.arm.neon.vld4dup.v2i32.p0i8(i8*, i32)
+
+; CHECK-LABEL: test_vld2_dup_update
+; CHECK: vld2.32 {d16[], d17[]}, {{\[}}[[SRC_R:r[0-9]+]]]
+; CHECK: add {{r[0-9]+|lr}}, [[SRC_R]], #4
+define i8* @test_vld2_dup_update(%struct.uint32x2x2_t* %dest, i8* %src) {
+entry:
+  %tmp = tail call %struct.uint32x2x2_t @llvm.arm.neon.vld2dup.v2i32.p0i8(i8* %src, i32 4)
+  store %struct.uint32x2x2_t %tmp, %struct.uint32x2x2_t* %dest, align 8
+  %updated_src = getelementptr inbounds i8, i8* %src, i32 4
+  ret i8* %updated_src
+}
+
+; CHECK-LABEL: test_vld3_dup_update
+; CHECK: vld3.32 {d16[], d17[], d18[]}, {{\[}}[[SRC_R:r[0-9]+]]]
+; CHECK: add {{r[0-9]+|lr}}, [[SRC_R]], #4
+define i8* @test_vld3_dup_update(%struct.uint32x2x3_t* %dest, i8* %src) {
+entry:
+  %tmp = tail call %struct.uint32x2x3_t @llvm.arm.neon.vld3dup.v2i32.p0i8(i8* %src, i32 4)
+  store %struct.uint32x2x3_t %tmp, %struct.uint32x2x3_t* %dest, align 8
+  %updated_src = getelementptr inbounds i8, i8* %src, i32 4
+  ret i8* %updated_src
+}
+
+; CHECK-LABEL: test_vld4_dup_update
+; CHECK: vld4.32 {d16[], d17[], d18[], d19[]}, {{\[}}[[SRC_R:r[0-9]+]]]
+; CHECK: add {{r[0-9]+|lr}}, [[SRC_R]], #4
+define i8* @test_vld4_dup_update(%struct.uint32x2x4_t* %dest, i8* %src) {
+entry:
+  %tmp = tail call %struct.uint32x2x4_t @llvm.arm.neon.vld4dup.v2i32.p0i8(i8* %src, i32 4)
+  store %struct.uint32x2x4_t %tmp, %struct.uint32x2x4_t* %dest, align 8
+  %updated_src = getelementptr inbounds i8, i8* %src, i32 4
+  ret i8* %updated_src
+}