[ARM] Fix PR37382: Don't optimize mul.with.overflow on thumbv6m.

[rogfer01]

Thanks a lot for the patch @pftbest!

Would it make sense to add a regression test with the reproducer in PR37382?

[pftbest]

I've added a RUN line in overflow-intrinsic-optimizations.ll test, and it will cause the same exact assertion if tested without the fix. So I think adding another test would be redundant.

[rogfer01]

Ah, I didn't notice it was exactly the same. You're right no need to add it again.

LGTM!

[efriedma]

test/CodeGen/ARM/overflow-intrinsic-optimizations.ll

85 ↗

(On Diff #153764)

Instead of this CHECK-NOT, could you explicitly CHECK for the call to __aeabi_lmul?

[pftbest]

Explicit check for __aeabi_lmul

[efriedma]

LGTM

llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp

SDValue ARMTargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
   SDValue Chain = Op.getOperand(0);
   SDValue Cond = Op.getOperand(1);
   SDValue Dest = Op.getOperand(2);
   SDLoc dl(Op);
 
   // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
   // instruction.
   unsigned Opc = Cond.getOpcode();
+  bool OptimizeMul = (Opc == ISD::SMULO || Opc == ISD::UMULO) &&
+                      !Subtarget->isThumb1Only();
   if (Cond.getResNo() == 1 &&
       (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
-       Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) {
+       Opc == ISD::USUBO || OptimizeMul)) {
     // Only lower legal XALUO ops.
     if (!DAG.getTargetLoweringInfo().isTypeLegal(Cond->getValueType(0)))
       return SDValue();
 
     // The actual operation with overflow check.
     SDValue Value, OverflowCmp;
     SDValue ARMcc;
     std::tie(Value, OverflowCmp) = getARMXALUOOp(Cond, DAG, ARMcc);
if (!RHS.getNode()) {
       RHS = DAG.getConstant(0, dl, LHS.getValueType());
       CC = ISD::SETNE;
     }
   }
 
   // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
   // instruction.
   unsigned Opc = LHS.getOpcode();
+  bool OptimizeMul = (Opc == ISD::SMULO || Opc == ISD::UMULO) &&
+                      !Subtarget->isThumb1Only();
   if (LHS.getResNo() == 1 && (isOneConstant(RHS) || isNullConstant(RHS)) &&
       (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
-       Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO) &&
+       Opc == ISD::USUBO || OptimizeMul) &&
       (CC == ISD::SETEQ || CC == ISD::SETNE)) {
     // Only lower legal XALUO ops.
     if (!DAG.getTargetLoweringInfo().isTypeLegal(LHS->getValueType(0)))
       return SDValue();
 
     // The actual operation with overflow check.
     SDValue Value, OverflowCmp;
     SDValue ARMcc;

llvm/trunk/test/CodeGen/ARM/overflow-intrinsic-optimizations.ll

 ; RUN: llc < %s -mtriple=arm-eabi -mcpu=generic | FileCheck %s
+; RUN: llc < %s -mtriple=thumbv6m-eabi | FileCheck %s -check-prefix=CHECK-V6M-THUMB
 
 define i32 @sadd(i32 %a, i32 %b) local_unnamed_addr #0 {
 ; CHECK-LABEL: sadd:
 ; CHECK:    adds r0, r0, r1
 ; CHECK-NEXT:    movvc pc, lr
 entry:
   %0 = tail call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %a, i32 %b)
   %1 = extractvalue { i32, i1 } %0, 1

 
 }
 
 define i32 @smul(i32 %a, i32 %b) local_unnamed_addr #0 {
 ; CHECK-LABEL: smul:
 ; CHECK: smull r0, r[[RHI:[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}
 ; CHECK-NEXT: cmp r[[RHI]], r0, asr #31
 ; CHECK-NEXT: moveq pc, lr
+; CHECK-V6M-THUMB-LABEL: smul:
+; CHECK-V6M-THUMB: bl __aeabi_lmul
 entry:
   %0 = tail call { i32, i1 } @llvm.smul.with.overflow.i32(i32 %a, i32 %b)
   %1 = extractvalue { i32, i1 } %0, 1
   br i1 %1, label %trap, label %cont
 
 trap:
   tail call void @llvm.trap() #2
   unreachable
 
 cont:
   %2 = extractvalue { i32, i1 } %0, 0
   ret i32 %2
 }
 
 define i32 @umul(i32 %a, i32 %b) local_unnamed_addr #0 {
 ; CHECK-LABEL: umul:
 ; CHECK: umull r0, r[[RHI:[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}
 ; CHECK-NEXT: cmp r[[RHI]], #0
 ; CHECK-NEXT: moveq pc, lr
+; CHECK-V6M-THUMB-LABEL: umul:
+; CHECK-V6M-THUMB: bl __aeabi_lmul
 entry:
   %0 = tail call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %a, i32 %b)
   %1 = extractvalue { i32, i1 } %0, 1
   br i1 %1, label %trap, label %cont
 
 trap:
   tail call void @llvm.trap() #2
   unreachable