[X86] Suppress load folding into and/or/xor if it will prevent matching btr/bts/btc.

[craig.topper]

Summary

This is a follow up to r335753. At the time I forgot about isProfitableToFold which makes this pretty easy.

[lebedev.ri]

This looks reasonable, but i'm not familiar with that code.

lib/Target/X86/X86ISelDAGToDAG.cpp

576 ↗

(On Diff #153261)

Extra unneeded brackets

[xbolva00]

lib/Target/X86/X86ISelDAGToDAG.cpp

594 ↗

(On Diff #153261)

dyn_cast maybe?

[craig.topper]

lib/Target/X86/X86ISelDAGToDAG.cpp

576 ↗

(On Diff #153261)

Oops. Leftover from before I realized that I had to handle both operand orders.

594 ↗

(On Diff #153261)

I was just trying to avoid another level of 'if'

[RKSimon]

LGTM once the extra brackets have been fixed. I'm happy with either the isa/cast pattern or replacing with a dyn_cast inner if().

llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp

case ISD::XOR: {
       // a load.
       // FIXME: This is probably also true for non-TLS addresses.
       if (Op1.getOpcode() == X86ISD::Wrapper) {
         SDValue Val = Op1.getOperand(0);
         if (Val.getOpcode() == ISD::TargetGlobalTLSAddress)
           return false;
       }
 
+      // Don't fold load if this matches the BTS/BTR/BTC patterns.
+      // BTS: (or X, (shl 1, n))
+      // BTR: (and X, (rotl -2, n))
+      // BTC: (xor X, (shl 1, n))
+      if (U->getOpcode() == ISD::OR || U->getOpcode() == ISD::XOR) {
+        if (U->getOperand(0).getOpcode() == ISD::SHL &&
+            isOneConstant(U->getOperand(0).getOperand(0)))
+          return false;
+
+        if (U->getOperand(1).getOpcode() == ISD::SHL &&
+            isOneConstant(U->getOperand(1).getOperand(0)))
+          return false;
+      }
+      if (U->getOpcode() == ISD::AND) {
+        SDValue U0 = U->getOperand(0);
+        SDValue U1 = U->getOperand(1);
+        if (U0.getOpcode() == ISD::ROTL) {
+          auto *C = dyn_cast<ConstantSDNode>(U0.getOperand(0));
+          if (C && C->getSExtValue() == -2)
+            return false;
+        }
+
+        if (U1.getOpcode() == ISD::ROTL) {
+          auto *C = dyn_cast<ConstantSDNode>(U1.getOperand(0));
+          if (C && C->getSExtValue() == -2)
+            return false;
+        }
+      }
+
       break;
     }
     case ISD::SHL:
     case ISD::SRA:
     case ISD::SRL:
       // Don't fold a load into a shift by immediate. The BMI2 instructions
       // support folding a load, but not an immediate. The legacy instructions
       // support folding an immediate, but can't fold a load. Folding an

llvm/trunk/test/CodeGen/X86/btc_bts_btr.ll

 ; X64-NEXT:    movl %esi, %ecx
 ; X64-NEXT:    rolw %cl, %ax
 ; X64-NEXT:    andl %edi, %eax
 ; X64-NEXT:    # kill: def $ax killed $ax killed $eax
 ; X64-NEXT:    retq
 ;
 ; X86-LABEL: btr_16:
 ; X86:       # %bb.0:
+; X86-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
 ; X86-NEXT:    movb {{[0-9]+}}(%esp), %cl
-; X86-NEXT:    movw $-2, %ax
-; X86-NEXT:    rolw %cl, %ax
-; X86-NEXT:    andw {{[0-9]+}}(%esp), %ax
+; X86-NEXT:    btrw %cx, %ax
 ; X86-NEXT:    retl
   %1 = shl i16 1, %n
   %2 = xor i16 %1, -1
   %3 = and i16 %x, %2
   ret i16 %3
 }
 
 define i16 @bts_16(i16 %x, i16 %n) {

 ; X64-LABEL: btr_32:
 ; X64:       # %bb.0:
 ; X64-NEXT:    btrl %esi, %edi
 ; X64-NEXT:    movl %edi, %eax
 ; X64-NEXT:    retq
 ;
 ; X86-LABEL: btr_32:
 ; X86:       # %bb.0:
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X86-NEXT:    movb {{[0-9]+}}(%esp), %cl
-; X86-NEXT:    movl $-2, %eax
-; X86-NEXT:    roll %cl, %eax
-; X86-NEXT:    andl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    btrl %ecx, %eax
 ; X86-NEXT:    retl
   %1 = shl i32 1, %n
   %2 = xor i32 %1, -1
   %3 = and i32 %x, %2
   ret i32 %3
 }
 
 define i32 @bts_32(i32 %x, i32 %n) {
 ; X64-LABEL: bts_32:
 ; X64:       # %bb.0:
 ; X64-NEXT:    btsl %esi, %edi
 ; X64-NEXT:    movl %edi, %eax
 ; X64-NEXT:    retq
 ;
 ; X86-LABEL: bts_32:
 ; X86:       # %bb.0:
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X86-NEXT:    movb {{[0-9]+}}(%esp), %cl
-; X86-NEXT:    movl $1, %eax
-; X86-NEXT:    shll %cl, %eax
-; X86-NEXT:    orl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    btsl %ecx, %eax
 ; X86-NEXT:    retl
   %1 = shl i32 1, %n
   %2 = or i32 %x, %1
   ret i32 %2
 }
 
 define i32 @btc_32(i32 %x, i32 %n) {
 ; X64-LABEL: btc_32:
 ; X64:       # %bb.0:
 ; X64-NEXT:    btcl %esi, %edi
 ; X64-NEXT:    movl %edi, %eax
 ; X64-NEXT:    retq
 ;
 ; X86-LABEL: btc_32:
 ; X86:       # %bb.0:
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X86-NEXT:    movb {{[0-9]+}}(%esp), %cl
-; X86-NEXT:    movl $1, %eax
-; X86-NEXT:    shll %cl, %eax
-; X86-NEXT:    xorl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    btcl %ecx, %eax
 ; X86-NEXT:    retl
   %1 = shl i32 1, %n
   %2 = xor i32 %x, %1
   ret i32 %2
 }
 
 define i64 @btr_64(i64 %x, i64 %n) {
 ; X64-LABEL: btr_64:

 ; X64-NEXT:    movl %esi, %ecx
 ; X64-NEXT:    rolw %cl, %ax
 ; X64-NEXT:    andl %edi, %eax
 ; X64-NEXT:    # kill: def $ax killed $ax killed $eax
 ; X64-NEXT:    retq
 ;
 ; X86-LABEL: btr_16_mask:
 ; X86:       # %bb.0:
+; X86-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
 ; X86-NEXT:    movb {{[0-9]+}}(%esp), %cl
-; X86-NEXT:    movw $-2, %ax
-; X86-NEXT:    rolw %cl, %ax
-; X86-NEXT:    andw {{[0-9]+}}(%esp), %ax
+; X86-NEXT:    btrw %cx, %ax
 ; X86-NEXT:    retl
   %1 = and i16 %n, 15
   %2 = shl i16 1, %1
   %3 = xor i16 %2, -1
   %4 = and i16 %x, %3
   ret i16 %4
 }
 

 ; X64-LABEL: btr_32_mask:
 ; X64:       # %bb.0:
 ; X64-NEXT:    btrl %esi, %edi
 ; X64-NEXT:    movl %edi, %eax
 ; X64-NEXT:    retq
 ;
 ; X86-LABEL: btr_32_mask:
 ; X86:       # %bb.0:
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X86-NEXT:    movb {{[0-9]+}}(%esp), %cl
-; X86-NEXT:    movl $-2, %eax
-; X86-NEXT:    roll %cl, %eax
-; X86-NEXT:    andl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    btrl %ecx, %eax
 ; X86-NEXT:    retl
   %1 = and i32 %n, 31
   %2 = shl i32 1, %1
   %3 = xor i32 %2, -1
   %4 = and i32 %x, %3
   ret i32 %4
 }
 
 define i32 @bts_32_mask(i32 %x, i32 %n) {
 ; X64-LABEL: bts_32_mask:
 ; X64:       # %bb.0:
 ; X64-NEXT:    btsl %esi, %edi
 ; X64-NEXT:    movl %edi, %eax
 ; X64-NEXT:    retq
 ;
 ; X86-LABEL: bts_32_mask:
 ; X86:       # %bb.0:
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X86-NEXT:    movb {{[0-9]+}}(%esp), %cl
-; X86-NEXT:    movl $1, %eax
-; X86-NEXT:    shll %cl, %eax
-; X86-NEXT:    orl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    btsl %ecx, %eax
 ; X86-NEXT:    retl
   %1 = and i32 %n, 31
   %2 = shl i32 1, %1
   %3 = or i32 %x, %2
   ret i32 %3
 }
 
 define i32 @btc_32_mask(i32 %x, i32 %n) {
 ; X64-LABEL: btc_32_mask:
 ; X64:       # %bb.0:
 ; X64-NEXT:    btcl %esi, %edi
 ; X64-NEXT:    movl %edi, %eax
 ; X64-NEXT:    retq
 ;
 ; X86-LABEL: btc_32_mask:
 ; X86:       # %bb.0:
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X86-NEXT:    movb {{[0-9]+}}(%esp), %cl
-; X86-NEXT:    movl $1, %eax
-; X86-NEXT:    shll %cl, %eax
-; X86-NEXT:    xorl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    btcl %ecx, %eax
 ; X86-NEXT:    retl
   %1 = and i32 %n, 31
   %2 = shl i32 1, %1
   %3 = xor i32 %x, %2
   ret i32 %3
 }
 
 define i64 @btr_64_mask(i64 %x, i64 %n) {
; X86-NEXT:    retl
   ret i64 %3
 }
 
 ; Tests below use loads and we favor folding those over matching btc/btr/bts.
 
 define i16 @btr_16_load(i16* %x, i16 %n) {
 ; X64-LABEL: btr_16_load:
 ; X64:       # %bb.0:
-; X64-NEXT:    movw $-2, %ax
-; X64-NEXT:    movl %esi, %ecx
-; X64-NEXT:    rolw %cl, %ax
-; X64-NEXT:    andw (%rdi), %ax
+; X64-NEXT:    movzwl (%rdi), %eax
+; X64-NEXT:    btrw %si, %ax
 ; X64-NEXT:    retq
 ;
 ; X86-LABEL: btr_16_load:
 ; X86:       # %bb.0:
-; X86-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; X86-NEXT:    movb {{[0-9]+}}(%esp), %cl
-; X86-NEXT:    movw $-2, %ax
-; X86-NEXT:    rolw %cl, %ax
-; X86-NEXT:    andw (%edx), %ax
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movzwl (%eax), %eax
+; X86-NEXT:    btrw %cx, %ax
 ; X86-NEXT:    retl
   %1 = load i16, i16* %x
   %2 = shl i16 1, %n
   %3 = xor i16 %2, -1
   %4 = and i16 %1, %3
   ret i16 %4
 }
 
; X86-NEXT:    retl
   %2 = shl i16 1, %n
   %3 = xor i16 %1, %2
   ret i16 %3
 }
 
 define i32 @btr_32_load(i32* %x, i32 %n) {
 ; X64-LABEL: btr_32_load:
 ; X64:       # %bb.0:
-; X64-NEXT:    movl $-2, %eax
-; X64-NEXT:    movl %esi, %ecx
-; X64-NEXT:    roll %cl, %eax
-; X64-NEXT:    andl (%rdi), %eax
+; X64-NEXT:    movl (%rdi), %eax
+; X64-NEXT:    btrl %esi, %eax
 ; X64-NEXT:    retq
 ;
 ; X86-LABEL: btr_32_load:
 ; X86:       # %bb.0:
-; X86-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; X86-NEXT:    movb {{[0-9]+}}(%esp), %cl
-; X86-NEXT:    movl $-2, %eax
-; X86-NEXT:    roll %cl, %eax
-; X86-NEXT:    andl (%edx), %eax
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movl (%eax), %eax
+; X86-NEXT:    btrl %ecx, %eax
 ; X86-NEXT:    retl
   %1 = load i32, i32* %x
   %2 = shl i32 1, %n
   %3 = xor i32 %2, -1
   %4 = and i32 %1, %3
   ret i32 %4
 }
 
 define i32 @bts_32_load(i32* %x, i32 %n) {
 ; X64-LABEL: bts_32_load:
 ; X64:       # %bb.0:
-; X64-NEXT:    movl $1, %eax
-; X64-NEXT:    movl %esi, %ecx
-; X64-NEXT:    shll %cl, %eax
-; X64-NEXT:    orl (%rdi), %eax
+; X64-NEXT:    movl (%rdi), %eax
+; X64-NEXT:    btsl %esi, %eax
 ; X64-NEXT:    retq
 ;
 ; X86-LABEL: bts_32_load:
 ; X86:       # %bb.0:
-; X86-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; X86-NEXT:    movb {{[0-9]+}}(%esp), %cl
-; X86-NEXT:    movl $1, %eax
-; X86-NEXT:    shll %cl, %eax
-; X86-NEXT:    orl (%edx), %eax
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movl (%eax), %eax
+; X86-NEXT:    btsl %ecx, %eax
 ; X86-NEXT:    retl
   %1 = load i32, i32* %x
   %2 = shl i32 1, %n
   %3 = or i32 %1, %2
   ret i32 %3
 }
 
 define i32 @btc_32_load(i32* %x, i32 %n) {
 ; X64-LABEL: btc_32_load:
 ; X64:       # %bb.0:
-; X64-NEXT:    movl $1, %eax
-; X64-NEXT:    movl %esi, %ecx
-; X64-NEXT:    shll %cl, %eax
-; X64-NEXT:    xorl (%rdi), %eax
+; X64-NEXT:    movl (%rdi), %eax
+; X64-NEXT:    btcl %esi, %eax
 ; X64-NEXT:    retq
 ;
 ; X86-LABEL: btc_32_load:
 ; X86:       # %bb.0:
-; X86-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; X86-NEXT:    movb {{[0-9]+}}(%esp), %cl
-; X86-NEXT:    movl $1, %eax
-; X86-NEXT:    shll %cl, %eax
-; X86-NEXT:    xorl (%edx), %eax
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movl (%eax), %eax
+; X86-NEXT:    btcl %ecx, %eax
 ; X86-NEXT:    retl
   %1 = load i32, i32* %x
   %2 = shl i32 1, %n
   %3 = xor i32 %1, %2
   ret i32 %3
 }
 
 define i64 @btr_64_load(i64* %x, i64 %n) {
 ; X64-LABEL: btr_64_load:
 ; X64:       # %bb.0:
-; X64-NEXT:    movq $-2, %rax
-; X64-NEXT:    movl %esi, %ecx
-; X64-NEXT:    rolq %cl, %rax
-; X64-NEXT:    andq (%rdi), %rax
+; X64-NEXT:    movq (%rdi), %rax
+; X64-NEXT:    btrq %rsi, %rax
 ; X64-NEXT:    retq
 ;
 ; X86-LABEL: btr_64_load:
 ; X86:       # %bb.0:
 ; X86-NEXT:    pushl %esi
 ; X86-NEXT:    .cfi_def_cfa_offset 8
 ; X86-NEXT:    .cfi_offset %esi, -8
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %esi
; X86-NEXT:    retl
   %3 = xor i64 %2, -1
   %4 = and i64 %1, %3
   ret i64 %4
 }
 
 define i64 @bts_64_load(i64* %x, i64 %n) {
 ; X64-LABEL: bts_64_load:
 ; X64:       # %bb.0:
-; X64-NEXT:    movl $1, %eax
-; X64-NEXT:    movl %esi, %ecx
-; X64-NEXT:    shlq %cl, %rax
-; X64-NEXT:    orq (%rdi), %rax
+; X64-NEXT:    movq (%rdi), %rax
+; X64-NEXT:    btsq %rsi, %rax
 ; X64-NEXT:    retq
 ;
 ; X86-LABEL: bts_64_load:
 ; X86:       # %bb.0:
 ; X86-NEXT:    pushl %esi
 ; X86-NEXT:    .cfi_def_cfa_offset 8
 ; X86-NEXT:    .cfi_offset %esi, -8
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %esi
; X86-NEXT:    retl
   %2 = shl i64 1, %n
   %3 = or i64 %1, %2
   ret i64 %3
 }
 
 define i64 @btc_64_load(i64* %x, i64 %n) {
 ; X64-LABEL: btc_64_load:
 ; X64:       # %bb.0:
-; X64-NEXT:    movl $1, %eax
-; X64-NEXT:    movl %esi, %ecx
-; X64-NEXT:    shlq %cl, %rax
-; X64-NEXT:    xorq (%rdi), %rax
+; X64-NEXT:    movq (%rdi), %rax
+; X64-NEXT:    btcq %rsi, %rax
 ; X64-NEXT:    retq
 ;
 ; X86-LABEL: btc_64_load:
 ; X86:       # %bb.0:
 ; X86-NEXT:    pushl %esi
 ; X86-NEXT:    .cfi_def_cfa_offset 8
 ; X86-NEXT:    .cfi_offset %esi, -8
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %esi