[llvm-mca] Register listeners with stages; remove Pipeline dependency from Stage.

[mattd]

Summary

This patch removes a few callbacks from Pipeline. It comes at the cost of
registering Listeners with all Stages. Not all stages need listeners or issue
callbacks, this registration is a bit redundant. However, as we build-out the
API, this redundancy can disappear.

The main purpose here is to move callback code from the Pipeline and into the
stages that actually issue those callbacks. This removes the back-pointer to
the Pipeline that was put into a few Stage subclasses.

[courbet]

tools/llvm-mca/DispatchStage.cpp

36

This pattern appears quite a lot in various stages. One solution to avoid duplication would be to change the virtual void onXXXEvent(constHWXXXEvent&) callback to virtual void onEvent(const HWXXXEvent&). Then there can be a single notifyEvent function in Stage:

template <typename EventT>
void Stage::notifyEvent(const EventT &Event) const {
  for (HWEventListener *Listener : Listeners)
    Listener->onEvent(Event);
}

What do you think ?

tools/llvm-mca/Stage.h

35

I think this should be made private and only exposed to subclasses as a const accessor:

protected:
  const std::set& getListeners() const { return Listeners; }
private:
  std::set<HWEventListener *> Listeners;

[mattd]

• Added a const accessor for the Stages::Listeners set.

tools/llvm-mca/DispatchStage.cpp

36

I like the idea. However, it feels a bit more of a functional change than what the current patch is trying to achieve. I'd be happy to make this suggested change in separate patch. But if you feel otherwise, I can make the appropriate changes to this patch.

tools/llvm-mca/Stage.h

35

I like that *done*

[courbet]

tools/llvm-mca/DispatchStage.cpp

36

Sounds good to me.

[andreadb]

Nice!

LGTM too.

-Andrea

tools/llvm-mca/DispatchStage.h

 /// and communicating to the simulated instruction scheduler that an instruction
 /// is ready to be scheduled for execution.
 ///
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_TOOLS_LLVM_MCA_DISPATCH_STAGE_H
 #define LLVM_TOOLS_LLVM_MCA_DISPATCH_STAGE_H
 
+#include "HWEventListener.h"
 #include "Instruction.h"
 #include "RegisterFile.h"
 #include "RetireControlUnit.h"
 #include "Stage.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 
 namespace mca {
 
 class WriteState;
 class Scheduler;
-class Pipeline;
 
 // Implements the hardware dispatch logic.
 //
 // This class is responsible for the dispatch stage, in which instructions are
 // dispatched in groups to the Scheduler.  An instruction can be dispatched if
 // the following conditions are met:
 //  1) There are enough entries in the reorder buffer (see class
 //     RetireControlUnit) to write the opcodes associated with the instruction.
 //  2) There are enough temporaries to rename output register operands.
 //  3) There are enough entries available in the used buffered resource(s).
 //
 // The number of micro opcodes that can be dispatched in one cycle is limited by
 // the value of field 'DispatchWidth'. A "dynamic dispatch stall" occurs when
 // processor resources are not available. Dispatch stall events are counted
 // during the entire execution of the code, and displayed by the performance
 // report when flag '-dispatch-stats' is specified.
 //
 // If the number of micro opcodes exceedes DispatchWidth, then the instruction
 // is dispatched in multiple cycles.
 class DispatchStage : public Stage {
   unsigned DispatchWidth;
   unsigned AvailableEntries;
   unsigned CarryOver;
-  Pipeline *Owner;
   const llvm::MCSubtargetInfo &STI;
   RetireControlUnit &RCU;
   RegisterFile &PRF;
   Scheduler ≻
 
   bool checkRCU(const InstRef &IR);
   bool checkPRF(const InstRef &IR);
   bool checkScheduler(const InstRef &IR);
   void dispatch(InstRef IR);
   void updateRAWDependencies(ReadState &RS, const llvm::MCSubtargetInfo &STI);
 
+  void notifyStallEvent(const HWStallEvent &Event);
   void notifyInstructionDispatched(const InstRef &IR,
                                    llvm::ArrayRef<unsigned> UsedPhysRegs);
 
   bool isAvailable(unsigned NumEntries) const {
     return NumEntries <= AvailableEntries || AvailableEntries == DispatchWidth;
   }
 
   bool canDispatch(const InstRef &IR) {
     assert(isAvailable(IR.getInstruction()->getDesc().NumMicroOps));
     return checkRCU(IR) && checkPRF(IR) && checkScheduler(IR);
   }
 
   void collectWrites(llvm::SmallVectorImpl<WriteState *> &Vec,
                      unsigned RegID) const {
     return PRF.collectWrites(Vec, RegID);
   }
 
 public:
-  DispatchStage(Pipeline *P, const llvm::MCSubtargetInfo &Subtarget,
+  DispatchStage(const llvm::MCSubtargetInfo &Subtarget,
                 const llvm::MCRegisterInfo &MRI, unsigned RegisterFileSize,
                 unsigned MaxDispatchWidth, RetireControlUnit &R,
                 RegisterFile &F, Scheduler &Sched)
       : DispatchWidth(MaxDispatchWidth), AvailableEntries(MaxDispatchWidth),
-        CarryOver(0U), Owner(P), STI(Subtarget), RCU(R), PRF(F), SC(Sched) {}
+        CarryOver(0U), STI(Subtarget), RCU(R), PRF(F), SC(Sched) {}
 
   // We can always try to dispatch, so returning false is okay in this case.
   // The retire stage, which controls the RCU, might have items to complete but
   // RetireStage::hasWorkToComplete will check for that case.
   virtual bool hasWorkToComplete() const override final { return false; }
   virtual void preExecute(const InstRef &IR) override final;
   virtual bool execute(InstRef &IR) override final;
   void notifyDispatchStall(const InstRef &IR, unsigned EventType);
 
 #ifndef NDEBUG
   void dump() const;
 #endif
 };
 } // namespace mca
 
 #endif // LLVM_TOOLS_LLVM_MCA_DISPATCH_STAGE_H

tools/llvm-mca/DispatchStage.cpp

 /// The DispatchStage is responsible for updating instruction dependencies
 /// and communicating to the simulated instruction scheduler that an instruction
 /// is ready to be scheduled for execution.
 ///
 //===----------------------------------------------------------------------===//
 
 #include "DispatchStage.h"
 #include "HWEventListener.h"
-#include "Pipeline.h"
 #include "Scheduler.h"
 #include "llvm/Support/Debug.h"
 
 using namespace llvm;
 
 #define DEBUG_TYPE "llvm-mca"
 
 namespace mca {
 
 void DispatchStage::notifyInstructionDispatched(const InstRef &IR,
                                                 ArrayRef<unsigned> UsedRegs) {
   LLVM_DEBUG(dbgs() << "[E] Instruction Dispatched: " << IR << '\n');
-  Owner->notifyInstructionEvent(HWInstructionDispatchedEvent(IR, UsedRegs));
+  notifyInstructionEvent(HWInstructionDispatchedEvent(IR, UsedRegs));
+}
+
+void DispatchStage::notifyStallEvent(const HWStallEvent &Event) {
+  for (HWEventListener *Listener : getListeners())
+    Listener->onStallEvent(Event);
 }
 
 bool DispatchStage::checkPRF(const InstRef &IR) {
   SmallVector<unsigned, 4> RegDefs;
   for (const std::unique_ptr<WriteState> &RegDef :
        IR.getInstruction()->getDefs())
     RegDefs.emplace_back(RegDef->getRegisterID());
 
   const unsigned RegisterMask = PRF.isAvailable(RegDefs);
   // A mask with all zeroes means: register files are available.
   if (RegisterMask) {
-    Owner->notifyStallEvent(HWStallEvent(HWStallEvent::RegisterFileStall, IR));
+    notifyStallEvent(HWStallEvent(HWStallEvent::RegisterFileStall, IR));
     return false;
   }
 
   return true;
 }
 
 bool DispatchStage::checkRCU(const InstRef &IR) {
   const unsigned NumMicroOps = IR.getInstruction()->getDesc().NumMicroOps;
   if (RCU.isAvailable(NumMicroOps))
     return true;
-  Owner->notifyStallEvent(
-      HWStallEvent(HWStallEvent::RetireControlUnitStall, IR));
+  notifyStallEvent(HWStallEvent(HWStallEvent::RetireControlUnitStall, IR));
   return false;
 }
 
 bool DispatchStage::checkScheduler(const InstRef &IR) {
   HWStallEvent::GenericEventType Event;
   const bool Ready = SC.canBeDispatched(IR, Event);
   if (!Ready)
-    Owner->notifyStallEvent(HWStallEvent(Event, IR));
+    notifyStallEvent(HWStallEvent(Event, IR));
   return Ready;
 }
 
 void DispatchStage::updateRAWDependencies(ReadState &RS,
                                           const MCSubtargetInfo &STI) {
   SmallVector<WriteState *, 4> DependentWrites;
 
   collectWrites(DependentWrites, RS.getRegisterID());

tools/llvm-mca/ExecuteStage.h

 #include "Instruction.h"
 #include "RetireControlUnit.h"
 #include "Scheduler.h"
 #include "Stage.h"
 #include "llvm/ADT/ArrayRef.h"
 
 namespace mca {
 
-class Pipeline;
-
 class ExecuteStage : public Stage {
   // Owner will go away when we move listeners/eventing to the stages.
-  Pipeline *Owner;
   RetireControlUnit &RCU;
   Scheduler &HWS;
 
   // The following routines are used to maintain the HWS.
   void reclaimSchedulerResources();
   void updateSchedulerQueues();
   void issueReadyInstructions();
 
 public:
-  ExecuteStage(Pipeline *P, RetireControlUnit &R, Scheduler &S)
-      : Stage(), Owner(P), RCU(R), HWS(S) {}
+  ExecuteStage(RetireControlUnit &R, Scheduler &S) : Stage(), RCU(R), HWS(S) {}
   ExecuteStage(const ExecuteStage &Other) = delete;
   ExecuteStage &operator=(const ExecuteStage &Other) = delete;
 
   // The ExecuteStage will always complete all of its work per call to
   // execute(), so it is never left in a 'to-be-processed' state.
   virtual bool hasWorkToComplete() const override final { return false; }
 
   virtual void preExecute(const InstRef &IR) override final;

tools/llvm-mca/ExecuteStage.cpp

 /// This file defines the execution stage of an instruction pipeline.
 ///
 /// The ExecuteStage is responsible for managing the hardware scheduler
 /// and issuing notifications that an instruction has been executed.
 ///
 //===----------------------------------------------------------------------===//
 
 #include "ExecuteStage.h"
-#include "Pipeline.h"
 #include "Scheduler.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/Support/Debug.h"
 
 #define DEBUG_TYPE "llvm-mca"
 
 namespace mca {
 
if (IR.getInstruction()->isExecuted())
     notifyInstructionExecuted(IR);
 
   return true;
 }
 
 void ExecuteStage::notifyInstructionExecuted(const InstRef &IR) {
   HWS.onInstructionExecuted(IR);
   LLVM_DEBUG(dbgs() << "[E] Instruction Executed: " << IR << '\n');
-  Owner->notifyInstructionEvent(
-      HWInstructionEvent(HWInstructionEvent::Executed, IR));
+  notifyInstructionEvent(HWInstructionEvent(HWInstructionEvent::Executed, IR));
   RCU.onInstructionExecuted(IR.getInstruction()->getRCUTokenID());
 }
 
 void ExecuteStage::notifyInstructionReady(const InstRef &IR) {
   LLVM_DEBUG(dbgs() << "[E] Instruction Ready: " << IR << '\n');
-  Owner->notifyInstructionEvent(
-      HWInstructionEvent(HWInstructionEvent::Ready, IR));
+  notifyInstructionEvent(HWInstructionEvent(HWInstructionEvent::Ready, IR));
 }
 
 void ExecuteStage::notifyResourceAvailable(const ResourceRef &RR) {
-  Owner->notifyResourceAvailable(RR);
+  LLVM_DEBUG(dbgs() << "[E] Resource Available: [" << RR.first << '.'
+                    << RR.second << "]\n");
+  for (HWEventListener *Listener : getListeners())
+    Listener->onResourceAvailable(RR);
 }
 
 void ExecuteStage::notifyInstructionIssued(
     const InstRef &IR, ArrayRef<std::pair<ResourceRef, double>> Used) {
   LLVM_DEBUG({
     dbgs() << "[E] Instruction Issued: " << IR << '\n';
     for (const std::pair<ResourceRef, unsigned> &Resource : Used) {
       dbgs() << "[E] Resource Used: [" << Resource.first.first << '.'
              << Resource.first.second << "]\n";
       dbgs() << "           cycles: " << Resource.second << '\n';
     }
   });
-  Owner->notifyInstructionEvent(HWInstructionIssuedEvent(IR, Used));
+  notifyInstructionEvent(HWInstructionIssuedEvent(IR, Used));
 }
 
 void ExecuteStage::notifyReservedBuffers(ArrayRef<uint64_t> Buffers) {
   if (Buffers.empty())
     return;
 
   SmallVector<unsigned, 4> BufferIDs(Buffers.begin(), Buffers.end());
   std::transform(Buffers.begin(), Buffers.end(), BufferIDs.begin(),
                  [&](uint64_t Op) { return HWS.getResourceID(Op); });
-  Owner->notifyReservedBuffers(BufferIDs);
+  for (HWEventListener *Listener : getListeners())
+    Listener->onReservedBuffers(BufferIDs);
 }
 
 void ExecuteStage::notifyReleasedBuffers(ArrayRef<uint64_t> Buffers) {
   if (Buffers.empty())
     return;
 
   SmallVector<unsigned, 4> BufferIDs(Buffers.begin(), Buffers.end());
   std::transform(Buffers.begin(), Buffers.end(), BufferIDs.begin(),
                  [&](uint64_t Op) { return HWS.getResourceID(Op); });
-  Owner->notifyReleasedBuffers(BufferIDs);
+  for (HWEventListener *Listener : getListeners())
+    Listener->onReleasedBuffers(BufferIDs);
 }
 
 } // namespace mca

tools/llvm-mca/Pipeline.h

public:
   Pipeline(unsigned DispatchWidth = 0, unsigned RegisterFileSize = 0,
            unsigned LoadQueueSize = 0, unsigned StoreQueueSize = 0,
            bool AssumeNoAlias = false)
       : Cycles(0) {}
   void appendStage(std::unique_ptr<Stage> S) { Stages.push_back(std::move(S)); }
   void run();
   void addEventListener(HWEventListener *Listener);
   void notifyCycleBegin(unsigned Cycle);
-  void notifyInstructionEvent(const HWInstructionEvent &Event);
-  void notifyStallEvent(const HWStallEvent &Event);
-  void notifyResourceAvailable(const ResourceRef &RR);
-  void notifyReservedBuffers(llvm::ArrayRef<unsigned> Buffers);
-  void notifyReleasedBuffers(llvm::ArrayRef<unsigned> Buffers);
   void notifyCycleEnd(unsigned Cycle);
 };
 } // namespace mca
 
 #endif // LLVM_TOOLS_LLVM_MCA_PIPELINE_H

tools/llvm-mca/Pipeline.cpp

 
 #define DEBUG_TYPE "llvm-mca"
 
 using namespace llvm;
 
 void Pipeline::addEventListener(HWEventListener *Listener) {
   if (Listener)
     Listeners.insert(Listener);
+  for (auto &S : Stages)
+    S->addListener(Listener);
 }
 
 bool Pipeline::hasWorkToProcess() {
   const auto It = llvm::find_if(Stages, [](const std::unique_ptr<Stage> &S) {
     return S->hasWorkToComplete();
   });
   return It != Stages.end();
 }

 }
 
 void Pipeline::notifyCycleBegin(unsigned Cycle) {
   LLVM_DEBUG(dbgs() << "[E] Cycle begin: " << Cycle << '\n');
   for (HWEventListener *Listener : Listeners)
     Listener->onCycleBegin();
 }
 
-void Pipeline::notifyInstructionEvent(const HWInstructionEvent &Event) {
-  for (HWEventListener *Listener : Listeners)
-    Listener->onInstructionEvent(Event);
-}
-
-void Pipeline::notifyStallEvent(const HWStallEvent &Event) {
-  for (HWEventListener *Listener : Listeners)
-    Listener->onStallEvent(Event);
-}
-
-void Pipeline::notifyResourceAvailable(const ResourceRef &RR) {
-  LLVM_DEBUG(dbgs() << "[E] Resource Available: [" << RR.first << '.'
-                    << RR.second << "]\n");
-  for (HWEventListener *Listener : Listeners)
-    Listener->onResourceAvailable(RR);
-}
-
-void Pipeline::notifyReservedBuffers(ArrayRef<unsigned> Buffers) {
-  for (HWEventListener *Listener : Listeners)
-    Listener->onReservedBuffers(Buffers);
-}
-
-void Pipeline::notifyReleasedBuffers(ArrayRef<unsigned> Buffers) {
-  for (HWEventListener *Listener : Listeners)
-    Listener->onReleasedBuffers(Buffers);
-}
-
 void Pipeline::notifyCycleEnd(unsigned Cycle) {
   LLVM_DEBUG(dbgs() << "[E] Cycle end: " << Cycle << "\n\n");
   for (HWEventListener *Listener : Listeners)
     Listener->onCycleEnd();
 }
 } // namespace mca.

tools/llvm-mca/RetireStage.h

 #define LLVM_TOOLS_LLVM_MCA_RETIRE_STAGE_H
 
 #include "RegisterFile.h"
 #include "RetireControlUnit.h"
 #include "Stage.h"
 
 namespace mca {
 
-class Pipeline;
-
 class RetireStage : public Stage {
   // Owner will go away when we move listeners/eventing to the stages.
-  Pipeline *Owner;
   RetireControlUnit &RCU;
   RegisterFile &PRF;
 
 public:
-  RetireStage(Pipeline *P, RetireControlUnit &R, RegisterFile &F)
-      : Stage(), Owner(P), RCU(R), PRF(F) {}
+  RetireStage(RetireControlUnit &R, RegisterFile &F)
+      : Stage(), RCU(R), PRF(F) {}
   RetireStage(const RetireStage &Other) = delete;
   RetireStage &operator=(const RetireStage &Other) = delete;
 
-  virtual bool hasWorkToComplete() const override final { return !RCU.isEmpty(); }
+  virtual bool hasWorkToComplete() const override final {
+    return !RCU.isEmpty();
+  }
   virtual void preExecute(const InstRef &IR) override final;
   virtual bool execute(InstRef &IR) override final { return true; }
   void notifyInstructionRetired(const InstRef &IR);
   void onInstructionExecuted(unsigned TokenID);
 };
 
 } // namespace mca
 
 #endif // LLVM_TOOLS_LLVM_MCA_RETIRE_STAGE_H

tools/llvm-mca/RetireStage.cpp

 /// This file defines the retire stage of an instruction pipeline.
 /// The RetireStage represents the process logic that interacts with the
 /// simulated RetireControlUnit hardware.
 ///
 //===----------------------------------------------------------------------===//
 
 #include "RetireStage.h"
 #include "HWEventListener.h"
-#include "Pipeline.h"
 #include "llvm/Support/Debug.h"
 
 using namespace llvm;
 
 #define DEBUG_TYPE "llvm-mca"
 
 namespace mca {
 

 
 void RetireStage::notifyInstructionRetired(const InstRef &IR) {
   LLVM_DEBUG(dbgs() << "[E] Instruction Retired: " << IR << '\n');
   SmallVector<unsigned, 4> FreedRegs(PRF.getNumRegisterFiles());
   const InstrDesc &Desc = IR.getInstruction()->getDesc();
 
   for (const std::unique_ptr<WriteState> &WS : IR.getInstruction()->getDefs())
     PRF.removeRegisterWrite(*WS.get(), FreedRegs, !Desc.isZeroLatency());
-  Owner->notifyInstructionEvent(HWInstructionRetiredEvent(IR, FreedRegs));
+  notifyInstructionEvent(HWInstructionRetiredEvent(IR, FreedRegs));
 }
 
 } // namespace mca

tools/llvm-mca/Stage.h

 /// This file defines a stage.
 /// A chain of stages compose an instruction pipeline.
 ///
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_TOOLS_LLVM_MCA_STAGE_H
 #define LLVM_TOOLS_LLVM_MCA_STAGE_H
 
+#include "HWEventListener.h"
 #include <set>
 
 namespace mca {
 
-class HWEventListener;
 class InstRef;
 
 class Stage {
-  std::set<HWEventListener *> Listeners;
   Stage(const Stage &Other) = delete;
   Stage &operator=(const Stage &Other) = delete;
+  std::set<HWEventListener *> Listeners;
+
+protected:
+  const std::set<HWEventListener *> &getListeners() const { return Listeners; }
 
 public:
   Stage();
   virtual ~Stage() = default;
 
   /// Called prior to preExecute to ensure that the stage has items that it
   /// is to process.  For example, a FetchStage might have more instructions
   /// that need to be processed, or a RCU might have items that have yet to
   /// retire.
   virtual bool hasWorkToComplete() const = 0;
 
   /// Called as a setup phase to prepare for the main stage execution.
   virtual void preExecute(const InstRef &IR) {}
 
   /// Called as a cleanup and finalization phase after main stage execution.
   virtual void postExecute(const InstRef &IR) {}
 
   /// The primary action that this stage performs.
   virtual bool execute(InstRef &IR) = 0;
 
   /// Add a listener to receive callbaks during the execution of this stage.
   void addListener(HWEventListener *Listener);
+
+  virtual void notifyInstructionEvent(const HWInstructionEvent &Event);
 };
 
 } // namespace mca
 #endif // LLVM_TOOLS_LLVM_MCA_STAGE_H

tools/llvm-mca/Stage.cpp

 //===---------------------- Stage.cpp ---------------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \file
 ///
 /// This file defines a stage.
 /// A chain of stages compose an instruction pipeline.
 ///
 //===----------------------------------------------------------------------===//
 
 #include "Stage.h"
-#include "llvm/Support/ErrorHandling.h"
 
 namespace mca {
 
 // Pin the vtable here in the implementation file.
 Stage::Stage() {}
 
 void Stage::addListener(HWEventListener *Listener) {
-  llvm_unreachable("Stage-based eventing is not implemented.");
+  Listeners.insert(Listener);
+}
+
+void Stage::notifyInstructionEvent(const HWInstructionEvent &Event) {
+  for (HWEventListener *Listener : Listeners)
+    Listener->onInstructionEvent(Event);
 }
 
 } // namespace mca

tools/llvm-mca/llvm-mca.cpp

for (const std::unique_ptr<mca::CodeRegion> &Region : Regions) {
     mca::RegisterFile PRF(SM, *MRI, RegisterFileSize);
     mca::Scheduler HWS(SM, LoadQueueSize, StoreQueueSize, AssumeNoAlias);
 
     // Create the pipeline and add stages to it.
     auto P = llvm::make_unique<mca::Pipeline>(
         Width, RegisterFileSize, LoadQueueSize, StoreQueueSize, AssumeNoAlias);
     P->appendStage(llvm::make_unique<mca::FetchStage>(IB, S));
     P->appendStage(llvm::make_unique<mca::DispatchStage>(
-        P.get(), *STI, *MRI, RegisterFileSize, Width, RCU, PRF, HWS));
-    P->appendStage(llvm::make_unique<mca::RetireStage>(P.get(), RCU, PRF));
-    P->appendStage(llvm::make_unique<mca::ExecuteStage>(P.get(), RCU, HWS));
+        *STI, *MRI, RegisterFileSize, Width, RCU, PRF, HWS));
+    P->appendStage(llvm::make_unique<mca::RetireStage>(RCU, PRF));
+    P->appendStage(llvm::make_unique<mca::ExecuteStage>(RCU, HWS));
     mca::PipelinePrinter Printer(*P);
 
     if (PrintSummaryView)
       Printer.addView(llvm::make_unique<mca::SummaryView>(SM, S, Width));
 
     if (PrintInstructionInfoView)
       Printer.addView(
           llvm::make_unique<mca::InstructionInfoView>(*STI, *MCII, S, *IP));